Micro-Disk Resonator with Precise Depletion Layer

The present invention generally relates to semiconductor devices and processing methods, and more particularly to micro-disks having a controlled depletion layer thickness.

A data center houses computer systems and associated components, such as telecommunications and storage systems. An important element in a data center includes transceiver devices, which include optoelectronic modulators. Si-based optoelectronic modulators include a vertical P-N junction, which provides low power consumption, low-voltage operation, high-speed, and is compact in size. However, conventional fabrication of a vertical P-N junction micro-disk resonator requires four ion doping/implantation steps on a single silicon-on-insulator (SOI) substrate. The number of ion doping/implantation steps can cause damage, disrupting the crystalline structure of the substrate. This can result in performance issues, which can include difficulty in getting a carrier-free depletion region between P-doped and N-doped regions (resulting in optical loss) and changing carrier concentrations with applied voltage (resulting in output frequency shifts).

In accordance with an embodiment of the present invention, a semiconductor device includes a first doped region of a first conductivity type and a second doped region of a second conductivity type different from the first conductivity type. A fusion bonded insulating layer is disposed between the first doped region and the second doped region, wherein the fusion bonded insulating layer forms a tuned depletion layer disposed between the first doped region and the second doped region to form a P-I-N junction.

In accordance with another embodiment of the present invention, a semiconductor device includes a micro-disk resonator including a P-I-N junction and a bus waveguide spaced apart by a distance. The PIN-junction includes a first doped region of a first conductivity type and a second doped region of a second conductivity type different from the first conductivity type. A fusion bonded insulating layer is disposed between the first doped region and the second doped region. The fusion bonded insulating layer includes two separately formed dielectric layers, wherein the fusion bonded insulating layer forms a tuned depletion layer disposed between the first doped region and the second doped region to form the P-I-N junction.

In accordance with another embodiment of the present invention, a method of fabricating a semiconductor device includes forming a first doped region of a first conductivity type on a first substrate; forming a second doped region of a second conductivity type on a second substrate; depositing a first dielectric layer on the first doped region; depositing a second dielectric layer on the second doped region; bonding the first dielectric layer to the second dielectric layer to form a fusion bonded insulating layer; and forming a P-I-N junction from the first doped region, the fusion bonded insulating layer, and the second doped region.

These and other features and advantages will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.

In accordance with embodiments of the present invention, devices and methods are described which include micro-disk resonators, which are photonic devices that include a circular disk-shaped waveguide fabricated from a high refractive index material such as, e.g., silicon. The disk may be surrounded by a lower refractive index material, often air or silicon dioxide. Light may be coupled into the disk through an adjacent waveguide positioned close to the disk's edge. In some embodiments, micro-disk resonators can have light circulate around the disk's perimeter by total internal reflection. Resonant frequencies of these modes may depend on the disk's size and material properties. When the wavelength of the input light matches a resonant mode, the light may build up in intensity within the disk.

Micro-disk resonators find applications in various photonic devices and systems. Micro-disk resonators may be employed as optical filters, where specific wavelengths are selectively transmitted or reflected. Micro-disk resonators may be employed in optical switching and modulation applications.

The fabrication of micro-disk resonators includes semiconductor processing techniques. This may include lithography to define the disk shape, etching to create the disk structure, and deposition steps to form cladding layers or electrodes for active devices. Micro-disk resonators may be integrated with other photonic and electronic components on a single chip. This integration may enable the development of complex photonic circuits for applications in optical communication, sensing, and information processing.

In accordance with embodiments of the present invention, a micro-disk includes a P-doped-insulator-N-doped (P-I-N) junction, with a precise layer (I layer) between the N-doped and P-doped regions. The precision of the I layer can be achieved by separately forming the N-doped region on a first substrate and a P-doped region on a second separate substrate. For example, a P-doped region (P and P+ doping) can be provided on a first semiconductor-on-insulator (SOI) substrate with optimized process conditions. An N-doped region (N and N+ doping) can be provided on a second SOI substrate with optimized process conditions.

An insulating layer can be deposited on both SOI substrate surfaces using a high precision process, e.g., a plasma enhanced chemical vapor deposition (PECVD) process. A planarization process, such as chemical mechanical polishing (CMP) can be employed to prepare surfaces of the dielectric layer formed on the two SOI substrates for fusion bonding. The insulating layers can include barrier layers, such as, e.g., SiN or SiCN, etc. A final thickness of the dielectric layer can be precisely controlled, and can include a thickness of, e.g., 2-5 nm to a few microns (e.g., 2-3 microns), depending on the N-P junction depletion layer thickness needed.

One substrate is flipped to permit the dielectric layers to be in contact, and the substrates are bonded at the dielectric layers using, e.g., a fusion bonding process. A top substrate is removed to expose a top doped region. A bus waveguide and an N-P junction are patterned in the top doped region using an anisotropic etch (e.g., reactive ion etching (RIE)). Metal contacts are fabricated to both the N-doped region and the P-doped region.

A micro-disk based on a vertical P-I-N junction in accordance with embodiments of the present invention includes a precise depletion layer between N-doped and P-doped regions. P-doped and N-doped regions are separately fabricated on two SOI substrates with optimized process conditions, then fusion bonded to make a vertical P-I-N junction where the depletion layer/barrier eliminates carrier-induced optical loss and reduces or eliminates frequency shift.

1 FIG. 100 104 103 103 103 102 104 108 110 122 103 102 2 Referring now to the drawings in which like numerals represent the same or similar elements and initially to, a micro-disk resonator 150 is shown in accordance with an embodiment of the present invention. The micro-disk resonator 150 includes a micro-disk, which is formed on a silicon-on-insulator (SOI) substrate. The silicon-on-insulator (SOI) substrate may include a layered structure including a thin layer, e.g., of silicon, on top of an insulating layer. The insulating layercan include, e.g., silicon dioxide (SiO), also referred to as a buried oxide (BOX), although other dielectric materials can be employed. The insulating layermay be formed on a handle wafer(or substrate). The thin layer, can be referred to as a device layer used for fabricating semiconductor devices, and in particular, for forming doped regions,and bus waveguidewhile the insulating layerprovides electrical isolation from the underlying handle wafer.

102 102 102 102 The handle wafercan have a single layer or multiple layers. The handle wafercan include a monocrystalline semiconductor. In one example, the handle wafercan include a silicon-containing material. Illustrative examples of Si-containing materials suitable for the handle wafercan include, but are not limited to, Si, SiGe, SiGeC, SiC and multi-layers thereof. Although silicon is the predominantly used semiconductor material in wafer fabrication, alternative semiconductor materials can be employed as additional layers, such as, but not limited to, germanium, gallium arsenide, gallium nitride, silicon germanium, cadmium telluride, zinc selenide, etc.

104 104 104 104 104 104 While the thin layeris preferably silicon, the thin layercan include other semiconductor materials. For example, the thin layercan have a single layer or multiple layers. The thin layercan include a monocrystalline semiconductor. In one example, the thin layercan include a silicon-containing material. Illustrative examples of Si-containing materials suitable for the thin layercan include, but are not limited to, Si, SiGe, SiGeC, SiC and multi-layers thereof. In other embodiments, III-V or other semiconductor materials can be employed.

126 126 104 126 114 116 124 A thin layeris included from another SOI substrate as will be described herein. The thin layercan include the same or different materials as the thin layer. The thin layeris employed in forming devices, and in particular, for forming doped regions,and bus waveguide.

108 110 122 114 116 124 112 112 112 112 112 100 Doped regions,and bus waveguideand doped regions,and bus waveguideare separated by a bonding layer. The bonding layeris formed from portions on separate substrates using high precision processing to provide a highly precise thickness. The thickness of the bonding layercan be controlled or tuned to within a 1- 2 nm and includes an overall thickness of between about 2 nm and about 3 microns. In a particularly useful embodiment, the bonding layercan be about 10 nm. The thickness of the bonding layerwill depend on the function of the micro-diskand the optical signals for which it is designed to handle.

112 108 110 122 114 116 124 112 108 114 108 114 The bonding layerprovides an insulator disposed between doped regions,and bus waveguideand doped regions,and bus waveguide. The bonding layerfunctions as a depletion layer between doped regionsand. Doped regions,and the bonding layer form a P-I-N junction, where the precision of the depletion layer in the P-I-N junction provides a more stable carrier concentration leading to a reduction in optical loss and a reduction in frequency shift.

108 114 110 108 110 108 120 116 114 116 114 118 In an embodiment, doped regioncan include an N or N+ doped region and doped regioncan include a P or P+ doped region or vice versa. A contact pad (doped region) is integrally formed with the doped regionand includes a same dopant conductivity. Contact pad (doped region) can include a higher dopant concentration than the doped regionto improve electrical conductivity with a contact. A contact pad (doped region) is integrally formed with the doped region(main portion) and includes a same dopant conductivity. Contact pad (doped region) can include a higher dopant concentration than the doped region(main portion) to improve electrical conductivity with a contact.

122 124 108 114 122 124 100 122 124 100 122 124 100 Bus waveguidesandcorrespond to doped regionsand, respectively. Bus waveguidesandare used to couple light into and out of the micro-disk. The bus waveguidesandcan include a linear waveguide positioned in close proximity to the edge of the micro-disk. This proximity permits for evanescent coupling between the bus waveguidesandand the micro-disk.

122 124 100 122 124 The bus waveguidesandcan be fabricated from the same high refractive index material as the micro-disk, such as silicon, or it may be made from a different material with suitable optical properties. In some cases, the bus waveguide,can be designed to have a width and height that support single-mode operation at a wavelength of interest.

128 122 124 100 128 A gapbetween the bus waveguides,and the micro-diskaffects coupling efficiency. This gapcan be on the order of hundreds of nanometers, although the exact dimension may depend on factors such as the operating wavelength, material properties, and desired coupling strength.

122 124 100 122 124 100 122 124 100 122 124 100 In some embodiments, the bus waveguides,can be tapered as they approach the micro-diskto improve mode matching and increase coupling efficiency. The bus waveguides,can be curved to wrap partially around the micro-disk, potentially increasing the interaction length and permitting stronger coupling. The position of the bus waveguides,relative to the micro-diskcan be precisely controlled during fabrication to achieve the desired coupling characteristics. Multiple bus waveguides,can be used with a single micro-diskto enable more complex functionalities, such as add-drop filtering or bidirectional coupling.

127 150 122 124 127 122 124 A dielectric layeris formed over the micro-disk resonatorto protect components and to function as a cladding material for the bus waveguides,. The dielectric layercan be deposited over the bus waveguides,to provide optical confinement and protect the waveguide structures. The cladding material may have a lower refractive index than the bus waveguides core to ensure light remains guided within the waveguide. Materials such as silicon dioxide, silicon nitride, or polymers may be employed as cladding layers.

150 122 124 150 2 The micro-disk resonatorin accordance with embodiments of the present invention provides an optical device structure with a stacked structure having a P doped layer and an N doped separated by an insulation layer to form a P-I-N junction. P+ doped material of one of the contact pads is connected with the P doped layer, and N+ doped material of one of the contact pads is connected with N doped layer for better contact. The P doped layer and the N doped layer include monocrystalline semiconductor material and are aligned without any or a minimum shift therebetween. This means the main portion of the doped layers (N and P) share a same footprint without a relative offset between the doped layers. This results in more carrier uniformity at the junction and therefore better performance. An insulation layer or bonding layer between the P doped layer and the N doped layer can be a few nanometers thick (e.g., 2-5 nm) and include, e.g., SiOor SiN. The P-I-N junction structure is provided on a same device as bus waveguides,to form the micro-disk resonator.

2 FIG. 210 220 220 210 203 202 126 210 108 110 108 110 108 110 Referring to, a method for fabricating a micro-disk resonator is described and shown in accordance with embodiments of the present invention. A first semiconductor-on-insulator (SOI) substrateand a second SOI substrateare separately provided. The second SOI substrateincludes a similar structure and materials as the first SOI substrateincluding an insulating layerbetween a handle waferand the thin layer. The first SOI substrateis masked to pattern doped regions,. The doped regionsandcan be doped together and/or separately using ion implantation methods or other doping methods. In an embodiment, the doped regioncan include N type dopants while the doped regioncan include a higher concentration of N type dopants (e.g., P, As, etc.).

220 114 116 114 116 114 116 210 220 The second SOI substrateis masked to pattern doped regions,. The doped regionsandcan be doped together and/or separately using ion implantation methods or other doping methods. In an embodiment, the doped regioncan include P type dopants while the doped regioncan include a higher concentration of P type dopants (e.g., B, Ga, etc.). Because the first SOI substrateand the second SOI substrateare processed separately optimized process conditions are provided for each doping type resulting in higher quality semiconductor structures.

3 FIG. 212 210 104 108 110 214 220 126 114 116 212 214 210 220 Referring to, a dielectric layeris deposited on the first SOI substrateover the thin layer, which includes the doped regionsand. A dielectric layeris deposited on the second SOI substrateover the thin layer, which includes the doped regionsand. The dielectric layersandcan be deposited on both SOI substrate surfaces (SOI substrateand SOI substrate) using a high precision process, such as plasma enhanced chemical vapor deposition (PECVD).

212 214 210 220 104 126 212 214 The surfaces of the dielectric layersandon both SOI substrates,are planarized using a process such as chemical mechanical polishing (CMP) to prepare them for fusion bonding. The CMP process permits the layer’s thickness to be honed to collectively provide a precise insulating layer between the thin layersand. The collective thickness of the two dielectric layersandcan be maintained to within 2-5 nm with an overall thickness of between about 10 nm to a few microns (3-5 microns), as needed.

4 FIG. 220 210 212 214 112 Referring to, the second SOI substrateis flipped and fusion bonded to the first SOI substatecombining dielectric layersandto form bonding layer. This includes flipping one substrate and aligning it with the other substrate so that the dielectric layers are in contact. Fusion bonding includes bringing two highly polished and cleaned dielectric surfaces into close contact and allowing them to adhere through van der Waals forces and chemical bonds. The process may begin with surface preparation, which can include chemical cleaning to remove contaminants and activation treatments to increase surface reactivity. In some cases, the surfaces may be exposed to plasma or chemical solutions to create hydroxyl groups that can form strong bonds.

212 214 The dielectric layersandmay then be aligned and pressed together under controlled temperature and pressure conditions. The initial contact may occur at room temperature, with subsequent annealing at elevated temperatures to strengthen the bond. The annealing temperature may vary depending on the materials involved, but can range from 200°C to over 1000°C for some embodiments.

212 214 During the annealing process, the interface between the dielectric layersandundergoes chemical reactions, leading to the formation of covalent bonds. For silicon dioxide layers, this can include condensation of silanol groups (Si-OH) to form siloxane bonds (Si-O-Si). The bonding process may also cause the diffusion of water molecules away from the interface, further strengthening the bond.

In some embodiments, the fusion bonding process may be performed in a vacuum or inert atmosphere to prevent the formation of voids or trapped gases at the interface. The bonding strength may be influenced by factors such as surface roughness, cleanliness, and the presence of intermediate layers.

212 214 112 112 Fusion bonding of dielectric layers,maintains a thickness of the two layers to a high precision to form the bonding layer. The bonding layeris a high-quality interface that provides a depletion layer for the P-I-N junction.

112 212 214 The depletion layer thickness in the P-I-N junction may be precisely controlled through the fabrication process of the micro-disk resonator. The thickness of the depletion layer or the bonding layercan be tuned by adjusting various parameters during the fabrication process, e.g., by varying the deposition conditions of the dielectric layers on each substrate. For example, the PECVD process used to deposit the dielectric layersandmay be optimized by adjusting parameters such as gas flow rates, chamber pressure, RF power, and deposition time to achieve the desired layer thickness.

212 214 Additionally, the planarization process applied to the dielectric layersandprior to bonding may be used to fine-tune the thickness. CMP may be employed to precisely control the final thickness of each dielectric layer before bonding. The CMP process parameters, such as polishing time, pressure, and slurry composition, may be adjusted to achieve the desired thickness with high precision. The bonding process can include high temperatures and pressures, which can cause slight changes in the thickness of the bonded layers. By carefully controlling the bonding parameters, such as temperature, pressure, and duration, the final thickness of the insulating layer may be further tuned.

112 The ability to precisely control the depletion layer thickness to provide a tuned depletion layer (bonding layer) permits optimization of the micro-disk resonator's performance. In some cases, a thinner depletion layer may result in stronger coupling between the P and N regions, potentially leading to improved modulation efficiency. Conversely, a thicker depletion layer may provide better electrical isolation and reduced capacitance, which could be beneficial for high-speed operation. Furthermore, the thickness of the depletion layer may be tailored to specific wavelengths of light used in the micro-disk resonator. By adjusting the depletion layer thickness, the optical properties of the P-I-N junction may be tuned to optimize performance for particular applications or operating conditions.

5 FIG. 202 220 203 Referring to, the handle waferof the second substrateis removed by an etch process. The etch process can include, e.g., a wet etch or dry etch. The etch process stops on the insulating layer.

6 FIG. 112 103 230 122 124 232 203 122 124 232 Referring to, a patterning process or processes are performed to etch down to the bonding layerand insulating layerin regions. The etch process patterns the bus waveguidesanda precise distance from the P-I-N junction. The patterning process(es) can include the use of a photoresist mask and lithography process. A photoresist layer (not shown) may be deposited on top of the insulating layer. The photoresist can then be exposed to light through a photomask that defines the desired pattern for the bus waveguides,and P-I-N junction.

230 122 124 232 122 124 232 122 124 232 After exposure and development, the photoresist mask may leave openings corresponding to the regionswhere the bus waveguides,and P-I-N junctionare to be formed. The mask pattern may be designed to position the bus waveguides,at a specific distance from the P-I-N junction, which can be on the order of hundreds of nanometers. This distance may be precisely controlled through careful design of the photomask. An anisotropic etching process, such as reactive ion etching (RIE), may then be used to transfer the pattern from the photoresist mask to the underlying semiconductor layers. The photoresist mask may be removed after etching, leaving the bus waveguides,and the P-I-N junctionpatterned.

7 FIG. 127 203 127 122 124 127 122 124 122 124 127 Referring to, a dielectric layeris deposited over the micro-disk resonator and planarized to the insulating layer. The dielectric layercan function as a cladding layer over the micro-disk resonator to protect components and provide optical confinement for the bus waveguides,. The dielectric layercan be formed from materials such as silicon dioxide, silicon nitride, or polymers, which may have a lower refractive index than the core of the bus waveguides,. This layer can serve to enhance the optical confinement within the bus waveguides,and protect the underlying structures from environmental factors and mechanical damage. The dielectric layercan be deposited by CVD, PECVD, spin coating, etc. depending on the material and desired properties.

8 FIG. 236 238 232 236 108 110 238 114 116 Referring to, metal contactsandare formed to doped portions of the P-I-N junction. The metal contactconnects to the doped regionthrough contact pad (doped region). The metal contactconnects to the doped regionthrough the contact pad (doped region).

236 238 127 110 116 236 238 The metal contactsandcan be formed by patterning and etching the dielectric layerto form contact openings that expose the contact pads (doped regionsand). A conductive fill is performed to fill the contact openings. The conductive fill can include materials, such as, e.g., W, Cu, Co, and alloys or combinations of these and other conductive materials. In a particularly useful embodiment, the conductive fill includes W. The conductive fill can be formed using a deposition method, such as, e.g., CVD, PECVD, ALD or any other suitable deposition method. The conductive fill is planarized, e.g., by CMP, to form the metal contactsand.

Exemplary applications/uses to which the present invention can be applied include, but are not limited to semiconductor devices. Semiconductor devices can include processors, memory devices, application specific integrated circuits (ASICs), logic circuits or devices, combinations of these and any other circuit device. In such devices, one or more semiconductor devices can be included in a central processing unit, a graphics processing unit, and/or a separate processor- or computing element-based controller (e.g., logic gates, etc.). The semiconductor devices can include one or more on-board memories (e.g., caches, dedicated memory arrays, read only memory, etc.). In some embodiments, the semiconductor devices can include one or more memories that can be on or off board or that can be dedicated for use by a hardware processor subsystem (e.g., ROM, RAM, basic input/output system (BIOS), etc.).

In some embodiments, the semiconductor devices can include and execute one or more software elements. The one or more software elements can include an operating system and/or one or more applications and/or specific code to achieve a specified result. In still other embodiments, the semiconductor devices can include dedicated, specialized circuitry that perform one or more electronic processing functions to achieve a specified result. Such circuitry can include one or more field programmable gate arrays (FPGAs), and/or programmable applications programmable logic arrays (PLAs).

It is to be understood that aspects of the present invention will be described in terms of a given illustrative architecture; however, other architectures, structures, substrate materials and process features and steps can be varied within the scope of aspects of the present invention.

It will also be understood that when an element such as a layer, region or substrate is referred to as being “on” or “over” another element, it can be directly on the other element or intervening elements can also be present. In contrast, when an element is referred to as being “directly on” or “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements can be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.

The present embodiments can include a design for an integrated circuit chip, which can be created in a graphical computer programming language, and stored in a computer storage medium (such as a disk, tape, physical hard drive, or virtual hard drive such as in a storage access network). If the designer does not fabricate chips or the photolithographic masks used to fabricate chips, the designer can transmit the resulting design by physical means (e.g., by providing a copy of the storage medium storing the design) or electronically (e.g., through the Internet) to such entities, directly or indirectly. The stored design is then converted into the appropriate format (e.g., GDSII) for the fabrication of photolithographic masks, which typically include multiple copies of the chip design in question that are to be formed on a wafer. The photolithographic masks are utilized to define areas of the wafer (and/or the layers thereon) to be etched or otherwise processed.

Methods described herein can be used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case, the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case, the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.

x 1-x It should also be understood that material compounds will be described in terms of listed elements, e.g., SiGe. These compounds include different proportions of the elements within the compound, e.g., SiGe includes SiGewhere x is less than or equal to 1, etc. In addition, other elements can be included in the compound and still function in accordance with the present principles. The compounds with additional elements will be referred to herein as alloys.

Reference in the specification to “one embodiment” or “an embodiment”, as well as other variations thereof, means that a particular feature, structure, characteristic, and so forth described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrase “in one embodiment” or “in an embodiment”, as well any other variations, appearing in various places throughout the specification are not necessarily all referring to the same embodiment.

It is to be appreciated that the use of any of the following “/”, “and/or”, and “at least one of”, for example, in the cases of “A/B”, “A and/or B” and “at least one of A and B”, is intended to encompass the selection of the first listed option (A) only, or the selection of the second listed option (B) only, or the selection of both options (A and B). As a further example, in the cases of “A, B, and/or C” and “at least one of A, B, and C”, such phrasing is intended to encompass the selection of the first listed option (A) only, or the selection of the second listed option (B) only, or the selection of the third listed option (C) only, or the selection of the first and the second listed options (A and B) only, or the selection of the first and third listed options (A and C) only, or the selection of the second and third listed options (B and C) only, or the selection of all three options (A and B and C). This can be extended, as readily apparent by one of ordinary skill in this and related arts, for as many items listed.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes” and/or “including,” when used herein, specify the presence of stated features, integers, steps, operations, elements and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and/or groups thereof.

Spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper,” “top,” “bottom” and the like, can be used herein for ease of description to describe one element's or feature's relationship to another element(s) or feature(s) as illustrated in the FIGS. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the FIGS. For example, if the device in the FIGS. is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the term “below” can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein can be interpreted accordingly. In addition, it will also be understood that when a layer is referred to as being “between” two layers, it can be the only layer between the two layers, or one or more intervening layers can also be present.

It will be understood that, although the terms first, second, etc. can be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Thus, a first element discussed below could be termed a second element without departing from the scope of the present concept.

Having described preferred embodiments of devices and methods (which are intended to be illustrative and not limiting), it is noted that modifications and variations can be made by persons skilled in the art in light of the above teachings. It is therefore to be understood that changes may be made in the particular embodiments disclosed which are within the scope of the invention as outlined by the appended claims. Having thus described aspects of the invention, with the details and particularity required by the patent laws, what is claimed and desired protected by Letters Patent is set forth in the appended claims.