Built-In Self Test (bist) for a Memory Which Utilizes Redundancy Repair

This disclosure relates generally to memories, and more specifically, to built-in self test (BIST) for a memory which utilizes redundancy repair.

Memories, such as static random access memories (SRAMs), commonly use redundancy repair. For example, the bit cells of these memories are typically arranged in an array of rows and columns, in which the rows are addressed by corresponding word lines and the columns are addressed by corresponding bit lines. A bit cell with a corresponding storage element is located at the intersection of each row and column. A column or set of columns may be defective, in which case replacement columns can be used to perform column repair upon a read or write access to the memory. These memories typically include a set of redundant columns, in which the redundant columns can be selected and utilized as a replacement column during memory repair.

It is often desirable to test the redundant columns of a repairable memory. However, this testing typically requires two passes for testing the memory, in which a first testing pass through the memory is performed with all redundant columns disabled, and then a second testing pass through the memory is performed with repair enabled so as to test the redundant columns. The need for two testing passes at each testing condition (e.g. at room temperature) consumes additional test time. Therefore, a need exists for improved testing of the redundant columns, which may result in reduced test time.

In one aspect, a memory (such as an SRAM) includes, as part of its data array, redundant columns which can be used during normal memory operation to replace defective columns in response to read or write accesses which access bit locations from one or more defective columns. Furthermore, circuitry within the memory, such as within a control circuit of the memory, implements one or more scan chains utilized during scan mode, in which each scan chain has an input coupled to a scan input pin of the memory and an output coupled to a scan output pin of the memory such that scan data can be shifted into and out of the scan chains during scan mode. However, when not in scan mode, the scan input and output pins are not typically being utilized. Note that scan mode is typically disabled during normal memory operation as well as during a test mode in which bult-in self test (BIST) is performed.

In one embodiment, repair circuitry within the memory includes a multiplexer (MUX) corresponding to each data line of the data array which is configured to provide access to either the data line or an alternate data line. For example, when memory repair is enabled during normal memory operation, a redundant column can repair a defective column by being multiplexed into an adjacent column (in which the defective column is disabled from communicating with its corresponding data line by its corresponding MUX). However, when not in normal memory operation, such as during a test mode (such as BIST), it is desirable to access the data lines corresponding to the data array of the memory, including those corresponding to the redundant columns of the data array. Therefore, in addition to multiplexing the redundant column to an adjacent column for performing repair during normal memory operation, additional logic is present to access the redundant columns during BIST. In one embodiment, a data line corresponding to the redundant columns is coupled through additional MUXes located at the scan output and input pins, which are used in scan mode but are not in use during BIST. In this manner, when not in scan mode, these additional MUXes enable the data line corresponding to the redundant column to be read or written in parallel with the other data lines of the data array during BIST, thus preventing the need for multiple test passes. Further, these additional MUXes can be controlled by a logical combination of control signals (including, e.g. unused repair or scan control signals) so as to repurpose the scan input and output pins for use by BIST circuitry to test the redundant columns in parallel with the remaining columns of the data array.

1 FIG. 100 102 104 106 110 114 116 112 128 130 130 128 100 100 110 110 110 100 100 100 100 illustrates, in partial schematic and partial block diagram form, a memory(e.g. an SRAM) which includes a data array, a row decoder, a column decoder, memory control circuitry, repair control circuitry, repair circuitry, read/write circuitry, scan mode control circuitry, and BIST circuitry. Note that BIST circuitryand scan mode control circuitmay be located outside memory. Memoryincludes memory pins coupled to memory control circuitry(e.g. a scan_in PIN configured to receive a scan input signal, such as scan chain input data, to a scan chain during scan mode and a scan_out PIN configured to provide a scan output signal, such as scan chain output data, from a scan chain during scan mode). Memory control circuitryis also configured to receive a memory access address (ADDR) from a requestor, write data from the requestor when an access request is a write access, and corresponding control signals (CONTROL, such as a read/write (R/W) indicator). Memory control circuitryis also configured to return read data to the requestor when an access is a read access. The write data can be an N-bit input value received as DIN[N−1:0] and the read data can be returned as an N-bit output value provided as DOUT[N−1:0], in which N corresponds to the size of an addressable data element of memory. For example, based on the design of memory, N can correspond to a word (e.g. 16 bits or 32 bits) or a double word (e.g. 32 bits or 64 bits). For the descriptions herein, it will be assumed that the addressable data element of memoryis a word, in which N is 16 bits, such that each read or write access to memoryduring normal memory operation loads or stores a word (e.g. 16 bits).

110 128 128 128 110 130 100 128 128 100 110 130 130 100 100 100 128 110 110 Memory control circuitryis also configured to receive a scan enable (SE) signal from scan mode control circuit, receive an internal scan input signal (scan_in INT) from scan mode control circuitry, and provide an internal scan output signal (scan_out INT) to scan mode control circuitry. Memory control circuitryis also configured to communicate with BIST circuitry. As will be described in more detail below, during test mode in which BIST is performed, the scan pins (scan_out PIN and scan_in PIN) are unused by memory. Therefore, in one embodiment, during scan testing (i.e. when in scan mode), the scan_in and scan_out pins are configured to receive scan_in INT from scan mode controland provide scan_out INT from scan mode control, respectively, in which scan_in INT corresponds to an input of a scan chain and scan_out INT corresponds to an output of a scan chain (in which the scan chains are located within memory, such as within memory control circuitry). However, when not in scan mode but in test mode, scan_in PIN is instead configured to receive input information for use during BIST testing by BIST circuitry, and provide output information for use during BIST testing to BIST circuitry. Note that each of scan_in PIN, scan_out PIN, scan_in INT, scan_out INT are configured to communicate a single bit of scan chain data, corresponding to a single scan chain of memory. However, memorymay include any number of scan chains and may therefore include a scan_in PIN, scan_out PIN, scan_in INT, and scan_out INT for each scan chain. Memorymay also have visibility to a scan mode pin (SE_PIN) of scan mode control, provided as SE to memory control, which is used to selectively enable scan mode. When SE_PIN is enabled at a logic level one, SE is also provided as a logic level one to memory control circuitry, and the scan_in PIN and scan_out PIN are used for scan testing, but when SE_PIN is disabled at a logic level zero, SE is also a logic level zero and values used during BIST testing can instead be input into and output from these pins.

102 100 102 0 0 102 104 106 112 0,0 0,K-1 N-1,0 N-1,K-1 2,0 2, K-1 2,4 N,0 N,K-1 rd th rd Referring back to data arrayof memory, data arrayincludes M rows, each having a corresponding word line, WL-WLM−1 of WLs, and N input/output (IO) groups, including IO-ION−1 and a redundant IO. Each IO group (also referred to as a column group) includes K columns, each column having a corresponding bit line (BL). Therefore, the bit lines are grouped into N−1 groups of K bit lines, resulting in BL-BLthrough BL-BL, in which each BL label is followed by two indices, the first index indicating one of the N groups and the second index indicating one of the K bit lines within the group. For example, BL-BLidentifies the 3group of K bit lines in which, for example, BLrefers to the 5bit line in this 3group of K bit lines. Redundant IO also includes K bit lines, labeled as BL-BL. A bit cell of data arrayis located at each intersection of a word line and a bit line. Row decodeis coupled to the word lines, and column decodeis coupled between the bit lines and read/write circuitry. As indicated above, N is assumed to be 16 bits in the embodiments described herein, and, in one embodiment, K=8. However, in alternate embodiments, N and K can be any value. In yet another embodiment, K=1 such that each IO group only includes a single column (i.e. a single bit line).

110 104 106 100 102 104 106 0 104 106 110 104 106 102 106 1 FIG. Control circuitryreceives ADDR, CONTROL, and write data for write accesses, and is coupled to both row decodeand column decode. The access address for a read or write to memorymay be referred to herein as a memory access address, in which each access address, during normal operation, accesses N bit cells of arrayfor writing a word of data or reading a word of data. For reads and writes during normal operation, row decodeactivates one word line (one of the WLs), based on a first portion of a received access address, and column decodeselects one bit line from each of the N+1 IO groups of K bit lines to couple to a corresponding data line of DL-DLN, based on a second portion of the access address. Note that each of row decodeand column decodecan be implemented as known in the art. Control circuitryparses the access address and provides the appropriate first portion to row decodeand column decode, and can provide timing information and any other control signals, as necessary and as known in the art, for performing the writes and reads of array. Note that only bit lines are illustrated in, but it is understood that each bit line may also have a corresponding source line, or a complementary bit line, such that each data line at the output of column decodemay include only a bit line, only a source line, a bit line/source line pair, or a bit line/complementary bit line pair, depending on the implementation of the read and write circuitries. As used herein, each bit line or source line may be referred to generically as a column line.

116 0 0 102 0 0 0 114 0 112 102 110 112 102 110 Repair circuitryis coupled between DL-DLN and access data lines Q()-Q(N−1), in which, during normal memory operation, the access data lines correspond to an accessed N-bit word (w) location of data array. Therefore, Q[N−1:0] is equivalent to Q(w). If repair is not enabled, then Q(w) simply corresponds to DL-DLN−1. If repair is enabled, then Q(w) corresponds to N bits of DL-DLN (in which DLN is used as a column replacement for one of DL-DLN−1, as indicated by repair control circuitry). Note that redundant IO provides DLN which corresponds to one bit beyond an N-bit word, such that DLN is provided as Q(N) (also referred to as Q(w+1)). Q()-Q(N) are provided to read/write circuitry. During normal memory operation, Q(w) (i.e. Q[N−1:0]) corresponds to an accessed N-bit word (w) location in data array. For a write access, write data is provided by memory control circuitryas DIN[N−1:0] to read/write circuitrywhich is then written into data arrayvia Q[N−1:0], and for a read access, read data is sensed on Q[N−1:0] and returned to memory control circuitryas DOUT[N−1:0].

116 114 0 114 116 118 120 122 124 126 0 0 1 116 114 116 116 Repair circuitryand corresponding repair control circuitryallow for redundant IO, for a particular access, to replace a defective IO (which can be one of IO-ION−1). Repair control circuitryis coupled to memory input pins to receive repair enable signals which indicate whether repair is enabled (r_en) and if so, which columns should be repaired (r_d). In the illustrated embodiment, repair circuitryincludes a corresponding MUX (e.g. MUXes,,,, and) for each of column groups IO-ION−1 to receive, at a first input, a corresponding data line from the group (DL-DLN−1, respectively). Each corresponding MUX also receives, at a second input, an alternate (i.e. replacement) data line from another column group. In the illustrated embodiment, the alternate data line corresponds to the data line of an immediately neighboring column group such that the corresponding MUXes receive, at the second inputs, DL-DLN, respectively. Therefore, in the case that repair is enabled, the data line corresponding to the defective IO group is multiplexed out by repair circuitrywhile DLN is multiplexed in. Repair controlcan determine the inputs to the MUXes of repair circuitryand provide control signals to the MUXes of repair circuitrybased on the values of r_en and r_d.

0 0 118 120 122 124 126 1 1 1 120 1 114 120 2 2 1 118 126 1 1 0 116 114 For example, in the case in which repair is not enabled (e.g. r_en is negated to a logic level zero), or there are no defective IO groups, DL-DLN−1 is connected to Q()-Q(N−1) via the corresponding MUXes (e.g. MUXes,,,, and) in which the control signals of the MUXes are set to a first logic value so as to select the data line from the corresponding group. For example, in this case, the data line from group IO(DL) is selected and connected to Q() via MUX. If, however, repair is enabled (e.g. r_en is asserted to a logic level one) and IOis indicated as defective to repair control circuitry(via r_d), the control signal of the corresponding MUX (e.g. MUX) would be set to a second logic value so as to instead select the data line from the neighboring adjacent group (e.g. DLof IO) to be connected to Q(). The control signal of all MUXes to the right of MUXwould similarly be set to the second control value to select the neighboring adjacent group, and in the case of the last IO group (ION−1), MUXwould select DLN of the redundant IO to be connected to Q(N−1). In this manner, IO(and thus DL) is multiplexed out and the redundant IO (and thus DLN) is multiplexed in when accessing the accessed data lines Q()-Q(N−1). Note that any known circuitry may be used to implement repair circuitryand repair control circuitry, in which any known method may be used to multiplex in a redundant IO (or to otherwise replace a defective IO with a redundant IO).

112 0 112 110 112 0 102 112 0 112 106 0 In one embodiment, read/write circuitryincludes a set of N+1 sense amplifiers to read (i.e. sense) the data bit values on Q()-Q(N). For a read access, read/write circuitryoutputs an N-bit read value as DOUT[N−1:0]. The sensed value of Q(N) can be provided, for example, as Q(N)_OUT to memory controlRead/write circuitrymay include appropriate bit line (and, if needed, source line) drivers coupled to Q()-Q(N) to program write data into array. For a write access, read/write circuitrycan set Q()-Q(N−1) based on DIN[N−1:0]. Read/write circuitrymay also receive a data value for Q(N) as Q(N)_IN to be programmed into the redundant IO. The read and write circuitries can be implemented as known in the art. In another embodiment, a set of N+1 sense amplifiers may alternatively be located within column decode, and provide signals DL-DLN at their respective sense amplifier outputs.

100 102 106 102 102 102 102 1 FIG. 1 FIG. 1 FIG. Note that memoryofis a simplified memory, having the elements needed to describe embodiments of the present invention, and may therefore include further elements and aspects not illustrated and not pertinent to the embodiments described herein. For example, as mentioned above, data arraymay also include a source line for each column (corresponding to each bit line) which may also be coupled to column decode, in which the source lines, like the bit lines, are coupled to the bit cells of data array. The descriptions herein are done with respect to the bit lines of data array, but could apply to any column line (bit line or source line). Also, note that the illustrated embodiment ofmay only illustrated a portion of data array, in which the illustrated portion may be half of one quarter of the full data array. Also, although each read or write access to data arrayofaccesses an N-bit word, in alternate embodiments, a word may include more or fewer bits, or each access may access more words than just one word.

100 114 116 114 100 100 100 100 100 During normal operation of memory, repair control circuitrycan either enable or disable repair circuitrybased on input r_en. If repair is enabled, repair control circuitryalso receives input r_d[x:0] in which r_d may be an x+1 bit signal which identifies which IO group will be repaired (multiplexed out or replaced) by the redundant IO. In addition to normal operation, memorycan operate in scan mode in which scan testing is performing using scan chains within memory, and memorymay also operate in test mode during which BIST is performed. Therefore, memoryis capable of operating in at least three different exclusive modes: normal mode (corresponding to normal functional operation, with our without redundancy enabled), scan mode (corresponding to scan testing with or without redundancy enabled), and test mode (corresponding to BIST). Each of these modes is exclusive to the other modes, in that memorycan only operate in one of these modes at a time.

102 100 102 102 2 FIG. 3 FIG. Note that during memory operation in which reads and writes of data arrayare being performed, only a total of N bits is accessed. That is, only an addressable data element (e.g. Q(w)) is accessed. Therefore, in the case of redundancy being disabled or no repair of a defective column is needed, the data line of the redundant IO group (DLN), corresponding to Q(w+1), is not accessed from outside memory. However, in order to more completely perform BIST testing on data arrayduring the test mode, the data of the redundant data line (corresponding to Q(N)_OUT) is MUXed with scan_out INT onto scan_out PIN to be able to read Q(w+1) in parallel with all the bits of Q(w). This will be described in more detail with respect tobelow. Similarly, an extra bit can be provided to scan_in PIN, via a 1:2 decoder, as Q(N)_IN to Q(w+1) to be written in parallel with all the bits of Q(w). This will be described in more detail with respect tobelow. In each of these cases, control signals available during scan testing or repair can be reused during BIST testing to control how to properly route signals to and from the scan pins, depending on whether normal operation is occurring (normal reads and writes, which may or may not utilize repair) or BIST testing. By being able to access Q(w+1) in addition to Q(w), BIST testing is performed with parallel redundancy which is capable of testing all IO groups of data array, including the redundant IO, without requiring multiple testing passes.

100 128 The table below provides an example of how various control signals are used during operation of memoryin its various modes. A first control signal corresponds to r_en and is used to selectively enable redundancy (i.e. column repair), in which a value of one indicates that repair is enabled and a zero indicates that repair is not enabled. A second control signal corresponds to r_d[x:0] which controls which IO will be repaired out (in which the second control signal can be just a single bit of r_d or, alternatively, can be more than one bit of r_d). A third control signal corresponds to SE (provided by SE_PIN of scan mode control circuitry), in which a value of one enables scan mode and a value of zero indicates scan mode is not enabled.

r_en r_d[x:0] SE Mode 0 0 0 Normal functional operation, without redundancy enabled 0 x 1 Scan mode, without redundancy enabled 0 1 0 BIST test mode with parallel redundancy for Q(w + 1) 1 x 0 Normal functional operation, with redundancy enabled 1 x 1 Scan mode, with redundancy enabled

2 3 FIGS.and 100 136 Therefore, as will be seen inbelow, existing scan pins and repair pins can be used to select the test mode which implements BIST with parallel redundancy (also referred to as “parallel redundancy test mode”) in which a parallel read or write of Q(w+1) along with Q(w) is enabled. This is possible because the scan chains are not used during test mode. Therefore, SoCor BISTcan set r_en to 0, r_d[x:0] to 1, and SE to 0 in order to allow BIST test mode with parallel redundancy. Note that setting r_d[x:0] to 1 indicates that not all bus pins of r_d[x:0] are low (i.e. 0).

2 FIG. 202 100 110 202 100 202 202 204 110 204 206 206 206 206 illustrates, in block diagram form, an example scan chainwhich may be located within memory, such as within memory control circuitry. Scan chainincludes multiple flip flops (FFs) which can be configured to either operate functionally or to be coupled in series for inputting and outputting scan chains. Scan testing is known in the art, therefore, further details in setting up the scan chains and performing scan testing will not be described herein. Note also that memorymay include any number of scan chains. An output of scan chain(from the last FF of the scan chain) is provided as scan_out INT such that scan chain output data can be serially output from scan chainvia scan_out INT. The scan chain output, scan_out INT, is provided as a first input to a MUX(which may be located within memory control circuitry), and Q(N)_OUT is provided as a second input to MUX. A control signal is provided as a first logical combinationof r_en, r_d, and SE. In one embodiment, logical combinationrefers to “(NOT r_en) AND r_d AND (NOT SE).” When scan mode is enabled, “NOT SE” is a logic level zero, causing logical combinationto evaluate as a zero, thus selecting scan_out INT to be output via scan_out PIN, as is typically the case during scan mode for scan testing. However, when scan mode is not enabled, but BIST mode is instead enabled (r_en is a logic level zero and r_d is a logic level one), then logical combinationevaluates as a logic level one, thus selecting Q(w+1) to be output via scan_out PIN. In this manner, Q(w+1) from the redundancy IO group is provided visibility via a scan pin as Q(N)_OUT while Q(w) is provided as DOUT[N−1:0]. Therefore, scan_out PIN is selectable between a scan output and redundancy IO output, based on a logical combination of control signals.

3 FIG. 308 100 110 308 202 100 308 310 312 312 312 312 illustrates, in block diagram form, an example scan chainwhich may be located within memory, such as within memory control circuitry. Scan chainmay be the same scan chain as scan chainor may be a different scan chain of memory. A first FF of scan chainreceives a scan chain input, scan_in INT, configured to serially receive scan chain input data. A 1:2 decoderhas an input coupled to scan_in PIN, in which, based on a control signal which is provided as a logical combinationof r_en, r_d, and SE, provides the input received at scan_in PIN as either Q(N)_IN to Q(w+1) or as scan_in INT. In one embodiment, logical combinationrefers to “(NOT r_en) AND r_d AND (NOT SE).” When scan mode is enabled, “NOT SE” is a logic level zero, causing logical combinationto evaluate as a zero, thus routing scan_in PIN to scan_in INT, as is typically the case for scan mode. However, when scan mode is not enabled, but BIST mode is enabled (r_en is a logic level zero and r_d is a logic level one), then logical combinationevaluates as a logic level one, thus routing scan_in PIN as Q(N)_IN to Q(w+1) while DIN[N−1:0] is provided to Q(w). In this manner, Q(w+1) can be written into the redundancy IO group in parallel with Q(w). Therefore, scan_in PIN can be used to either provide a scan input or a redundancy data bit input, based on a logical combination of control signals.

Therefore, by now it can be appreciated how different pins may be reconfigured, when not needed, to allow improved visibility to a redundant IO group for improved BIST. This improved visibility allows redundant IOs to be tested in one pass, in parallel with the other IO groups of a data array. This improved visibility is achieved by leveraging other control signals, in addition to various pins, which are only used in mutually exclusive modes of operation. For example, since BIST is performed while in test mode, control signals and pins related to scan mode can be reused during BIST testing to output data from the redundant IO or write data into the redundant IO in parallel with accessing the other IO groups of the data array.

Because the apparatus implementing the present invention is, for the most part, composed of electronic components and circuits known to those skilled in the art, circuit details will not be explained in any greater extent than that considered necessary as illustrated above, for the understanding and appreciation of the underlying concepts of the present invention and in order not to obfuscate or distract from the teachings of the present invention.

Although the invention has been described with respect to specific conductivity types or polarity of potentials, skilled artisans appreciated that conductivity types and polarities of potentials may be reversed.

Moreover, the terms “front,” “back,” “top,” “bottom,” “over,” “under” and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions. It is understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in other orientations than those illustrated or otherwise described herein.

1 FIG. Some of the above embodiments, as applicable, may be implemented using a variety of different architectures in a variety of different information processing systems. For example, althoughand the discussion thereof describe an exemplary memory system architecture, this exemplary architecture is presented merely to provide a useful reference in discussing various aspects of the invention. Of course, the description of the architecture has been simplified for purposes of discussion, and it is just one of many different types of appropriate architectures that may be used in accordance with the invention. Those skilled in the art will recognize that the boundaries between logic blocks are merely illustrative and that alternative embodiments may merge logic blocks or circuit elements or impose an alternate decomposition of functionality upon various logic blocks or circuit elements. Thus, it is to be understood that the architectures depicted herein are merely exemplary, and that in fact many other architectures can be implemented which achieve the same functionality.

100 Also for example, in one embodiment, the illustrated elements of systemare circuitry located on a single integrated circuit or within a same device. Furthermore, those skilled in the art will recognize that boundaries between the functionality of the above described operations merely illustrative. The functionality of multiple operations may be combined into a single operation, and/or the functionality of a single operation may be distributed in additional operations. Moreover, alternative embodiments may include multiple instances of a particular operation, and the order of operations may be altered in various other embodiments.

1 FIG. 100 Although the invention is described herein with reference to specific embodiments, various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below. For example, the data array in the memory ofcan include any number of redundant column groups to repair any number of defective columns. Similarly, memorymay include other scan pins which may be reconfigured for use during test mode for improved BIST. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of the present invention. Any benefits, advantages, or solutions to problems that are described herein with regard to specific embodiments are not intended to be construed as a critical, required, or essential feature or element of any or all the claims.

The term “coupled,” as used herein, is not intended to be limited to a direct coupling or a mechanical coupling.

Furthermore, the terms “a” or “an,” as used herein, are defined as one or more than one. Also, the use of introductory phrases such as “at least one” and “one or more” in the claims should not be construed to imply that the introduction of another claim element by the indefinite articles “a” or “an” limits any particular claim containing such introduced claim element to inventions containing only one such element, even when the same claim includes the introductory phrases “one or more” or “at least one” and indefinite articles such as “a” or “an.” The same holds true for the use of definite articles.

Unless stated otherwise, terms such as “first” and “second” are used to arbitrarily distinguish between the elements such terms describe. Thus, these terms are not necessarily intended to indicate temporal or other prioritization of such elements.

The following are various embodiments of the present invention. Note that any of the aspects below can be used in any combination with each other and with any of the disclosed embodiments.

In an embodiment, a memory includes an output pin; a data array having a plurality of rows and columns, wherein a memory cell is located at an intersection of each row and column, wherein the data array is divided into a plurality of input/output (IO) groups and a redundant IO group, each group including a set of columns; a column decoder configured to select one column from each IO group of the plurality of IO groups to provide selected data lines from the data array and one column from the redundant group to provide a redundant data line from the data array; repair circuitry configured to, during normal operation, perform column repair using the selected one column from the redundant group to repair a defective column within one of the plurality of IO groups; read/write circuitry configured to, in response to a read access during a test mode in which built-in self-testing (BIST) is performed, output read data sensed from the redundant data line in parallel with read data sensed from all the selected data lines; and memory control circuitry configured to, in response to the read access during the test mode, provide the output read data sensed from the redundant data line external to the memory via the output pin. In one aspect, the repair circuitry is further configured to, during the test mode, couple all the selected data lines to the read/write circuitry. In a further aspect, the repair circuitry is further configured to, for a read access during normal operation, select a set of N data lines from the selected data lines and the redundant data line to couple to the read/write circuitry, wherein N corresponds to a number of bits in an addressable data element of the data array for the read access. In yet a further aspect, for the read access during normal operation, an unselected data line outside the selected set of N data lines corresponds to a defective column repaired with the selected one column from the redundant IO group. In another further aspect, the read data sensed from the redundant data line in parallel with read data sensed from the selected data lines includes N+1 data bits. In another aspect of the above embodiment, the memory control circuitry includes a plurality of flip flops configured as a scan chain, the scan chain having an output configured to serially output scan chain output data, wherein, during a scan mode of the memory, which is mutually exclusive with the test mode and with normal operation, the memory control circuitry is configured to provide the scan chain output data external to the memory via the output pin. In a further aspect, the memory control circuitry includes a multiplexer (MUX) having a first input configured to receive the scan chain output data, a second input configured to receive the output read data sensed from the redundant data line, and an output coupled to the output pin, wherein the MUX is configured to provide the scan chain output data to the output pin during the scan mode and provide the output read data sensed from the redundant data line to the output pin during the test mode. In yet a further aspect, the MUX further includes a control input coupled to receive a logical combination of a set of control signals used by the memory during at least one of the scan mode or normal operation with column repair. In yet an even further aspect, the set of control signals includes a scan enable signal which selectively enables scan mode, a repair enable signal which selectively enables column repair, and one or more bits of a defective column indicator which indicates a defective column of the plurality of IO groups which is to be repaired when column repair is enabled. In yet another aspect of the above embodiment, the memory further includes an input pin, and the memory control circuitry includes a plurality of flip flops configured as a scan chain, the scan chain having an input configured to serially receive scan chain input data, wherein, during a scan mode of the memory, which is mutually exclusive with the test mode and with normal operation, the memory control circuitry is configured to receive the scan chain input data via the input pin. In a further aspect, the memory control circuitry includes a one-to-two (1:2) decoder having an input coupled to the input pin to receive an input bit, a first output configured to provide the input bit to the read/write circuitry for a write access during normal operation, a second output configured to provide the input bit to the input of the scan chain during the scan mode, and a control input coupled to a receive a logical combination of a set of control signals. In yet a further aspect, the set of control signals includes a scan enable signal which selectively enables scan mode, a repair enable signal which selectively enables column repair, and one or more bits of a defective column indicator which indicates a defective column of the plurality of IO groups which is to be repaired when column repair is enabled. In another further aspect, in response to the write access during normal operation, the input bit is stored into the redundant IO in parallel with storing write data of the write access into the plurality of IO groups. In yet another aspect of the above embodiment, the repair circuitry includes a plurality of multiplexers (MUXes), each coupled to receive a data line from a corresponding IO group of the plurality of IO groups, wherein each MUX of the plurality of MUXes is configured to, during normal operation, provide one of the data line from the corresponding IO group or an alternate data line to the read/write circuitry. In a further aspect, the alternate data line of each MUX is one of a data line corresponding to a neighboring IO group or the redundant data line.

In another embodiment, a memory includes a plurality of flip flops configured as a scan chain having a scan input configured to serially receive scan chain input data and a scan output configured to serially output scan chain output data during a scan mode of the memory; a scan output pin configured to provide the scan chain output data from the scan output of the scan chain during the scan mode; a data array having a plurality of rows and columns, wherein a memory cell is located at an intersection of each row and column, wherein the data array is divided into a plurality of input/output (IO) groups and a redundant IO group, each group including a set of columns; a column decoder configured to select one column from each IO group of the plurality of IO groups to provide selected data lines and one column from the redundant group to provide a redundant data line; read/write circuitry configured to, in response to a read access during a test mode in which built-in self-testing (BIST) is performed, output read data sensed from the redundant data line in parallel with read data sensed from all the selected data lines, wherein the scan mode and test mode are mutually exclusive; and memory control circuitry configured to, in response to the read access during the test mode, provide the output read data sensed from the redundant data line external to the memory via the scan output pin. In one aspect of the another embodiment, the memory further includes repair circuitry configured to, during normal operation, perform column repair using the selected one column from the redundant group to repair a defective column within one of the plurality of IO groups, wherein the scan mode and test modes occur outside of normal operation, wherein the memory control circuitry includes a multiplexer (MUX) having a first input coupled to the scan output to receive the scan chain output data, a second input coupled to the read/write circuitry to receive the output read data sensed from the redundant data line, and an output coupled to the scan output pin. In a further aspect, the memory further includes a scan input pin, wherein the memory control circuitry includes a one-to-two (1:2) decoder having an input coupled to the scan input pin to receive an input bit, a first output configured to provide the input bit to the read/write circuitry for a write access during normal operation, and a second output configured to provide the input bit to the scan input of the scan chain during the scan mode. In yet a further aspect, the MUX further includes a control input coupled to receive a first logical combination of a set of control signals, and the one-to-two decoder further includes a control input coupled to receive a second logical combination of the set of control signals. In yet an even further aspect, the set of control signals includes a scan enable signal which selectively enables scan mode, a repair enable signal which selectively enables column repair, and one or more bits of a defective column indicator which indicates a defective column of the plurality of IO groups which is to be repaired when column repair is enabled.