Semiconductor Device and Manufacturing Method Thereof

This application claims priority to and the benefit of Korean Patent Application No. 10-2024-0164600 filed in the Korean Intellectual Property Office on Nov. 18, 2024, the entire contents of which are incorporated herein by reference.

The present disclosure relates to semiconductor devices and manufacturing methods thereof.

In the modern society, semiconductor devices are closely related to our daily lives. In particular, power semiconductor devices which are used in various fields such as the transportation field, for example, electric vehicles, trains, and electric trams, renewable energy systems, for example, solar power generation and wind power generation, and mobile devices, are becoming increasingly important. Power semiconductor devices are semiconductor devices that are usable to handle high voltage or high current, and perform functions such as power conversion and control in large power systems and high-power electronic devices. Power semiconductor devices have the ability and durability to handle high power, allowing them to handle large amounts of current and withstand high voltages. For example, power semiconductor devices can handle voltages of hundreds to thousands of volts and currents of tens to thousands of amperes. Power semiconductor devices can improve the efficiency of electrical energy by reducing (and/or minimizing) power losses. Further, power semiconductor devices can be stably driven in environments such as high temperatures.

Power semiconductor devices can be categorized by their materials, and for example, there are SiC power semiconductor devices and GaN power semiconductor devices. Instead of conventional silicon (Si), SiC or GaN may be used to manufacture power semiconductor devices, whereby it is possible to compensate for disadvantages of silicon such as for example having unstable characteristics at high temperatures. SiC power semiconductor devices are resistant to high temperatures and have low power loss, making them suitable for electric vehicles, renewable energy systems, and the like. GaN power semiconductor devices require high cost, but are efficient in terms of speed, making them suitable for fast charging of mobile devices and the like.

The present disclosure provides a semiconductor device capable of relieving high-current stress when a surge voltage is applied.

Some example embodiments provide a semiconductor device that includes a substrate including an active region, a termination region outside the active region, and a peripheral region between the active region and the termination region; a semiconductor layer on a first surface of the substrate, the semiconductor layer having a first conductivity type; a doping region inside the semiconductor layer in the active region, the doping region having of a second conductivity type different than the first conductivity type; a peripheral doping region inside the semiconductor layer in the peripheral region, the peripheral doping region having the second conductivity type; a first electrode on the semiconductor layer, the doping region, and the peripheral doping region; a second electrode on a second surface of the substrate, the second surface opposite the first surface; an ohmic contact layer between the peripheral doping region and the first electrode, the ohmic contact layer containing a metal silicide material; and a first insulating pattern between the ohmic contact layer and the first electrode, the first insulating pattern being adjacent to the ohmic contact layer in a direction parallel with the first surface of the substrate.

Some example embodiments further provide a semiconductor device that includes a substrate including an active region, a termination region outside the active region, and a peripheral region between the active region and the termination region; a semiconductor layer on a first surface of the substrate, the semiconductor layer having a first conductivity type; a doping region inside the semiconductor layer in the active region, the doping region having a second conductivity type different than the first conductivity type; a peripheral doping region inside the semiconductor layer in the peripheral region, the peripheral doping region having the second conductivity type; a first electrode on the semiconductor layer, the doping region, and the peripheral doping region; a second electrode on a second surface of the substrate, the second surface being opposite the first surface; an ohmic contact layer positioned between the peripheral doping region and the first electrode, the ohmic contact layer containing a metal silicide material; and a first insulating pattern between the ohmic contact layer and the first electrode, and the first insulating pattern being adjacent to the ohmic contact layer in a direction parallel with the first surface of the substrate. One side surface of the ohmic contact layer abuts with the first insulating pattern, and an upper surface of the ohmic contact layer abuts with the first electrode.

Some example embodiments still further provide a semiconductor device that includes a semiconductor layer having a first conductivity type and being on a substrate, the semiconductor layer including a doping region and a peripheral doping region, and the doping region and the peripheral doping region having a second conductivity type different than the first conductivity type, the semiconductor layer including an active region, a termination region outside the active region, and a peripheral region between the active region and the termination region, and the doping region being in the active region and the peripheral doping region being in the peripheral region; a first insulating pattern on the semiconductor layer in the peripheral region and on the peripheral doping region; a second insulating pattern on the peripheral doping region and on the semiconductor layer in the termination region, the second insulation pattern being spaced apart from the first insulation pattern; an ohmic contact layer on the peripheral doping region between and abutting with the first insulating pattern and the second insulating pattern; and an electrode abutting the doping region and the semiconductor layer in the active region, the ohmic contact layer and the first and second insulating patterns.

Some example embodiments provide a method of manufacturing a semiconductor device that includes implanting an impurity into an upper portion of a semiconductor layer to form a doping region and a peripheral region, the semiconductor layer having a first conductivity type, and the doping region and the peripheral region having a second conductivity type different than the first conductivity type, the semiconductor layer being on a first surface of a substrate including an active region, a termination region outside the active region, and a peripheral region between the active region and the termination region, and the doping region being in the active region and the peripheral doping region being in the peripheral region; forming an insulating layer on the semiconductor layer, the doping region, and the peripheral doping region; forming a first photoresist pattern on the insulating layer; forming a first insulating pattern and a second insulating pattern by etching the insulating layer using the first photoresist pattern as a mask, the first insulating pattern being spaced apart from the second insulating pattern in a direction parallel to the first surface of the substrate; forming an ohmic contact layer on the peripheral doping region between the first insulating pattern and the second insulating pattern; removing the first photoresist pattern; forming a second photoresist pattern covering the ohmic contact layer, the second insulating pattern and a portion of the first insulating pattern; removing a portion of the first insulating pattern by etching the first insulating pattern using the second photoresist pattern as a mask; removing the second photoresist pattern; and forming a first electrode abutting the doping region, the semiconductor layer, and the ohmic contact layer.

In some example embodiments of the method of manufacturing, the implanting the impurity includes forming a plurality of additional doping regions in the active region, the plurality of additional doping regions being spaced apart for each other and from the doping region.

In some example embodiments of the method of manufacturing, the ohmic contact layer includes a metal silicide material, and the forming the ohmic contact layer includes annealing the ohmic contact layer.

In some example embodiments the method of manufacturing further includes implanting a termination doping region having the second conductivity type in the termination region.

In some example embodiments of the method of manufacturing, a doping concentration of the termination doping region is less than a doping concentration of the doping region and a doping concentration of the peripheral doping region.

In some example embodiments of the method of manufacturing, the termination doping region abuts with the peripheral doping region.

In some example embodiments of the method of manufacturing, the portion of the first insulating pattern removed includes portions of the first insulating pattern overlapping the active region.

In some example embodiments of the method of manufacturing, the removing the portion of the first insulating pattern is performed so that the first insulating pattern remains overlapping the doping region.

In some example embodiments of the method of manufacturing, the removing the portion of the first insulating pattern is performed so that the first insulating pattern remains overlapping the semiconductor layer in the active region.

Some example embodiments still further provide a method of manufacturing a semiconductor device that includes forming a semiconductor layer having a first conductivity type on a substrate, the semiconductor layer including an active region, a termination region outside the active region, and a peripheral region between the active region and the termination region; implanting a doping region and a peripheral region in the semiconductor layer, the doping region and the peripheral region having a second conductivity type different than the first conductivity type, and the doping region being in the active region and the peripheral doping region being in the peripheral region; forming a first insulating pattern on the semiconductor layer in the peripheral region and on the peripheral doping region; forming a second insulating pattern on the peripheral doping region and on the semiconductor layer in the termination region, the second insulation pattern being spaced apart from the first insulation pattern; forming an ohmic contact layer on the peripheral doping region between and abutting with the first insulating pattern and the second insulating pattern; and forming an electrode abutting the doping region and the semiconductor layer in the active region, the ohmic contact layer, the first insulating pattern and the second insulating pattern.

According to some example embodiments, it is possible to protect the semiconductor device from high-current stress when a surge voltage is applied.

In the following detailed description, some example embodiments have been shown and described, simply by way of illustration. The present inventive concepts can be variously implemented and are not limited to the following some example embodiments.

The drawings and description are to be regarded as illustrative in nature and not restrictive. Like reference numerals designate like elements throughout the specification.

The size and thickness of each configuration shown in the drawings are arbitrarily shown for understanding and ease of description, but the present inventive concepts are not limited thereto. In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Further, in the drawings, for understanding and ease of description, the thickness of some layers and areas is exaggerated.

Further, it will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” another element, there are no intervening elements present. Further, when an element is “on” a reference portion, the element is located above or below the reference portion, and it does not necessarily mean that the element is located “above” or “on” in a direction opposite to gravity.

Unless explicitly described to the contrary, the word “comprise”, and variations such as “comprises” or “comprising”, will be understood to imply the inclusion of stated elements but not the exclusion of any other elements.

Further, when a target part is referred to as “on a plane”, it means that the target part is viewed from above, and when a target part is referred to as “on a cross-section”, it means the cross-section obtained by cutting the target part vertically is viewed from the side.

When the terms “about” or “substantially” are used in this specification in connection with a numerical value, it is intended that the associated numerical value includes a manufacturing or operational tolerance (e.g., ±10%) around the stated numerical value. Moreover, when the words “generally” and “substantially” are used in connection with geometric shapes, it is intended that precision of the geometric shape is not required but that latitude for the shape is within the scope of the disclosure. Further, regardless of whether numerical values or shapes are modified as “about” or “substantially,” it will be understood that these values and shapes should be construed as including a manufacturing or operational tolerance (e.g., ±10%) around the stated numerical values or shapes. When ranges are specified, the range includes all values therebetween such as increments of 0.1%.

Also, for example, “at least one of A, B, and C” and similar language (e.g., “at least one selected from the group consisting of A, B, and C”) may be construed as A only, B only, C only, or any combination of two or more of A, B, and C, such as, for instance, ABC, AB, BC, and AC.

1 4 FIGS.to Hereinafter, a semiconductor device according to some example embodiments will be described with reference to.

1 FIG. 2 FIG. 1 FIG. 3 FIG. 1 FIG. 4 FIG. 1 FIG. is a plan view of a semiconductor device according to some example embodiments.is a cross-sectional view taken along line A-A′ of.is a cross-sectional view taken along line B-B′ of.is a cross-sectional view taken along line C-C′ of.

1 4 FIGS.to 110 131 110 110 133 131 133 131 173 131 133 175 110 110 110 110 150 133 173 173 141 150 173 150 110 110 a a b a b a b a Referring to, a semiconductor device according to some example embodiments may include a substratethat includes an active region AR, a termination region TR positioned on the outside of the active region AR, and a peripheral region PR positioned between the active region AR and the termination region TR, a semiconductor layerof a first conductivity type that is positioned on a first surfaceof the substrate, a doping regionof a second conductivity type that is positioned inside the semiconductor layerin the active region AR, a peripheral doping regionof the second conductivity type that is positioned inside the semiconductor layerin the peripheral region PR, a first electrodethat is positioned on the semiconductor layerand the doping region, and a second electrodethat is positioned on a second surfaceof the substratefacing the first surfaceof the substrate. The semiconductor device according to some example embodiments may include an ohmic contact layerthat is positioned between the peripheral doping regionand the first electrodeand contains a material different from that of the first electrode, and a first insulating patternthat is positioned between the ohmic contact layerand the first electrodeand positioned so as to abut the ohmic contact layerin a direction parallel with the first surfaceof the substrate.

110 110 110 110 110 110 110 110 110 110 110 110 110 110 110 110 110 110 a b a b The substratemay be a semiconductor substrate containing SiC. For example, the substratemay consist of a 4H SiC substrate. In some example embodiments, the substratemay consist of a 3C SiC substrate, a 6H SiC substrate, or the like. The substratemay be doped with a first conductivity type impurity. For example, the first conductivity type impurity may be an n-type impurity. For example, the substratemay be doped into an n-type. The substratemay be doped into an n-type at a high concentration. The resistivity of the substratemay be in a range from about 0.005 Ωcm to about 0.035 Ωcm. The thickness of the substratemay be in a range from about 10 μm to about 700 μm. The material, doping type, doping concentration, resistivity, thickness, and the like of the substrateare not limited thereto, and may be variously changed. The substratemay have the first surfaceand the second surfacefacing each other. The first surfaceof the substratemay be the upper surface of the substrate, and the second surfaceof the substratemay be the lower surface of the substrate.

110 1 FIG. In some example embodiments, the substratemay include the active region AR, the termination region TR which is positioned on the outside of the active region AR, and the peripheral region PR which is positioned between the active region AR and the termination region TR. The peripheral region PR may be positioned on the outside of the active region AR. The peripheral region PR may abut the outer edge of the active region AR. The termination region TR may be positioned on the outside of the active region AR and the peripheral region PR. The termination region TR may abut the outer edge of the peripheral region PR. The peripheral region PR and the termination region TR may surround the active region AR in a plan view. In some example embodiments, the peripheral region PR and the termination region TR may have ring shapes in a plan view. In, it is shown that the peripheral region PR and the termination region TR completely surround the active region AR; however, the present disclosure is not limited thereto. The peripheral region PR and the termination region TR may surround a portion of the active region AR.

1 2 1 2 110 110 2 1 a In some example embodiments, the termination region TR may be positioned on both sides of the active region AR in a first direction DR, and positioned on both sides of the active region in a second direction DR, in a plan view; however, the present disclosure is not limited thereto. The termination region TR may be positioned on at least one side of the active region AR in a plan view. The first direction DRand the second direction DRmay be directions parallel with the first surfaceof the substrate. The second direction DRmay be, for example, a direction orthogonal to the first direction DR.

1 2 1 2 1 The peripheral region PR may be positioned between the active region AR and the termination region TR. In some example embodiments, the peripheral region PR may be positioned on both sides of the active region AR in a first direction DRand on both sides of the active region in a second direction DR, in a plan view; however, the present disclosure is not limited thereto. The peripheral region PR may be positioned in at least a portion between the active region AR and the termination region TR. For example, the termination region TR may be positioned on both sides of the active region AR in the first direction DRand on both sides of the active region in the second direction DR, in a plan view. Alternatively, the peripheral region PR may be positioned only on both sides in the first direction DRin a plan view. As another example, the termination region TR may be positioned on both sides of the active region AR in a plan view, and the peripheral region PR may be positioned only on one side of the active region AR in a plan view.

1 FIG. As shown in, for example, the active region AR may be rectangular in a plan view. In some example embodiments, the peripheral region PR and the termination region TR may have rectangular ring shapes in a plan view. However, some example embodiments are not limited thereto, and the planar shapes of the active region AR, the peripheral region PR, and the termination region TR may be variously changed.

131 110 110 131 110 131 110 110 131 131 110 131 131 131 131 131 131 110 a The semiconductor layermay be positioned on the first surfaceof the substrate, for example, on the upper surface. The semiconductor layermay be positioned on the entire region of the substrateincluding the active region AR, the peripheral region PR, and the edge region. The lower surface of the semiconductor layermay abut the upper surface of the substrate. However, the present disclosure is not limited thereto, and another desired (and/or alternatively predetermined) layer may be further positioned between the substrateand the semiconductor layer. The semiconductor layermay be an epitaxy layer formed on the substrateby epitaxial growth. The semiconductor layermay contain SiC. For example, the semiconductor layermay contain 4H SiC. The semiconductor layermay be doped into the first conductivity type. In some example embodiments, the first conductivity type may be an n-type. The semiconductor layermay be doped into an n-type. The semiconductor layermay be doped into an n-type at a low concentration. The doping concentration of the semiconductor layermay be lower than the doping concentration of the substrate.

131 133 133 133 133 133 133 131 133 133 133 131 131 133 133 133 3 131 133 133 133 131 133 133 133 133 133 133 133 133 133 133 133 133 133 133 133 a b c a b c a b c a b c a b c a b c a b c a b c a b c c a b. In some example embodiments, inside the semiconductor layer, the doping region, the peripheral doping region, and a termination doping regionmay be positioned. The doping region, the peripheral doping region, and the termination doping regionmay be positioned in the upper portion of the semiconductor layer. The doping region, the peripheral doping region, and the termination doping regionmay extend from the upper surface of the semiconductor layertoward the lower surface of the semiconductor layer. For example, the doping region, the peripheral doping region, and the termination doping regionmay extend in a third direction DRfrom the upper surface of the semiconductor layer. The doping region, the peripheral doping region, and the termination doping regionmay be formed in at least some regions of the semiconductor layerby an ion implantation method. The doping region, the peripheral doping region, and the termination doping regionmay contain SiC. For example, the doping region, the peripheral doping region, and the termination doping regionmay contain 4H SiC. The doping region, the peripheral doping region, and the termination doping regionmay be doped into the second conductivity type. In some example embodiments, the second conductivity type may be a p-type. The doping region, the peripheral doping region, and the termination doping regionmay be doped into a p-type. The doping concentration of the termination doping regionmay be lower than the doping concentrations of the doping regionand the peripheral doping region

131 133 133 133 a b c The materials, doping types, and so on of the semiconductor layer, the doping region, the peripheral doping region, and the termination doping regionare not limited to the above description, and may be variously changed.

133 133 133 1 133 2 a a a a In some example embodiments, the doping regionmay be positioned in the active region AR. In the active region AR, a plurality of doping regionsmay be positioned. The plurality of doping regionsmay be disposed so as to be spaced apart in the first direction DR. Each of the plurality of doping regionsmay extend in the second direction DR.

173 131 173 133 133 131 a a In some example embodiments, in the active region AR, a diode may be positioned. The diode of the semiconductor device according to the some example embodiments may be a SiC diode. The SiC diode which is positioned in the active region AR of the semiconductor device according to some example embodiments may include a Schottky barrier diode and a junction barrier Schottky diode, but is not limited thereto. The Schottky barrier diode may include a structure in which a metal and a semiconductor are bonded. For example, by a structure in which the first electrodeand the semiconductor layerare bonded, a Schottky barrier diode may be formed. The junction barrier Schottky diode may be a structure in which a metal and a semiconductor are bonded and which additionally includes a structure in which a p-type semiconductor and an n-type semiconductor are bonded. For example, by a structure in which the first electrodeand the doping regionare bonded and a structure in which the doping regionof the second conductivity type and the semiconductor layerof the first conductivity type are bonded, a junction barrier Schottky diode may be formed.

133 133 133 133 133 133 1 1 3 133 1 133 2 2 3 133 1 133 133 133 133 b b a b a b a b a b a b b 1 FIG. In some example embodiments, the peripheral doping regionmay be positioned in the peripheral region PR. The width of the peripheral doping regionmay be larger than the width of the doping region. The width of the peripheral doping regionmay be larger than the width of the doping region. The width of the peripheral doping regionin the first direction DRon a cross section along the first direction DRand the third direction DRmay be larger than the width of the doping regionin the first direction DR. The width of the peripheral doping regionin the second direction DRon a cross section along the second direction DRand the third direction DRmay be larger than the width of the doping regionin the first direction DR. The peripheral doping regionmay surround the doping regionin a plan view. In some example embodiments, the peripheral doping regionmay have a ring shape in a plan view. As shown in, the peripheral doping regionmay have a rectangular ring shape in a plan view; however, the present disclosure is not limited thereto.

133 133 133 133 133 133 133 133 133 133 133 133 133 133 c c b c c c b c b c b c b b. In some example embodiments, the termination doping regionmay be positioned in the termination region TR. Although not shown in the drawing, the termination doping regionmay surround the peripheral doping regionin a plan view. In some example embodiments, the termination doping regionmay have a ring shape in a plan view. For example, the termination doping regionmay have a rectangular ring shape in a plan view. The termination doping regionmay abut the peripheral doping region. The termination doping regionmay abut the outer surface of the peripheral doping region, but is not limited thereto. For example, the termination doping regionmay further abut the lower surface of the peripheral doping region. For example, the termination doping regionmay be formed deeper than the peripheral doping regionso as to surround the lower surface of the peripheral doping region

2 4 FIGS.to 133 133 110 110 133 1 2 133 133 c c a c c c In, a single termination doping regionis shown; however, the present disclosure is not limited thereto. In the termination region TR, a plurality of termination doping regionsmay be disposed so as to be spaced apart in a direction parallel with the first surfaceof the substrate. For example, the plurality of termination doping regionsmay be disposed so as to be spaced apart in the first direction DRand the second direction DR. Each of the plurality of termination doping regionsmay have a ring shape. The plurality of termination doping regionsmay have the same center and be different in the distances from the center.

150 150 133 150 133 3 3 1 2 110 110 150 133 150 1 133 1 150 2 133 2 b b a b b b In some example embodiments, the ohmic contact layermay be positioned in the peripheral region PR. The ohmic contact layermay be positioned on the peripheral doping region. The ohmic contact layermay overlap the peripheral doping regionin the third direction DR. The third direction DRmay be a direction perpendicular to the first direction DRand the second direction DRand perpendicular to the first surfaceof the substrate. The width of the ohmic contact layermay be narrower than the width of the peripheral doping region. For example, the width of the ohmic contact layerin the first direction DRmay be narrower than the width of the peripheral doping regionin the first direction DR. For example, the width of the ohmic contact layerin the second direction DRmay be narrower than the width of the peripheral doping regionin the second direction DR.

150 150 150 150 131 133 b In some example embodiments, the ohmic contact layermay form an ohmic contact between a metal and a semiconductor. The ohmic contact layermay lower the resistance between the metal and the semiconductor. In some example embodiments, the ohmic contact layermay be formed on a structure in which a p-type semiconductor and an n-type semiconductor are bonded. The ohmic contact layermay be positioned on the structure in which the semiconductor layerof the first conductivity type and the peripheral doping regionof the second conductivity type are bonded.

150 133 173 173 133 150 150 173 150 b b In some example embodiments, the ohmic contact layermay be positioned between the peripheral doping regionand the first electrode. The first electrodemay be spaced apart from the peripheral doping regionby the ohmic contact layer. The ohmic contact layermay be connected to the SiC diode positioned in the active region AR by the first electrode. The ohmic contact layermay relieve high-current stress which is applied to the SiC diode positioned in the active region AR when a surge voltage is applied to the SiC diode.

150 150 150 150 133 173 133 150 133 173 2 2 2 2 b b b In some example embodiments, the ohmic contact layermay contain a metal silicide material. For example, the ohmic contact layermay contain NiSi, CoSi, WSi, RuSi, MoSi, or TiSi, but is not limited thereto. The metal silicide material which is contained in the ohmic contact layermay be variously changed. In some example embodiments, the work function difference between the material of the ohmic contact layerand the material of the peripheral doping regionmay be smaller than the work function difference between the material of the first electrodeand the material of the peripheral doping region. The ohmic contact layermay contain a metal silicide material having a smaller work function difference from the peripheral doping regionthan the material of the first electrode.

150 133 133 150 133 150 133 150 133 150 133 150 133 150 173 b b b b b b b In some example embodiments, the ohmic contact layermay be formed by depositing a metal layer so as to cover the upper surface of the peripheral doping region, silicidizing the portion of the metal layer abutting the peripheral doping regionthrough annealing, and removing the portion of the metal layer not silicidized. The lower surface of the ohmic contact layermay be positioned at a lower level than the upper surface of the peripheral doping region. The lower portion of the ohmic contact layermay have a shape buried in the upper surface of the peripheral doping region. The lower portion of the ohmic contact layermay be surrounded by the peripheral doping region. The upper surface of the ohmic contact layermay be positioned at a higher level than the upper surface of the peripheral doping region. The upper portion of the ohmic contact layermay have a shape protruding from the upper surface of the peripheral doping region. The upper portion of the ohmic contact layermay be surrounded by the first electrode.

150 141 142 150 141 1 150 141 150 142 150 142 In some example embodiments, the ohmic contact layermay be positioned between the first insulating patternand a second insulating pattern. One side surface of the ohmic contact layermay abut the first insulating pattern. For example, the inner surface (e.g., an inner side surface along the first direction DR) of the ohmic contact layermay abut the first insulating pattern. The other side surface of the ohmic contact layermay abut the second insulating pattern. For example, the outer surface of the ohmic contact layermay abut the second insulating pattern.

141 141 150 150 150 141 133 131 141 133 141 131 141 133 3 141 133 3 141 133 131 141 133 131 b b b b b b In some example embodiments, the first insulating patternmay be positioned in the peripheral region PR. In the peripheral region PR, the first insulating patternmay be positioned on the inner side of the ohmic contact layer. The inner side of the ohmic contact layermay refer to a region closer to the active region AR than the ohmic contact layer. The first insulating patternmay be positioned on the peripheral doping regionand the semiconductor layer. A portion of the first insulating patternmay cover the upper surface of the peripheral doping region, and another portion of the first insulating patternmay cover the upper surface of the semiconductor layer. The first insulating patternmay overlap a portion of the peripheral doping regionin the third direction DR. The first insulating patternmay overlap a portion of the peripheral doping region, adjacent to the active region AR, in the third direction DR. The first insulating patternmay abut the peripheral doping regionand the semiconductor layer. The lower surface of the first insulating patternmay abut the upper surface of the peripheral doping regionand the upper surface of the semiconductor layer.

141 150 173 141 150 110 110 141 150 110 141 150 141 173 141 150 141 173 150 173 141 150 173 1 2 110 110 150 173 173 173 150 141 a a a In some example embodiments, the first insulating patternmay be positioned between the ohmic contact layerand the first electrode. The first insulating patternmay be positioned so as to be adjacent to the ohmic contact layerin a direction parallel with the first surfaceof the substrate. The first insulating patternmay abut the ohmic contact layerin the direction parallel with the first surface. One side surface of the first insulating patternmay abut the ohmic contact layer, and the other side surface of the first insulating patternmay abut the first electrode. A portion of the outer surface of the first insulating patternmay abut the ohmic contact layer, and the other portion of the outer surface of the first insulating patternand the inner surface and upper surface of the first insulating pattern may abut the first electrode. The ohmic contact layermay be spaced apart from a portion of the first electrode, positioned in the active region AR, by the first insulating pattern. In some example embodiments, the ohmic contact layermay be spaced apart from the portion of the first electrodepositioned in the active region AR, in the direction (e.g., the first direction DRand the second direction DR) parallel with the first surfaceof the substrate. This does not mean that the ohmic contact layeris not connected to the portion of the first electrodepositioned in the active region AR. The portion of the first electrodepositioned in the active region AR may be connected to the portion of the first electrodeabutting the ohmic contact layerin the peripheral region PR, on the upper surface of the first insulating pattern.

141 150 141 150 173 141 173 In some example embodiments, the upper surface of the first insulating patternmay be positioned at a higher level than the upper surface of the ohmic contact layer. One side surface of the first insulating patternmay abut the ohmic contact layerand the first electrode, and the other side surface of the first insulating patternmay entirely abut the first electrode.

173 141 141 173 141 173 In some example embodiments, the first electrodemay be positioned on the upper surface of the first insulating pattern. The upper surface of the first insulating patternmay be covered by the first electrode. The upper surface of the first insulating patternmay abut the first electrode.

141 110 110 141 110 150 141 150 150 150 141 a a In some example embodiments, the first insulating patternmay extend in a direction parallel with the first surfaceof the substrate. The first insulating patternmay extend in the direction parallel with the first surfacealong the inner surface of the ohmic contact layer. The first insulating patternmay cover the inner surface of the ohmic contact layer. The inner surface of the ohmic contact layermay refer to the side surface adjacent to the active region AR. As the ohmic contact layerhas a ring shape in a plan view, the first insulating patternmay have a ring shape in a plan view.

142 142 150 150 150 142 133 133 131 142 133 142 133 142 131 142 133 3 142 133 3 142 133 133 131 142 133 133 131 b c b c b b b c b c In some example embodiments, the second insulating patternmay be positioned in the peripheral region PR and the termination region TR. In the peripheral region PR, the second insulating patternmay be positioned on the outside of the ohmic contact layer. The outside of the ohmic contact layermay refer to a region closer to the termination region TR than the ohmic contact layer. The second insulating patternmay be positioned on the peripheral doping region, the termination doping region, and the semiconductor layer. A portion of the second insulating patternmay cover the upper surface of the peripheral doping region, another portion of the second insulating patternmay cover the upper surface of the termination doping region, and another portion of the second insulating patternmay cover the upper surface of the semiconductor layer. The second insulating patternmay overlap a portion of the peripheral doping regionin the third direction DR. The second insulating patternmay overlap a portion of the peripheral doping region, adjacent to the termination region TR, in the third direction DR. The second insulating patternmay abut the peripheral doping region, the termination doping region, and the semiconductor layer. The lower surface of the second insulating patternmay abut the upper surface of the peripheral doping region, the upper surface of the termination doping region, and the upper surface of the semiconductor layer.

142 150 142 150 150 In some example embodiments, the second insulating patternmay be positioned on the outer surface of the ohmic contact layer. The second insulating patternmay cover the outer surface of the ohmic contact layer. The outer surface of the ohmic contact layermay refer to the side surface adjacent to the termination region TR.

142 110 110 142 110 150 150 142 a a In some example embodiments, the second insulating patternmay extend in a direction parallel with the first surfaceof the substrate. The second insulating patternmay extend in the direction parallel with the first surfacealong the outer surface of the ohmic contact layer. As the ohmic contact layerhas a ring shape in a plan view, the second insulating patternmay have a ring shape in a plan view.

142 150 142 150 173 142 141 141 142 150 173 In some example embodiments, the upper surface of the second insulating patternmay be positioned at a higher level than the upper surface of the ohmic contact layer. One side surface of the second insulating patternmay abut the ohmic contact layerand the first electrode. The upper surface of the second insulating patternmay be positioned at the same level or at substantially the same level as that of the upper surface of the first insulating pattern. Between the first insulating patternand the second insulating pattern, the ohmic contact layerand the first electrodemay be positioned.

141 142 141 142 141 142 131 133 133 133 141 142 133 150 133 141 142 133 131 173 133 131 a b c b b a a In some example embodiments, the first insulating patternand the second insulating patternmay be isolated; however, the present disclosure is not limited thereto. In some example embodiments, the first insulating patternand the second insulating patternmay be connected. The first insulating patternand the second insulating patternmay be formed by performing patterning on an insulating layer formed so as to cover the semiconductor layer, the doping region, the peripheral doping region, and the termination doping region. The first insulating patternand the second insulating patternmay be insulating patterns which expose at least a portion of the upper surface of the peripheral doping regionin order to form the ohmic contact layeron the peripheral doping region, which is positioned in the peripheral region PR. The first insulating patternand the second insulating patternmay be insulating patterns which expose at least some portions of the upper surfaces of the doping regionand the semiconductor layerin order to form the first electrodewhich abuts the doping regionand the semiconductor layerpositioned in the active region AR.

141 142 141 142 141 142 The first insulating patternand the second insulating patternmay contain an insulating material. In some example embodiments, the first insulating patternand the second insulating patternmay contain at least one of silicon oxides, silicon nitrides, and silicon oxynitrides; however, the present disclosure is not limited thereto. The insulating material which is contained in the first insulating patternand the second insulating patternmay be variously changed.

173 131 133 133 173 173 173 131 133 173 131 133 173 131 133 3 173 131 133 3 a b a b a b In some example embodiments, the first electrodemay be positioned on the semiconductor layer, the doping region, and the peripheral doping region. The first electrodemay be positioned in the active region AR and the peripheral region PR. The first electrodemay not be positioned in the termination region TR. The first electrodemay be positioned on the semiconductor layerand the doping regionin the active region AR. The first electrodemay be positioned on the semiconductor layerand the peripheral doping regionin the peripheral region PR. In the active region AR, the first electrodemay overlap the semiconductor layerand the doping regionin the third direction DR. In the peripheral region PR, the first electrodemay overlap the semiconductor layerand the peripheral doping regionin the third direction DR.

173 131 133 173 131 133 173 131 173 133 a a a In some example embodiments, the first electrodemay abut the semiconductor layerand the doping region. The first electrodemay abut the upper surface of the semiconductor layerand the upper surface of the doping region. As the lower surface of the first electrodeabuts the upper surface of the semiconductor layer, a Schottky barrier diode may be formed. As the lower surface of the first electrodeabuts the upper surface of the doping region, a junction barrier Schottky diode may be formed.

173 133 173 133 150 173 133 150 b b b In some example embodiments, the first electrodemay not abut the peripheral doping region. The first electrodemay be spaced apart from the upper surface of the peripheral doping regionby the ohmic contact layer. Between the first electrodeand the peripheral doping region, the ohmic contact layermay be positioned.

173 141 173 141 173 142 173 142 173 142 173 142 133 3 173 141 142 b In some example embodiments, the first electrodemay cover the first insulating pattern. The first electrodemay cover the upper surface and both side surfaces of the first insulating pattern. The first electrodemay cover the second insulating pattern. In some example embodiments, the first electrodemay cover the upper surface and side surface of the second insulating pattern. The first electrodemay cover a portion of the upper surface of the second insulating pattern. The first electrodemay cover a portion of the upper surface of the second insulating patternoverlapping the peripheral doping regionin the third direction DR. The upper surface of the first electrodemay be positioned at a higher level than the upper surface of the first insulating patternand the upper surface of the second insulating pattern.

173 173 141 173 131 133 173 150 141 173 141 173 141 141 141 141 a In some example embodiments, the portion of the first electrodepositioned in the active region AR and the portion of the first electrodepositioned in the peripheral region PR may be connected on the upper surface of the first insulating pattern. The portion of the first electrodewhich abuts the semiconductor layerand the doping regionin the active region AR and the portion of the first electrodewhich abuts the ohmic contact layerin the peripheral region PR may be connected on the upper surface of the first insulating pattern. The portion of the first electrodewhich is positioned on the inner surface of the first insulating patternand the portion of the first electrodewhich is positioned on the outer surface of the first insulating patternmay be connected on the upper surface of the first insulating pattern. The inner surface of the first insulating patternmay be the side surface adjacent to the active region AR, and the outer surface of the first insulating patternmay be the side surface adjacent to the termination region TR.

173 173 173 In some example embodiments, the first electrodemay have a plate shape entirely covering at least some portions of the active region AR and the peripheral region PR adjacent to the active region AR. The planar shape of the first electrodemay be, for example, a rectangle, but is not limited thereto, and the planar shape of the first electrodemay be variously changed.

173 173 173 173 173 2 4 FIGS.to The first electrodemay contain a conductive material. For example, the first electrodemay contain a metal, a metal alloy, a conductive metal nitride, a metal silicide material, a conductive metal oxide, a conductive metal nitride, or the like. The first electrodemay contain, for example, titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tantalum titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlC—N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), tantalum carbonizationnitride (TaCN), tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel platinum (Ni—Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V), or a combination thereof, but is not limited thereto. In, it is shown that the first electrodeis a single layer; however, the present disclosure is not limited thereto. The first electrodemay consist of multiple layers.

175 110 110 175 110 175 110 110 175 175 110 175 110 175 110 b The second electrodemay be positioned on the second surfaceof the substrate, e.g., the lower surface. The upper surface of the second electrodemay abut the lower surface of the substrate. The second electrodemay be in ohmic contact with the substrate. The region inside the substratewhich is in contact with the second electrodemay be doped at a relatively higher concentration, as compared to the other region. However, the present disclosure is not limited thereto, and between the second electrodeand the substrate, another desired (and/or alternatively predetermined) layer may be further positioned. For example, between the second electrodeand the substrate, a silicide layer may be positioned. The silicide layer may contain a metal silicide material. By the metal silicide layer, the second electrodeand the substratemay be electrically smoothly connected.

175 175 175 173 175 The second electrodemay contain a conductive material. For example, the second electrodemay contain a metal, a metal alloy, a conductive metal nitride, a metal silicide material, a doped semiconductor material, a conductive metal oxide, a conductive metal oxynitride, or the like. The second electrodemay consist of the same material as that of the first electrode, or may consist of a material different from that of the first electrode. The second electrodemay consist of a single layer or multiple layers.

150 133 173 133 131 141 110 110 150 173 b a a The semiconductor device according to some example embodiments may include the ohmic contact layerthat contains the metal silicide material between the peripheral doping region, which is positioned in the peripheral region PR positioned between the active region AR and the termination region TR positioned on the outside of the active region AR, and the first electrodewhich abuts the doping regionand the semiconductor layerpositioned in the active region AR, and the first insulating patternthat extends in the direction parallel with the first surfaceof the substratebetween the ohmic contact layerand the first electrode. According to the some example embodiments, it is possible to protect the semiconductor device from a surge voltage.

1 4 FIGS.to 5 7 FIGS.to Hereinafter, a modification of the semiconductor device according to some example embodiments shown inwill be described with reference to.

5 FIG. 1 FIG. 6 FIG. 1 FIG. 7 FIG. 1 FIG. 5 7 FIGS.to 1 4 FIGS.to 5 7 FIGS.to 1 4 FIGS.to 141 is a cross-sectional view taken along line A-A′ of.is a cross-sectional view taken along line B-B′ of.is a cross-sectional view taken along line C-C′ of. Since some example embodiments shown inhave many portions identical to those of the some example embodiments shown in, description thereof will not be made and the differences will be mainly described. Also, constituent elements identical to those of the above some example embodiments are denoted by the same reference symbols. Some example embodiments shown inmay be partially different than some example embodiments shown inin the structure of the first insulating pattern.

5 7 FIGS.to 5 7 FIGS.to 1 4 FIGS.to 1 4 FIGS.to 5 7 FIGS.to 141 141 133 131 141 131 133 133 131 133 133 141 131 133 133 141 b a b a b a b Referring to, the first insulating patternmay be positioned in the peripheral region PR. In some example embodiments shown in, in the peripheral region PR, the first insulating patternmay abut the peripheral doping regionand may not abut the semiconductor layer, unlike in some example embodiments shown in. The first insulating patternmay not be positioned on the upper surface of the semiconductor layerpositioned between the doping regionand the peripheral doping region. In some example embodiments shown in, the upper surface of the semiconductor layerpositioned between the doping regionand the peripheral doping regionis covered by the first insulating pattern, but in some example embodiments shown in, the upper surface of the semiconductor layerpositioned between the doping regionand the peripheral doping regionmay not be covered by the first insulating pattern.

173 131 173 131 133 133 a b. In some example embodiments, the first electrodemay abut the semiconductor layerin the peripheral region PR. The first electrodemay abut the semiconductor layerpositioned between the doping regionand the peripheral doping region

141 131 133 141 131 133 133 141 a a b 5 7 FIGS.to When the first insulating patternis patterned in order to expose the upper surfaces of the semiconductor layerand the doping regionpositioned in the active region AR, the portion of the first insulating patterncovering the upper surface of the semiconductor layerpositioned between the doping regionand the peripheral doping regionmay be removed, whereby the first insulating patternaccording to some example embodiments shown inmay be formed.

141 141 141 1 2 110 110 5 7 FIGS.to 1 4 FIGS.to a The width of the first insulating patternaccording to some example embodiments shown inmay be narrower than the width of the first insulating patternaccording to some example embodiments shown in. Here, the width of the first insulating patternmay refer to the width in a direction (e.g., the first direction DRand the second direction DR) parallel with the first surfaceof the substrate.

1 4 FIGS.to 8 10 FIGS.to Hereinafter, a modification of the semiconductor device according to some example embodiments shown inwill be described with reference to.

8 FIG. 1 FIG. 9 FIG. 1 FIG. 10 FIG. 1 FIG. 8 10 FIGS.to 1 4 FIGS.to 8 10 FIGS.to 1 4 FIGS.to 141 is a cross-sectional view taken along line A-A′ of.is a cross-sectional view taken along line B-B′ of.is a cross-sectional view taken along line C-C′ of. Since some example embodiments shown inhave many portions identical to those of some example embodiments shown in, description thereof will not be made and the differences will be mainly described. Also, constituent elements identical to those of the above some example embodiments are denoted by the same reference symbols. Some example embodiments shown inmay be partially different from some example embodiments shown inin the structure of the first insulating pattern.

8 10 FIGS.to 8 10 FIGS.to 1 4 FIGS.to 141 141 141 141 133 1 141 133 141 133 133 141 173 a a a a Referring to, the first insulating patternmay be positioned in the active region AR and the peripheral region PR. In some example embodiments shown in, a portion of the first insulating patternmay be positioned in the active region AR, and another portion of the first insulating patternmay be positioned in the peripheral region PR, unlike in some example embodiments shown in. The first insulating patternmay be positioned on the doping regionpositioned inside the active region AR. The first insulating patternmay be positioned on the doping regionadjacent to the peripheral region PR. The first insulating patternmay cover the upper surface of the doping regionadjacent to the peripheral region PR. Since the doping regionwhich is covered by the first insulating patterndoes not abut the first electrode, it does not constitute a junction barrier Schottky diode.

8 10 FIGS.to 8 10 FIGS.to 141 133 141 131 133 141 133 133 131 133 a a a a a. In, it is shown that the first insulating patterncovers only the upper surface of the doping region; however, the present disclosure is not limited thereto, and the first insulating patternmay further cover the upper surface of the semiconductor layeradjacent to the doping region. In, it is shown that the first insulating patterncovers only the upper surface of one doping regionclosest to the peripheral region PR; however, the present disclosure is not limited thereto, and the first insulating pattern may cover the upper surfaces of a plurality of doping regionsadjacent to the peripheral region PR and the upper surface of the semiconductor layerbetween the plurality of doping regions

141 131 133 141 133 141 a a 8 10 FIGS.to When the first insulating patternis patterned in order to expose the upper surfaces of the semiconductor layerand the doping regionpositioned in the active region AR, less of the portion of the first insulating patterncovering the upper surface of the doping regionadjacent to the peripheral region PR may be removed, whereby the first insulating patternaccording to some example embodiments shown inmay be formed.

141 141 141 1 2 110 110 8 10 FIGS.to 1 4 FIGS.to a The width of the first insulating patternaccording to some example embodiments shown inmay be wider than the width of the first insulating patternaccording to some example embodiments shown in. Here, the width of the first insulating patternmay refer to the width in a direction (e.g., the first direction DRand the second direction DR) parallel with the first surfaceof the substrate.

1 4 FIGS.to 11 20 FIGS.to Hereinafter, a method of manufacturing the semiconductor device according to some example embodiments shown inwill be described with reference to.

11 20 FIGS.to are cross-sectional views illustrating processes of manufacturing a semiconductor device according to some example embodiments in the order of the processes.

11 FIG. 110 110 131 131 133 133 a a b Referring to, on the first surfaceof the substrate, the semiconductor layerof the first conductivity type may be formed, and in the upper portion of the semiconductor layer, the doping regionof the second conductivity type and the peripheral doping regionof the second conductivity type may be formed.

110 110 110 110 110 110 110 110 110 a b The substratemay be a semiconductor substrate containing SiC. For example, the substratemay consist of a 4H SiC substrate. The substratemay be doped into the first conductivity type. For example, the first conductivity type may be an n-type. The substratemay be doped into an n-type. The substratemay be doped into an n-type at a high concentration. The first surfaceof the substratemay be the upper surface, and the second surfaceof the substratemay be the lower surface.

110 In some example embodiments, the substratemay include the active region AR, the termination region TR which is positioned on the outside of the active region AR, and the peripheral region PR which is positioned between the active region AR and the termination region TR. The peripheral region PR may be positioned on the outside of the active region AR. The termination region TR may be positioned on the outside of the active region AR and the peripheral region PR. The peripheral region PR and the termination region TR may surround the active region AR in a plan view. However, the peripheral region PR and the termination region TR are not limited to completely surrounding the active region AR, and the peripheral region PR and the termination region TR may surround a portion of the active region AR.

In some example embodiments, the peripheral region PR and the termination region TR may have ring shapes in a plan view. For example, the active region AR may be rectangular in a plan view. In some example embodiments, the peripheral region PR and the termination region TR may have rectangular ring shapes in a plan view. However, the some example embodiments is not limited to, and the planar shapes of the active region AR, the peripheral region PR, and the termination region TR may be variously changed.

110 110 131 131 110 110 131 131 131 131 131 131 131 110 131 110 a On the first surfaceof the substrate, e.g., on the upper surface, the semiconductor layerof the first conductivity type may be formed by epitaxial growth. The semiconductor layermay be formed directly on the substrate, or after another desired (and/or alternatively predetermined) layer is formed on the substrate, the semiconductor layermay be formed thereon. The semiconductor layermay contain SiC. For example, the semiconductor layermay contain 4H SiC. The semiconductor layermay be doped into the first conductivity type. For example, the first conductivity type may be an n-type. The semiconductor layermay be doped into an n-type. The semiconductor layermay be doped into an n-type at a low concentration. The doping concentration of the semiconductor layermay be lower than the doping concentration of the substrate. The dopant material for the semiconductor layermay be the same as the dopant material for the substrate, or may be different from the dopant material for the substrate.

131 133 131 133 131 133 133 133 133 133 133 133 131 133 133 133 133 133 133 a b c a b c a b c a b c a b c Next, in the upper portion of the semiconductor layerpositioned in the active region AR, the doping regionof the second conductivity type may be formed, and in the upper portion of the semiconductor layerpositioned in the peripheral region PR, the peripheral doping regionof the second conductivity type may be formed. Further, in the upper portion of the semiconductor layerpositioned in the termination region TR, the termination doping regionof the second conductivity type may be formed. The doping region, the peripheral doping region, and the termination doping regionmay be formed by an ion implantation process (IIP). First, regions where the doping region, the peripheral doping region, and the termination doping regionwill be formed may be defined on the semiconductor layerby a photolithography process. Thereafter, impurities of the second conductivity type may be implanted into the corresponding regions. The doping region, the peripheral doping region, and the termination doping regionmay have desired (and/or alternatively predetermined) depths. In some example embodiments, the depths of the doping region, the peripheral doping region, and the termination doping regionmay be determined by the numbers (e.g., amount) of impurities which are implanted, and/or the rates at which the impurities are accelerated.

133 133 1 133 2 a a a In some example embodiments, a plurality of doping regionsmay be formed in the active region AR. The plurality of doping regionsmay be formed so as to be spaced apart in the first direction DR, and each of the plurality of doping regionsmay extend in the second direction DR.

133 133 133 133 133 133 1 1 3 133 1 133 2 2 3 133 1 b a b b a b a b a In some example embodiments, the peripheral doping regionwhich is formed in the peripheral region PR may have a ring shape surrounding the plurality of doping regionsin a plan view. For example, the peripheral doping regionmay have a rectangular ring shape in a plan view. The width of the peripheral doping regionmay be larger than the width of the doping region. The width of the peripheral doping regionin the first direction DRon a cross section along the first direction DRand the third direction DRmay be larger than the width of the doping regionin the first direction DR. The width of the peripheral doping regionin the second direction DRon a cross section along the second direction DRand the third direction DRmay be larger than the width of the doping regionin the first direction DR.

133 133 133 133 133 133 133 133 133 110 110 133 c b c a b c c c c a c In the some example embodiments, the termination doping regionmay be formed so as to abut the outer surface of the peripheral doping region. The termination doping regionmay have a ring shape surrounding the plurality of doping regionsand the peripheral doping region. For example, the termination doping regionmay have a rectangular ring shape in a plan view. In the termination region TR, a single termination doping regionmay be formed, or a plurality of termination doping regionsmay be formed. The plurality of termination doping regionsmay be disposed so as to be spaced apart in a direction parallel with the first surfaceof the substrate. The plurality of individual termination doping regionsmay have ring shapes having the same center and different in the distances from the center.

133 133 133 133 133 133 133 133 133 133 133 133 a b c a b c a b c a b c The doping region, the peripheral doping region, and the termination doping regionmay contain SiC. For example, the doping region, the peripheral doping region, and the termination doping regionmay contain 4H SiC. The doping region, the peripheral doping region, and the termination doping regionmay be doped into the second conductivity type. For example, the second conductivity type may be a p-type. The doping region, the peripheral doping region, and the termination doping regionmay be doped into a p-type.

133 133 133 133 133 133 133 133 133 133 133 a b c a b c a b a b c In some example embodiments, the doping regionand the peripheral doping regionmay be doped into a p-type at a high concentration, and the termination doping regionmay be doped into a p-type at a low concentration. For example, after the doping region, the peripheral doping region, and the termination doping regionare doped into a p-type at a low concentration, the doping regionand the peripheral doping regionmay be additionally doped. As another example, the doping regionand the peripheral doping region, and the termination doping regionmay be doped separately such that the doping region and the peripheral doping region are doped at a concentration different from that of the doping concentration of the termination doping region.

133 133 133 a b c The materials, doping types, and the like of doping region, the peripheral doping region, and the termination doping regionare not limited thereto, and may be variously changed.

131 133 133 133 140 140 140 110 a b c Next, on the semiconductor layer, the doping region, the peripheral doping region, and the termination doping region, an insulating layermay be formed. The insulating layermay be formed through a deposition process such as physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD). The insulating layermay be formed throughout the active region AR, peripheral region PR, and termination region TR of the substrate.

140 140 140 The insulating layermay contain an insulating material. The insulating layermay contain, for example, a silicon oxide, but is not limited thereto. The insulating material which is contained in the insulating layermay be variously changed.

12 FIG. 140 1 140 1 141 142 Referring to, on the insulating layer, a first photoresist pattern PRmay be formed, and patterning may be performed on the insulating layerusing the first photoresist pattern PRto form the first insulating patternand the second insulating pattern.

140 1 1 140 140 1 133 140 141 142 140 141 142 142 141 b First, after a first photoresist layer is formed on the insulating layer, patterning may be performed on the first photoresist layer through a photolithography process to form the first photoresist pattern PR. The first photoresist pattern PRmay be used to perform patterning on the insulating layerby an etching process. The portion of the insulating layerthat is not covered by the first photoresist pattern PRmay be etched and removed. Accordingly, the portion of the upper surface of the peripheral doping regionhaving been covered by the insulating layermay be exposed. The first insulating patternand the second insulating patternmay be the portions of the insulating layerremaining after performing the etching process. The first insulating patternand the second insulating patternmay be spaced apart from each other. In a plan view, the second insulating patternmay have a shape surrounding the first insulating pattern.

141 133 142 133 141 142 133 133 133 133 1 2 110 110 b b b b b b a In some example embodiments, the first insulating patternmay cover a portion of the upper surface of the peripheral doping regionadjacent to the active region AR, and the second insulating patternmay cover a portion of the upper surface of the peripheral doping regionadjacent to the termination region TR. By the opening between the first insulating patternand the second insulating pattern, an approximately central portion of the upper surface of the peripheral doping regionmay be exposed. In some example embodiments, the exposed portion of the upper surface of the peripheral doping regionmay have a ring shape narrower than the width of the entire upper surface of the peripheral doping regionin a plan view. Here, the width of the upper surface of the peripheral doping regionmay refer to the width in a direction (e.g., the first direction DRor the second direction DR) parallel with the first surfaceof the substrate.

13 FIG. 1 150 150 141 142 133 150 133 150 141 142 141 142 150 141 142 133 b b b Referring to, the first photoresist pattern PRmay be removed, and a metal layerL may be formed. The metal layerL may be formed so as to cover the first insulating pattern, the second insulating pattern, and the peripheral doping region. The metal layerL may cover the upper surface of the peripheral doping region. The metal layerL may cover the upper surface of the first insulating pattern, the upper surface of the second insulating pattern, and the side surfaces of the first insulating patternand the second insulating patternfacing each other. The metal layerL may cover the first insulating pattern, the second insulating pattern, and the peripheral doping regionso as to conform to them.

150 150 For example, the metal layerL may be formed by a process such as electroplating, sputtering, or CVD; however, the process of forming the metal layerL is not limited thereto, and may be variously changed.

150 150 150 The metal layerL may contain a metal material. The metal layerL may contain, for example, Ni, Co, W, Ru, Mo, or Ti, but is not limited thereto. The material of the metal layerL may be variously changed, and needs only to be able to form a metal silicide material at the junction with SiC.

14 FIG. 150 Referring to, the ohmic contact layermay be formed by performing an annealing process.

133 150 150 133 150 150 150 150 133 173 b b b 2 2 2 2 When the annealing process is performed, the junction of the peripheral doping regionand the metal layerL may be silicidized. The metal material of the metal layerL and SiC of the peripheral doping regionmay react to form the ohmic contact layerwhich contains the metal silicide material. The ohmic contact layermay contain, for example, NiSi, CoSi, WSi, RuSi, MoSi, or TiSi, but is not limited thereto. The metal silicide material which is contained in the ohmic contact layermay be variously changed. In some example embodiments, the ohmic contact layermay contain a material having a smaller work function difference from the peripheral doping regionthan the first electrodeto be described below.

150 133 150 133 150 133 150 133 150 1 133 1 150 2 133 2 b b b b b b In some example embodiments, the ohmic contact layermay abut the peripheral doping region. The lower surface of the ohmic contact layermay be positioned at a lower level than the upper surface of the peripheral doping region. The upper surface of the ohmic contact layermay be positioned at a higher level than the upper surface of the peripheral doping region. The width of the ohmic contact layermay be narrower than the width of the peripheral doping region. The width of the ohmic contact layerin the first direction DRmay be narrower than the width of the peripheral doping regionin the first direction DR. The width of the ohmic contact layerin the second direction DRmay be narrower than the width of the peripheral doping regionin the second direction DR.

150 133 141 150 133 142 b b In some example embodiments, one side surface of the ohmic contact layermay abut the peripheral doping regionand the first insulating pattern. The other side surface of the ohmic contact layermay abut the peripheral doping regionand the second insulating pattern.

15 FIG. 150 150 150 141 142 150 141 142 150 150 Referring to, the metal layerL which has not reacted with SiC may be removed. The metal layerL may be removed, for example, through a wet etching process, but is not limited thereto. The process of etching the metal layerL may be performed using a material having high etch selectivity to the first insulating pattern, the second insulating pattern, and the ohmic contact layer. The first insulating pattern, the second insulating pattern, and the ohmic contact layermay be barely etched, and the metal layerL may be well etched and removed.

16 FIG. 141 150 142 2 141 150 142 2 Referring to, on the first insulating pattern, the ohmic contact layer, and the second insulating pattern, a second photoresist pattern PRmay be formed. For example, after a second photoresist layer is formed on the first insulating pattern, the ohmic contact layer, and the second insulating pattern, patterning may be performed on the second photoresist layer through a photolithography process to form the second photoresist pattern PR.

2 150 150 141 2 141 150 150 141 150 110 110 2 141 150 a In some example embodiments, the second photoresist pattern PRmay cover the ohmic contact layer. The ohmic contact layercan be limited and/or prevented from being etched together with the first insulating patternby a material which is used in the subsequent etching process of opening the active region AR. Further, the second photoresist pattern PRmay further cover the first insulating patternpositioned on the inner side of the ohmic contact layer. The inner side of the ohmic contact layermay refer to the region adjacent to the active region AR. The first insulating patternshould be covered such that the material which is used in the subsequent etching process cannot etch the ohmic contact layereven if it exerts an effect in a direction parallel with the first surfaceof the substrate. For this reason, the second photoresist pattern PRmay be patterned so as to cover the portion of the first insulating patterncovering the inner surface of the ohmic contact layer.

2 141 150 141 141 133 131 133 133 141 133 131 133 133 141 141 b a b b a b 5 7 FIGS.to 8 10 FIGS.to In some example embodiments, depending on the width by which the second photoresist pattern PRcovers the first insulating patternpositioned on the inner side of the ohmic contact layer, the width and structure of the first insulating patternwhich remains in the final structure may vary. According to some example embodiments, the first insulating patternmay be positioned only inside the peripheral region PR. According to some example embodiments, the first insulating pattern may be positioned on the upper surface of the peripheral doping regionin the peripheral region PR and the upper surface of the semiconductor layerpositioned between the doping regionand the peripheral doping region. However, the first insulating pattern is not limited thereto. For example, as shown in, in some example embodiments the first insulating patternmay be positioned only on the upper surface of the peripheral doping regionin the peripheral region PR, and may not be positioned on the upper surface of the semiconductor layerpositioned between the doping regionand the peripheral doping region. As another example, in some example embodiments as shown in, a portion of the first insulating patternmay be positioned in the active region AR, and another portion of the first insulating patternmay be positioned in the peripheral region PR.

17 FIG. 141 2 141 2 133 131 a Referring to, a portion of the first insulating patternmay be removed by performing an etching process using the second photoresist pattern PR. The portion of the first insulating patternthat is not covered by the second photoresist pattern PRmay be etched and removed. Accordingly, the upper surface of the doping regionpositioned in the active region AR and the upper surface of the semiconductor layermay be exposed.

18 FIG. 2 2 2 141 141 2 Referring to, the second photoresist pattern PRmay be removed. For example, the second photoresist pattern PRmay be removed through an ashing process and/or a strip process. While the second photoresist pattern PRis removed, a portion of the first insulating patternmay be removed together. For example, a portion of the first insulating patternadjacent to an end portion of the second photoresist pattern PRmay be removed together.

141 133 3 110 110 141 133 3 141 133 150 b a b b In some example embodiments, the first insulating patternmay overlap a portion of the peripheral doping regionin the third direction DRperpendicular to the first surfaceof the substrate. The first insulating patternmay abut the portion of the peripheral doping regionin the third direction DR. The lower surface of the first insulating patternmay abut the upper surface of the peripheral doping regionpositioned on the inner side of the ohmic contact layer.

19 FIG. 173 133 131 150 131 133 141 150 142 a a Referring to, the first electrodemay be formed so as to abut the doping region, the semiconductor layer, and the ohmic contact layer. First, a first electrode material layer may be formed so as to cover the upper surfaces of the semiconductor layer, the doping region, the first insulating pattern, the ohmic contact layer, and the second insulating pattern, and then, patterning may be performed on the first electrode material layer through a photolithography process and an etching process.

173 173 131 133 173 150 a In some example embodiments, the first electrodemay be positioned on the active region AR and the peripheral region PR, and may not be positioned in the termination region TR. The first electrodemay abut the upper surfaces of the semiconductor layerand the doping regionin the active region AR. The first electrodemay abut the upper surface of the ohmic contact layerin the peripheral region PR.

173 141 173 141 173 142 142 150 173 142 173 142 142 In some example embodiments, the first electrodemay surround the first insulating pattern. The first electrodemay cover the upper surface and both side surfaces of the first insulating pattern. The first electrodemay cover the inner surface of the second insulating pattern. The inner surface of the second insulating patternmay be the side surface abutting the ohmic contact layer. The first electrodemay cover a portion of the upper surface of the second insulating pattern, but is not limited thereto. The first electrodemay cover only the inner surface of the second insulating pattern, and may not cover the upper surface of the second insulating pattern.

173 173 The first electrodemay contain a conductive material. For example, the first electrodemay contain a metal, a metal alloy, a conductive metal nitride, a metal silicide material, a conductive metal oxide, a conductive metal nitride, or the like.

173 131 173 133 133 131 131 133 150 133 173 150 173 133 150 a a b b b As the first electrodeand the semiconductor layerabut each other in the active region AR, a Schottky barrier diode may be formed. As the first electrodeand the doping regionabut each other and the doping regionabuts the semiconductor layerof the different conductivity type in the active region AR, a junction barrier Schottky diode may be formed. In the peripheral region PR, the semiconductor layerand the peripheral doping regionhaving different conductivity types may abut each other, and the ohmic contact layermay be positioned between the peripheral doping regionand the first electrode. The ohmic contact layermay lower the resistance between the first electrodeand the peripheral doping region. Accordingly, when a surge voltage is applied to diodes positioned in the active region AR, a portion of high current may flow through the ohmic contact layerhaving relatively low resistance, whereby high-current stress on the diodes in the active region AR may be relieved.

20 FIG. 175 110 110 173 175 173 175 b Referring to, the second electrodemay be formed on the second surfaceof the substrate. Depending on the voltage which is applied between the first electrodeand the second electrode, current may flow in the diodes positioned in the active region AR from the first electrodetoward the second electrode.

While this disclosure has been described in connection with what is presently considered to be some example embodiments, it is to be understood that the inventive concepts are not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.