Method of Manufacturing a Semiconductor Device Including Depositing and Etching a Liner Multiple Times

This application is a continuation of U.S. patent application Ser. No. 18/514,661, filed on Nov. 20, 2023, entitled “Method of Manufacturing a Semiconductor Device Including Depositing and Etching a Liner Multiple Times,” which is a continuation of U.S. patent application Ser. No. 17/114,082, filed on Dec. 7, 2020, entitled “Method of Manufacturing a Semiconductor Device,” now U.S. Pat. No. 11,848,240, issued on Dec. 19, 2023, which is a continuation of U.S. patent application Ser. No. 16/400,418, filed on May 1, 2019, entitled “Method of Manufacturing a Semiconductor Device,” now U.S. Pat. No. 10,861,746, issued on Dec. 8, 2020, which application claims the benefit of U.S. Provisional Application No. 62/773,716, filed on Nov. 30, 2018, which applications are hereby incorporated herein by reference.

Semiconductor devices are used in a variety of electronic applications, such as, for example, personal computers, cell phones, digital cameras, and other electronic equipment. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers of material over a semiconductor substrate, and patterning the various material layers using lithography to form circuit components and elements thereon.

The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continual reductions in minimum feature size, which allow more components to be integrated into a given area. However, as the minimum features sizes are reduced, additional problems arise that should be addressed.

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

Embodiments are described below with respect to a process utilized to form air spacers within a cut metal gate process. However, the embodiments may be applicable to a large variety of applications, and are not limited to those embodiments described herein.

1 FIG. 100 100 101 103 101 101 With reference now to, there is illustrated a perspective view of a semiconductor devicesuch as a finFET device. In an embodiment the semiconductor devicecomprises a substratewith first trenchesformed therein. The substratemay be a silicon substrate, although other substrates, such as semiconductor-on-insulator (SOI), strained SOI, and silicon germanium on insulator, could be used. The substratemay be a p-type semiconductor, although in other embodiments, it could be an n-type semiconductor.

103 105 103 101 103 The first trenchesmay be formed as an initial step in the eventual formation of first isolation regions. The first trenchesmay be formed using a masking layer along with a suitable etching process. For example, the masking layer may be a hardmask comprising silicon nitride formed through a process such as chemical vapor deposition (CVD), although other materials, such as oxides, oxynitrides, silicon carbide, combinations of these, or the like, and other processes, such as plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), or even silicon oxide formation followed by nitridation, may be utilized. Once formed, the masking layer may be patterned through a suitable photolithographic process to expose those portions of the substratethat will be removed to form the first trenches.

101 101 103 101 103 As one of skill in the art will recognize, however, the processes and materials described above to form the masking layer are not the only method that may be used to protect portions of the substratewhile exposing other portions of the substratefor the formation of the first trenches. Any suitable process, such as a patterned and developed photoresist, may be utilized to expose portions of the substrateto be removed to form the first trenches. All such methods are fully intended to be included in the scope of the present embodiments.

103 101 101 103 101 103 101 Once a masking layer has been formed and patterned, the first trenchesare formed in the substrate. The exposed substratemay be removed through a suitable process such as reactive ion etching (RIE) in order to form the first trenchesin the substrate, although any suitable process may be used. In an embodiment, the first trenchesmay be formed to have a first depth of less than about 5,000 Å from the surface of the substrate, such as about 2,500 Å.

103 103 However, as one of ordinary skill in the art will recognize, the process described above to form the first trenchesis merely one potential process, and is not meant to be the only embodiment. Rather, any suitable process through which the first trenchesmay be formed may be utilized and any suitable process, including any number of masking and removal steps may be used.

103 107 101 107 101 107 107 101 107 1 FIG. In addition to forming the first trenches, the masking and etching process additionally forms finsfrom those portions of the substratethat remain unremoved. For convenience the finshave been illustrated in the figures as being separated from the substrateby a dashed line, although a physical indication of the separation may or may not be present. These finsmay be used, as discussed below, to form the channel region of multiple-gate FinFET transistors. Whileonly illustrates four finsformed from the substrate, any number of finsmay be utilized.

107 101 107 107 107 The finsmay be formed such that they have a width at the surface of the substrateof between about 5 nm and about 80 nm, such as about 30 nm. Additionally, the finsmay be spaced apart from each other by a distance of between about 10 nm and about 100 nm, such as about 50 nm. By spacing the finsin such a fashion, the finsmay each form a separate channel region while still being close enough to share a common gate (discussed further below).

Additionally, while the above description provides one example embodiment, the fins may be patterned by any suitable method. For example, the fins may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. In one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fins.

103 107 103 103 105 103 Once the first trenchesand the finshave been formed, the first trenchesmay be filled with a dielectric material and the dielectric material may be recessed within the first trenchesto form the first isolation regions. The dielectric material may be an oxide material, a high-density plasma (HDP) oxide, or the like. The dielectric material may be formed, after an optional cleaning and lining of the first trenches, using either a chemical vapor deposition (CVD) method (e.g., the HARP process), a high density plasma CVD method, or other suitable method of formation as is known in the art.

103 103 101 103 107 107 107 The first trenchesmay be filled by overfilling the first trenchesand the substratewith the dielectric material and then removing the excess material outside of the first trenchesand the finsthrough a suitable process such as chemical mechanical polishing (CMP), an etch, a combination of these, or the like. In an embodiment, the removal process removes any dielectric material that is located over the finsas well, so that the removal of the dielectric material will expose the surface of the finsto further processing steps.

103 107 107 107 107 107 107 107 2 3 3 Once the first trencheshave been filled with the dielectric material, the dielectric material may then be recessed away from the surface of the fins. The recessing may be performed to expose at least a portion of the sidewalls of the finsadjacent to the top surface of the fins. The dielectric material may be recessed using a wet etch by dipping the top surface of the finsinto an etchant such as HF, although other etchants, such as H, and other methods, such as a reactive ion etch, a dry etch with etchants such as NH/NF, chemical oxide removal, or dry chemical clean may be used. The dielectric material may be recessed to a distance from the surface of the finsof between about 50 Å and about 1000 Å, such as about 540 Å. Additionally, the recessing may also remove any leftover dielectric material located over the finsto ensure that the finsare exposed for further processing.

103 As one of ordinary skill in the art will recognize, however, the steps described above may be only part of the overall process flow used to fill and recess the dielectric material. For example, lining steps, cleaning steps, annealing steps, gap filling steps, combinations of these, and the like may also be utilized to form and fill the first trencheswith the dielectric material. All of the potential process steps are fully intended to be included within the scope of the present embodiment.

105 113 107 107 107 After the first isolation regionshave been formed, a dummy gate dielectric (or interface oxide), a dummy gate electrode over the dummy gate dielectric, and first spacersmay be formed over each of the fins. In an embodiment the dummy gate dielectric may be formed by thermal oxidation, chemical vapor deposition, sputtering, or any other methods known and used in the art for forming a gate dielectric. Depending on the technique of gate dielectric formation, the dummy gate dielectric thickness on the top of the finsmay be different from the gate dielectric thickness on the sidewall of the fins.

2 3 2 3 2 2 The dummy gate dielectric may comprise a material such as silicon dioxide or silicon oxynitride with a thickness ranging from about 3 angstroms to about 100 angstroms, such as about 10 angstroms. The dummy gate dielectric may be formed from a high permittivity (high-k) material (e.g., with a relative permittivity greater than about 5) such as lanthanum oxide (LaO), aluminum oxide (AlO), hafnium oxide (HfO), hafnium oxynitride (HfON), or zirconium oxide (ZrO), or combinations thereof, with an equivalent oxide thickness of about 0.5 angstroms to about 100 angstroms, such as about 10 angstroms or less. Additionally, any combination of silicon dioxide, silicon oxynitride, and/or high-k materials may also be used for the dummy gate dielectric.

The dummy gate electrode may comprise a conductive material and may be selected from a group comprising of polysilicon (e.g., a dummy polysilicon (DPO)), W, Al, Cu, AlCu, W, Ti, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, Ta, TaN, Co, Ni, combinations of these, or the like. The dummy gate electrode may be deposited by chemical vapor deposition (CVD), sputter deposition, or other techniques known and used in the art for depositing conductive materials. The thickness of the dummy gate electrode may be in the range of about 5 {acute over (Å)} to about 200 {acute over (Å)}. The top surface of the dummy gate electrode may have a non-planar top surface, and may be planarized prior to patterning of the dummy gate electrode or gate etch. Ions may or may not be introduced into the dummy gate electrode at this point. Ions may be introduced, for example, by ion implantation techniques.

107 107 1 FIG. Once formed, the dummy gate dielectric and the dummy gate electrode may be patterned to form a series of stacks over the fins. The stacks define multiple channel regions located on each side of the finsbeneath the dummy gate dielectric. The stacks may be formed by depositing and patterning a gate mask (not separately illustrated in) on the dummy gate electrode using, for example, deposition and photolithography techniques known in the art. The gate mask may incorporate commonly used masking and sacrificial materials, such as (but not limited to) silicon oxide, silicon oxynitride, SiCON, SiC, SiOC, and/or silicon nitride and may be deposited to a thickness of between about 5 {acute over (Å)} and about 200 {acute over (Å)}. The dummy gate electrode and the dummy gate dielectric may be etched using a dry etching process to form the patterned stacks.

113 113 113 105 113 113 1 FIG. Once the stacks have been patterned, the first spacersmay be formed. The first spacersmay be formed on opposing sides of the stacks. The first spacersare typically formed by blanket depositing a spacer layer (not separately illustrated in) on the previously formed structure. The spacer layer may comprise SiCON, SiN, oxynitride, SiC, SiON, SiOC, oxide, and the like and may be formed by methods utilized to form such a layer, such as chemical vapor deposition (CVD), plasma enhanced CVD, sputter, and other methods known in the art. The spacer layer may comprise a different material with different etch characteristics or the same material as the dielectric material within the first isolation regions. The first spacersmay then be patterned, such as by one or more etches to remove the spacer layer from the horizontal surfaces of the structure, to form the first spacers.

113 113 113 113 In an embodiment the first spacersmay be formed to have a thickness of between about 10 {acute over (Å)} and about 100 {acute over (Å)}. Additionally, once the first spacershave been formed, a first spaceradjacent to one stack may be separated from a first spaceradjacent to another stack by a first distance of between about 50 {acute over (Å)} and about 500 {acute over (Å)}, such as about 200 {acute over (Å)}. However, any suitable thicknesses and distances may be utilized.

113 107 113 117 107 113 113 107 105 Once the first spacershave been formed, a removal of the finsfrom those areas not protected by the stacks and the first spacersand a regrowth of source/drain regionsmay be performed. The removal of the finsfrom those areas not protected by the stacks and the first spacersmay be performed by a reactive ion etch (RIE) using the stacks and the first spacersas hardmasks, or by any other suitable removal process. The removal may be continued until the finsare either planar with or below the surface of the first isolation regions.

107 117 107 117 117 107 107 117 117 Once these portions of the finshave been removed, a hard mask (not separately illustrated), is placed and patterned to cover the dummy gate electrode to prevent growth thereon and the source/drain regionsmay be regrown in contact with each of the fins. In an embodiment the source/drain regionsmay be regrown and, in some embodiments the source/drain regionsmay be regrown to form a stressor that will impart a stress to the channel regions of the finslocated underneath the stacks. In an embodiment wherein the finscomprise silicon and the FinFET is a p-type device, the source/drain regionsmay be regrown through a selective epitaxial process with a material, such as silicon, silicon germanium, silicon phosphorous, that has a different lattice constant than the channel regions. The epitaxial growth process may use precursors such as silane, dichlorosilane, germane, and the like, and may continue for between about 5 minutes and about 120 minutes, such as about 30 minutes. In other embodiments the source/drain regionsmay comprise materials such as GaAs, GaP, GaN, InP, InAs, InSb, GaAsP, AlGaN, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or combinations, or the like.

117 117 107 113 Once the source/drain regionsare formed, dopants may be implanted into the source/drain regionsby implanting appropriate dopants to complement the dopants in the fins. For example, p-type dopants such as boron, gallium, indium, or the like may be implanted to form a PMOS device. Alternatively, n-type dopants such as phosphorous, arsenic, antimony, or the like may be implanted to form an NMOS device. These dopants may be implanted using the stacks and the first spacersas masks. It should be noted that one of ordinary skill in the art will realize that many other processes, steps, or the like may be used to implant the dopants. For example, one of ordinary skill in the art will realize that a plurality of implantation processes may be performed using various combinations of spacers and liners to form source/drain regions having a specific shape or characteristic suitable for a particular purpose. Any of these processes may be used to implant the dopants, and the above description is not meant to limit the present embodiments to the steps presented above.

117 Additionally at this point the hard mask that covered the dummy gate electrode during the formation of the source/drain regionsis removed. In an embodiment the hard mask may be removed using, e.g., a wet or dry etching process that is selective to the material of the hard mask. However, any suitable removal process may be utilized.

1 FIG. 1 FIG. 119 119 119 119 2 also illustrates a formation of an inter-layer dielectric (ILD) layer(e.g., an ILD0 layer, represented inusing dashed lines to better illustrate the underlying structures). The ILD layermay comprise a material such as silicon oxide (SiO) or boron phosphorous silicate glass (BPSG), although any suitable dielectrics may be used. The ILD layermay be formed using a process such as PECVD, although other processes, such as LPCVD, may alternatively be used. The ILD layermay be formed to a thickness of between about 100 Å and about 3,000 Å.

119 119 119 119 119 113 After the ILD layerhas been formed, the ILD layermay be planarized in order to prepare the ILD layerfor further processing. In an embodiment the ILD layermay be planarized using a planarization process such as chemical mechanical polishing (CMP) so that the ILD layeris coplanar with the first spacers. However, any other suitable method, such as one or more etching processes, may also be utilized.

119 Once the ILD layerhas been planarized to expose the underlying dummy gate electrode, the dummy gate electrode and the dummy gate dielectric may then be removed. In an embodiment one or more etches, such as one or more wet etch processes, may be used to remove the dummy gate electrode and the dummy gate dielectric. However, any suitable removal process may be utilized.

115 115 2 2 5 Once the dummy gate electrode and dummy gate dielectric have been removed, the openings left behind may be refilled to form a gate stack. In a particular embodiment the gate stackcomprises a first dielectric material, a first metal material, a second metal material, and a third metal material. In an embodiment the first dielectric material is a high-k material such as HfO, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, LaO, ZrO, TaO, combinations of these, or the like, deposited through a process such as atomic layer deposition, chemical vapor deposition, or the like. The first dielectric material may be deposited to a thickness of between about 5 {acute over (Å)} and about 200 {acute over (Å)}, although any suitable material and thickness may be utilized.

The first metal material may be formed adjacent to the first dielectric material and may be formed from a metallic material such as Ti, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, TaN, Ru, Mo, WN, other metal oxides, metal nitrides, metal silicates, transition metal-oxides, transition metal-nitrides, transition metal-silicates, oxynitrides of metals, metal aluminates, zirconium silicate, zirconium aluminate, combinations of these, or the like. The first metal material may be deposited using a deposition process such as atomic layer deposition, chemical vapor deposition, sputtering, or the like, to a thickness of between about 5 {acute over (Å)} and about 200 {acute over (Å)}, although any suitable deposition process or thickness may be used.

The second metal material may be formed adjacent to the first metal material and, in a particular embodiment, may be similar to the first metal material. For example, the second metal material may be formed from a metallic material such as Ti, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, TaN, Ru, Mo, WN, other metal oxides, metal nitrides, metal silicates, transition metal-oxides, transition metal-nitrides, transition metal-silicates, oxynitrides of metals, metal aluminates, zirconium silicate, zirconium aluminate, combinations of these, or the like. Additionally, the second metal material may be deposited using a deposition process such as atomic layer deposition, chemical vapor deposition, sputtering, or the like, to a thickness of between about 5 {acute over (Å)} and about 200 {acute over (Å)}, although any suitable deposition process or thickness may be used.

The third metal material fills a remainder of the opening left behind by the removal of the dummy gate electrode. In an embodiment the third metal material is a metallic material such as W, Al, Cu, AlCu, W, Ti, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, Ta, TaN, Co, Ni, combinations of these, or the like, and may be deposited using a deposition process such as atomic layer deposition, chemical vapor deposition, sputtering, or the like to fill and/or overfill the opening left behind by the removal of the dummy gate electrode. In a particular embodiment the third metal material may be deposited to a thickness of between about 5 {acute over (Å)} and about 500 {acute over (Å)}, although any suitable material, deposition process, and thickness may be utilized.

107 Once the opening left behind by the removal of the dummy gate electrode has been filled, the materials may be planarized in order to remove any material that is outside of the opening left behind by the removal of the dummy gate electrode. In a particular embodiment the removal may be performed using a planarization process such as chemical mechanical polishing, until the gate stacks have a height over the finsof between about 400 {acute over (Å)} and about 600 {acute over (Å)}, such as about 490 {acute over (Å)}. However, any suitable planarization and removal process may be utilized.

2 2 FIGS.A-C 1 FIG. 2 FIG.A 2 FIG.A 107 201 101 115 203 101 115 115 201 115 203 illustrate different cross-sectional views ofalong lines A-A′, B-B′ and C-C′. In particular,illustrates a cross-sectional view taken along the length of the finin a first regionof the substrate, and illustrates the gate stacksformed after the removal of the dummy gate electrode and dummy gate dielectric.has also been expanded to show a second regionof the substratewhich has a gate stackwith different gate length. In one embodiment, the gate stackswithin the first regionhave a first gate length GL1 of between about 400 {acute over (Å)} and about 600 {acute over (Å)}, such as about 500 {acute over (Å)}, while the gate stackswithin the second regionhave a second gate length GL2 of between about 1,000 {acute over (Å)} and about 3,000 {acute over (Å)}, such as about 2,000 {acute over (Å)}. However, any suitable gate lengths may be utilized.

2 FIG.B 1 FIG. 107 115 115 107 107 illustrates a cross-sectional view oftaken along line B-B′ and illustrates the finslocated beneath the gate stacks. As can be seen, a single gate stackextends over multiple ones of the fins. Additionally, while four such finsare illustrated, this number is intended to be illustrative and is not intended to be limiting in any fashion.

2 FIG.C 1 FIG. 117 201 101 117 illustrates a cross-sectional view oftaken along line C-C'. This view illustrates the view of the source/drain regionsin the first regionof the substrate. Additionally, while four such source/drain regionsare illustrated, this number is intended to be illustrative and is not intended to be limiting in any fashion.

3 3 FIGS.A-C 301 303 301 301 illustrate a formation of a first hard maskand a second hard maskover the structure. In an embodiment the first hard maskis a material such as titanium nitride or tantalum nitride formed through a deposition process such as atomic layer deposition (ALD), chemical vapor deposition (CVD), or physical vapor deposition (PVD). The first hard maskmay be formed to a thickness of between about 3 nm and about 10 nm, such as about 5 nm. However, any suitable material, process of deposition, and thicknesses may be utilized.

301 303 301 303 Once the first hard maskhas been deposited, the second hard maskmay be deposited to cover the first hard mask. In an embodiment the second hard maskmay be a single layer of material or else may be one or more layers of material, such as a dual layer of materials. In an embodiment one layer or each layer of materials may comprise a material such as silicon nitride or silicon carbon nitride (SiCN). However, any suitable material or combination of materials may be utilized.

303 In an embodiment in which the second hard maskcomprises two sub-layers, the first sub-layer may be deposited using a deposition process such as ALD, CVD, or PVD to a thickness of between about 30 nm and about 40 nm, such as about 34 nm. Additionally, the second sub-layer may also be deposited using a deposition process such as ALD, CVD, or PVD to a thickness of between about 30 nm and about 40 nm, such as about 34 nm. However, any suitable deposition process and any suitable thicknesses may be utilized.

303 303 303 303 303 303 2 2 Optionally, if desired, after the second hard maskhas been formed, a surface treatment of the second hard maskmay be performed in order to help protect the second hard maskand prepare the second hard maskfor additional processing. In an embodiment the surface treatment may be a descum treatment such as a plasma treatment wherein the surface of the second hard maskis exposed to a plasma of, e.g., argon, nitrogen, oxygen or a mixed Ar/N/Oambient environment in order to improve the interface adhesion between the second hard maskand overlying layers. However, any suitable surface treatment may be utilized.

4 4 FIGS.A-C 303 303 401 303 401 303 401 403 405 407 illustrate that, after the optional surface treatment, the second hard maskmay be patterned in order to provide a masking layer for a subsequent etching process. In an embodiment the patterning of the second hard maskmay be initiated by placing a first photoresistover the second hard maskand then exposing and developing the first photoresistto pattern the second hard mask. In an embodiment the first photoresistis a tri-layer photoresist, with a bottom anti-reflective coating (BARC) layer, an intermediate mask layer, and a top photoresist layer. However, any suitable type of photosensitive material or combination of materials may be utilized.

5 5 FIGS.A-B 401 401 303 illustrate that once the first photoresisthas been patterned, the pattern of the first photoresistis then transferred to the second hard mask. In an embodiment the transfer of the pattern can occur using, e.g., an anisotropic etching process such as a reactive ion etching process. However, any suitable process may be utilized.

303 401 407 407 407 407 405 403 Additionally, once the second hard maskhas been patterned, the first photoresistmay be removed. In an embodiment the top photoresist layermay be removed using a thermal process such as ashing, whereby the temperature of the top photoresist layeris increased until the top photoresist layerundergoes a thermal decomposition and can be easily removed. Once the top photoresist layerhas been removed, the intermediate mask layerand the bottom anti-reflective coating layermay be removed using one or more etching processes.

401 2 4 2 2 If desired, a wet clean may be performed during or after the removal of the first photoresist. In an embodiment a solution such as an SC-1 or SC-2 cleaning solution may be utilized, although other solutions, such as a mixture of HSOand HO(known as SPM), or a solution of hydrogen fluoride (HF), may alternatively be utilized. Any suitable solution or process that may be used are fully intended to be included within the scope of the embodiments.

6 6 FIGS.A-C 601 601 303 303 601 601 303 illustrate a deposition of a masking layerwhich is used to help initiate a cut metal gate process. In an embodiment the masking layermay be made of a material that is similar to the material of the second hard mask. As such, in an embodiment in which the second hard maskis formed of silicon nitride, the masking layermay also be formed of silicon nitride. However, the masking layermay also be made of different materials or different compositions from the second hard mask.

601 601 In an embodiment the masking layermay be deposited using a deposition process such as atomic layer deposition, chemical vapor deposition, sputtering, combinations of these, or the like. Additionally, the masking layermay be formed to a thickness of between about 3 nm and about 7 nm, such as about 5 nm. However, any suitable deposition process and any suitable thickness may be utilized.

7 7 FIGS.A-B 601 601 601 601 301 115 701 115 113 119 illustrates a continuation of the cut metal gate process that can be performed once the masking layerhas been deposited. In an embodiment the bottom portion of masking layermay be removed in an anisotropic etching process. The vertical portions of masking layerremain in the opening, and the width of the opening is reduced by the remaining portions of masking layer. Next, the underlying first hard maskand the gate stackare etched to form trench, which initially extends to an intermediate level of gate stack. The first spacersand the exposed portions of ILD layerare also etched.

2 3 4 4 115 701 115 In accordance with some embodiments of the present disclosure, the etching is performed using process gases selected from, and not limited to, Cl, BCl, Ar, CH, CF, and combinations thereof. The etching of gate stacksmay be performed with a pressure in the range between about 2.5 mTorr and about 25 mTorr. An RF power is applied in the main etching, and the RF power may be in the range between about 250 Watts and about 2,500 Watts. A bias voltage in the range between about 25 volts and about 750 volts may also be applied. The etching may be stopped when the bottom surface of the trenchis at an intermediate level between a top surface and a bottom surface of gate stack.

601 601 701 701 701 601 601 601 4 2 2 Subsequently, a second deposition process to reform the masking layeris performed. The second deposition process to reform the masking layerincludes sidewall portions on the sidewalls of the trenchto protect the sidewalls, so that the upper portions of the trenchare not laterally expanded when the trenchis extended downwardly. In accordance with some embodiments of the present disclosure, the second deposition process to form the masking layeris performed using process gases including SiCl, O, Ar, and the like. As such, the resulting masking layerincludes SiOtherein instead of, e.g., silicon nitride, which may or may not be compounded with additional elements such as carbon. The resulting masking layermay be formed to have a thickness of between about 2 nm and about 4 nm, such as about 3 nm.

601 701 601 601 601 701 4 6 Next, a dielectric breaking process is performed, so that the bottom portion of the reformed masking layerat the bottom of the trenchis removed in an anisotropic etching/bombardment process. In accordance with some embodiments, a carbon-and-fluorine gas (such as CF) is used to etch the bottom portion of the second masking layer. The thickness of the portion of masking layeron the top surface of the masking layermay be reduced during the etching process. The thickness of the portions of the masking layeron the sidewalls of the trenchmay also be reduced during the etching process.

701 115 115 x y 2 Another etching process is performed to extend the trenchdeeper into the gate stack. The etching is performed using an appropriate etching gas, depending on the material of the etched portion of gate stack. In accordance with some embodiments, a polymer such as CHmay be formed (with X and Y being integers) at the bottom of opening. The polymer may then be removed, for example, using oxygen (O).

115 701 701 115 701 105 601 701 701 7 7 FIGS.A-C 7 FIG.B In accordance with some embodiments, the etching of gate stackincludes a plurality of deposition-etching cycles, each including a dielectric-deposition process, a dielectric breaking process, an etching process to extend the trenchdown, and possibly a polymer removal process. Each of the deposition-etching cycles results in the trenchextending further down, until gate stackis etched through, and the trenchextends into first isolation region. In some embodiments, the process may be repeated two to ten times, although any suitable number of repetitions may be utilized. The resulting structure is shown in. After the last etching process, no more dielectric layer is deposited, and hence in, the bottom ends of masking layerare higher than the bottom of the trench. The polymer layer, if any in trench, is removed.

Once the cut metal gate process has been completed, an optional rinsing process may be utilized to help clean any residual debris or reactants. In an embodiment a rinse using a material such as deionized water may be placed in contact with the structure. However, any suitable rinse process may be utilized.

8 8 FIGS.A-C 8 FIG.D 601 601 601 601 601 800 3 3 4 2 6 illustrate a removal of the silicon oxide within the remnants of the masking layer. In one embodiment the removal of the silicon oxide from the masking layermay be performed by introducing hydrogen fluoride (HF) and ammonia (NH) as etchants to the masking layer. The HF and NHmay react with each other and with the oxide present in the masking layerto produce (NH)SiFon a surface of the masking layer. In a particular embodiment the hydrogen fluoride and the ammonia may be flowed into the reaction chamber at a flow ratio of between about 1:5 and about 5:1 (with results of a 5:1 flow ratio being illustrated inand wherein lower ranges will lead to an incomplete reaction), such as flowing the hydrogen fluoride into the reaction chamber at a flow rate of between about 100 sccm andsccm such as about 200 sccm, while flowing the ammonia into the reaction chamber at a flow rate of between about 50 sccm and 300 sccm such as about 100 sccm. However, any suitable flow rates and ratios may be utilized.

8 FIG.D Under these conditions, the process temperature may be selected in order to help increase the selectivity of the reaction. As illustrated in, while the temperature of the process may be set to be between about 30° C. and about 120° C., a temperature above 110° C., such as between about 115° C. and about 120° C., will help to modify the activation energies (e.g., “EAs”) of the etching process and, hence, the selectivity of the etching process to primarily etch the oxide that is present while only minimally removing the surrounding material (e.g., silicon nitride). However, any suitable temperature may be chosen.

8 FIG.E Similarly under these conditions, the process pressure may also be selected in order to help increase the selectivity of the reaction. As illustrated in, while the pressure of the process may be set to be between about 0.1 Torr and about 5 Torr, a pressure of less than 2.5 Torr, such as between about 1.5 Torr and about 2 Torr, will help to modify the selectivity of the etching process to primarily etch the oxide that is present while only minimally removing the surrounding material (e.g., silicon nitride). However, any suitable pressure may be chosen.

To determine when the reaction has completed, a timing of the process may be utilized. In some embodiments the reaction may be continued for a time of between about 1 second and about 5 seconds, such as about 2 seconds. However, any suitable time and any suitable method for deciding when to stop the etching process may be utilized.

601 601 601 601 601 4 2 6 4 2 6 2 2 4 3 4 2 6 Once the reaction has completed, the masking layermay be heated using an annealing process in order to remove the (NH)SiF, thereby removing the silicon oxide from the masking layer. The heat may cause the (NH)SiFto thermally decompose to N, HO, SiF, and NH, all of which may be vapor and may be removed from the surface of the masking layerby the annealing process. In an embodiment of the annealing process the masking layermay be heated to a temperature of between about 80° C. to about 200° C., such as about 100° C. for between about 60 seconds to about 180 seconds to remove the (NH)SiFfrom the masking layer.

4 2 6 601 After the (NH)SiFhas been removed, the masking layeris again exposed and may be further processed. In an embodiment a second etching process, such as a second etch process similar to the first etch process described above, may be performed to remove any remaining residual silicon oxide. However, as one of ordinary skill in the art will recognize, the precise type of etching process, the number of iterations of the CERTAS® process, and the process parameters for the etching process, as described above are intended to be illustrative only, as any number of iterations and process parameters may be utilized.

2 4 2 2 Optionally, after the removal of the oxide, a second wet clean may be performed to prepare the structure for subsequent processing. In an embodiment a solution such as an SC-1 or SC-2 cleaning solution may be utilized, although other solutions, such as a mixture of HSOand HO(known as SPM), or a solution of hydrogen fluoride (HF), may alternatively be utilized. Any suitable solution or process that may be used are fully intended to be included within the scope of the embodiments.

9 9 FIGS.A-B 701 901 115 901 illustrate a filling of the trencheswith a fill materialto finish the separation of the gate stack. In an embodiment the fill materialmay be a single layer of material or else may be one or more layers of material, such as a dual layer of materials. In an embodiment one layer or each layer of materials may comprise a material such as silicon nitride or silicon carbon nitride (SiCN). However, any suitable material or combination of materials may be utilized.

901 901 In an embodiment the fill materialmay be deposited using a deposition process such as ALD, CVD, or PVD to a thickness of between about 20 nm and about 30 nm, such as about 25 nm. However, any suitable deposition process and any suitable thicknesses may be utilized for the fill material.

10 10 FIGS.A-C 901 301 901 115 113 301 illustrate a planarization of the fill materialand a removal of the first hard mask. In an embodiment the planarization may be a process such as a chemical mechanical polishing process which is utilized to planarize the fill materialwith the gate stacksand the first spacers. During the process the first hard maskis also removed.

901 115 115 107 Additionally, the chemical mechanical polishing process that is used to remove excess fill materialmay be also be utilized to reduce the height of the gate stacksat this time. In an embodiment the height of the gate stacksover the finsmay be reduced to a height of between about 200 {acute over (Å)} and about 400 {acute over (Å)}. However, any suitable reduction of height may be utilized.

11 11 FIGS.A-C 119 1101 119 illustrate a recessing of the ILD layerto form recessesin preparation for formation of a dielectric helmet. In an embodiment the ILD layermay be recessed using one or more etching processes, such as a wet etching process to a depth of between about 10 nm and about 30 nm, such as about 20 nm. However, any suitable depth may be utilized.

12 12 FIGS.A-C 1201 1201 1201 119 illustrate a deposition of a helmet materialand subsequent planarization process. In an embodiment the helmet materialmay be a dielectric material such as silicon oxycarbide (SiOC) or silicon and the helmet materialmay be deposited to fill and/or overfill the recesses formed by the recessing of the ILD layerusing a deposition process such as chemical vapor deposition, atomic layer deposition, or sputtering. However, any suitable materials and deposition processes may be utilized.

1201 1201 1201 115 113 Subsequent to the deposition of the helmet material, a planarization of the helmet materialis performed. In an embodiment the planarization may be a process such as a chemical mechanical polishing process which is utilized to planarize the helmet materialwith the gate stackand the first spacers.

1201 115 115 107 Additionally, the chemical mechanical polishing process that is used to planarize the helmet materialmay be also be utilized to reduce the height of the gate stacksat this time. In an embodiment the height of the gate stacksover the finsmay be reduced to a height of between about 200 {acute over (Å)} and about 300 {acute over (Å)}. However, any suitable reduction of height may be utilized.

13 13 FIGS.A-C 113 1301 115 113 1301 113 113 113 illustrate a removal of the first spacersand the formation of a voidaround the gate stacks. In an embodiment a photoresist may be placed and patterned to protect those areas where removal is not desired, and then one or more etching process may be utilized to partially or fully remove the first spacersand form voidswhere the first spacershad previously resided. In one particular embodiment a wet etching process selective to the material or materials of the first spacersmay be utilized to remove the first spacerswithout significantly removing the surrounding materials.

115 113 901 119 113 901 119 105 8 8 FIGS.A-E However, because any residual oxygen along the sidewalls of the gate stackshas been previously removed prior to the filling of the trenches (as discussed above with respect to), this oxygen is not present during the removal of the first spacers. In particular, in previous processes in which the residual oxygen is still present between the fill materialand the ILD layer, the etching and removal of the first spacerswould also attack and remove the residual oxygen, opening up a pathway between the fill materialand the ILD layer. This pathway would allow the etchants to extend to and attack the underlying isolation region.

901 901 119 113 901 119 113 105 105 113 113 1403 14 14 FIGS.A-C However, because the currently described process removes the residual oxygen that was present prior to the formation of the fill material, the fill materialwill be formed to make direct contact with the material of the ILD layer, forming a seal that does not include the residual oxygen. Accordingly, during the removal process of the first spacers, there is no oxygen to be removed between the fill materialand the ILD layer, and no open pathway occurs. This prevention of formation of the pathway prevents any of the etchants that are used during the removal of the first spacersfrom penetrating to the underlying first isolation regionand removing material from the first isolation region. By preventing this pathway and reducing the damage from this pathway, the time limitations that were previously present during the etching of the first spacersto prevent such penetration can be removed, thereby widening the overall process window for the removal of the first spacersand the formation of the air spacers(illustrated further below with respect to) is enlarged.

14 14 FIGS.A-C 1401 1403 115 1401 1401 1401 113 1403 1401 1403 1403 illustrate a deposition of a cap layerand formation of an air spaceradjacent to the gate stacks. In an embodiment the cap layercan be an appropriate dielectric material, which may further be a low-k dielectric layer that has a dielectric constant (k) value less than 3.9, which may further be less than 2.0. In some embodiments, the dielectric material of the cap layeris silicon nitride (SiN), silicon carbon oxynitride (SiCON), silicon oxycarbide (SiOC), or the like. The cap layercan be formed using an appropriate deposition technique, such as ALD, CVD, or the like. If the aspect ratio of the openings is sufficiently high, the deposition will seal off the void formed by the removal of the first spacersand form the air spacer. A gas, such as a gas(es) used during the deposition of the dielectric material of the cap layeror any other species that can diffuse into air spacer, may be in the air spacers.

1401 1201 115 1401 1201 115 A planarization process, such as a CMP, may be performed to remove excess dielectric material of the cap layerfrom the top surfaces of the helmet materialand the gate stacks. As such, the cap layermay be planar with both the helmet materialas well as the gate stacks.

1401 115 115 107 Additionally, the chemical mechanical polishing process that is used to remove excess dielectric material of the cap layermay be also be utilized to reduce the height of the gate stacksat this time. In an embodiment the height of the gate stacksover the finsmay be reduced to a height of between about 140 {acute over (Å)} and about 160 {acute over (Å)}. However, any suitable reduction of height may be utilized.

113 1403 113 113 By removing residual oxygen from previous processes prior to the removal of the first spacersto form the air spacers, this oxygen is not present and cannot be removed during the removal of the first spacers. As such, no pathway can be formed that allows the etchants to penetrate into undesired areas of the structure, where the etchants can cause further damage. This allows for a widening of the process window for the removal of the first spacersand helps to improve the overall efficiency and yield of the manufacturing process.

In an embodiment, a method of manufacturing a semiconductor device includes: forming a metal gate over a semiconductor fin; cutting the metal gate into a first metal gate and a second metal gate, wherein after the cutting the metal gate, an oxide is present on a sidewall of the first metal gate; removing the oxide from the sidewall of the first metal gate; and filling a region between the first metal gate and the second metal gate with a dielectric material, wherein the dielectric material is in physical contact with the sidewall of the first metal gate. In an embodiment the method further includes removing a spacer from a second sidewall of the first metal gate after the removing the oxide from the sidewall, the removing the spacer creating a void. In an embodiment the method further includes capping the void to form an air spacer. In an embodiment the removing the oxide is performed at a temperature between about 115° C. and about 120° C. In an embodiment the removing the oxide is performed at a pressure of between about 1.5 Torr and about 2 Torr. In an embodiment the removing the oxide is performed at least in part with a mixture of hydrogen fluoride and ammonia. In an embodiment the cutting the metal gate is performed at least in part with cyclic deposition and etch processes.

In another embodiment a method of manufacturing a semiconductor device includes removing a dummy gate between spacers over a semiconductor fin; replacing the dummy gate with a gate stack; removing a portion of the gate stack with a cyclical etching process to form an opening, the cyclical etching process leaving an oxide material along sidewalls of the opening; removing the oxide material from along the sidewalls of the opening; after the removing the oxide material, filling the opening with a dielectric material; applying an etchant to the spacers and also to a portion of an interface between the dielectric material and the gate stack, wherein the etchant removes the spacers to form a void but does not interject between the dielectric material and the gate stack; and capping the void to form an air spacer adjacent to the gate stack. In an embodiment the method further includes after the filling the opening with the dielectric material, recessing an interlayer dielectric to form a recess. In an embodiment the method further includes filling the recess with a second dielectric material. In an embodiment each cycle of the cyclical etching process comprises: depositing a liner material; etching through the liner material; and using the liner material as a mask to etch the gate stack. In an embodiment the removing the oxide material is performed at a temperature between about 115° C. and about 120° C. In an embodiment the removing the oxide material is performed at a pressure of between about 1.5 Torr and about 2 Torr. In an embodiment the removing the oxide material is performed at least in part with a mixture of hydrogen fluoride and ammonia.

In yet another embodiment a method of manufacturing a semiconductor device includes: patterning a hard mask layer to form an opening over a conductive gate over a semiconductor fin; depositing a first liner in the opening; etching a first bottom of the first liner to expose the conductive gate; etching the conductive gate through the first liner; depositing a second liner within the opening; etching a second bottom of the second liner to expose the conductive gate; etching the conductive gate through the second liner; removing an oxide from a sidewall of the conductive gate after the etching the conductive gate; applying a dielectric material to the sidewall of the conductive gate after the removing the oxide; after the applying the dielectric material to the sidewall, removing spacers from adjacent to the conductive gate to form a void around the conductive gate; and capping the void to form air spacers around the conductive gate. In an embodiment the removing the oxide from the sidewall is performed at least in part with a mixture of hydrogen fluoride and ammonia. In an embodiment the removing the oxide further comprises an annealing process. In an embodiment the annealing process is performed at a temperature of between about 80° C. to about 200° C. In an embodiment the removing the oxide is performed at a pressure of between about 1.5 Torr and about 2 Torr. In an embodiment the method further includes: recessing an interlayer dielectric to form a recess; and filling the recess with a dielectric material.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.