Semiconductor Package

This application claims priority to and the benefit of Korean Patent Application No. 10-2024-0164014 filed at the Korean Intellectual Property Office on Nov. 18, 2024, the entire contents of which are incorporated herein by reference.

The present disclosure relates to a semiconductor package.

In the semiconductor package industry, a multi-layer ceramic capacitor (MLCC) may be mounted side by side with a semiconductor chip on a substrate to improve signal quality, and the MLCC may be connected to the semiconductor chip through the substrate.

When mounting the MLCC on a substrate, there is a problem in that mounting space for the MLCC is required and it may be difficult to utilize the MLCC mounting space as a wiring space.

In one aspect, some embodiments provide a semiconductor package capable of improving signal quality without increasing size.

In another aspect, some embodiments provide a semiconductor package capable of securing freedom in wiring design.

In another aspect, some embodiments provide a semiconductor package having low inductance by connecting passive elements and a semiconductor chip with a short electrical path.

Some embodiments provide a semiconductor package including a substrate, a semiconductor chip disposed on the substrate and electrically connected to the substrate, an encapsulant covering at least a portion of the semiconductor chip, the encapsulant including a groove portion at least partially disposed above the semiconductor chip, a passive element disposed at least partially within the groove portion, and a conductive pillar embedded at least partially in the encapsulant and electrically connecting the semiconductor chip and the passive element.

Some embodiments provide a semiconductor package including a substrate; a semiconductor chip disposed on the substrate and including a first connection pad, a second connection pad, and a third connection pad; an encapsulant covering at least a portion of the semiconductor chip, the encapsulant including a groove portion, at least a portion of the groove portion is disposed above the semiconductor chip; a passive element disposed at least partially within the groove portion and including a first external electrode and a second external electrode; a first conductive wire embedded at least partially in the encapsulant and electrically connecting the first connection pad to the substrate; a first conductive pillar embedded at least partially in the encapsulant and electrically connecting the second connection pad to the first external electrode; and a second conductive pillar embedded at least partially in the encapsulant and electrically connecting the third connection pad to the second external electrode.

Some embodiments provide a semiconductor package including a substrate; a chip stacking structure disposed on the substrate and including a plurality of stacked first semiconductor chips; an encapsulant covering at least a portion of the chip stacking structure, the encapsulant including a groove portion at least partially disposed above the chip stacking structure; a passive element disposed at least partially within the groove portion; and a conductive pillar embedded at least partially in the encapsulant and electrically connecting one of the first semiconductor chips to the passive element.

The present disclosure will be described in detail hereinafter with reference to the accompanying drawings, in which embodiments of the present disclosure are shown. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the scope of the present disclosure.

The drawings and description are to be regarded as illustrative in nature and not restrictive, and like reference numerals designate like elements throughout the specification.

Further, since sizes and thicknesses of constituent members shown in the accompanying drawings may be arbitrarily given to facilitate understanding and ease of description, the disclosure is not limited to the illustrated sizes and thicknesses. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. In the drawings, to facilitate understanding and ease of description, the thicknesses of some layers and regions may be exaggerated.

Throughout the specification, the term “connected” may mean not only “directly connected,” but also “indirectly connected” with another element in between. In a similar perspective, this includes being “physically connected,” as well as being “electrically connected.”

It should be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” another element, it may be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” another element, there are no intervening elements present. Further, being “on” or “above” a reference element means being above or below the reference element, and it may not necessarily mean being positioned “on” or “above” it in a direction opposite to gravity.

In addition, unless explicitly stated to the contrary, the word “comprise” and variations such as “comprises” and “comprising” should be understood to imply the inclusion of stated elements but not the exclusion of any other elements.

In addition, the phrase “on a plane” means a view from a position above the object (e.g., from the top), and the phrase “in a cross-section” means a view of a cross-section of the object which is vertically cut from the side.

In addition, throughout the specification, although the terms “first,” “second,” and the like are used to explain various components, the components are not limited to such terms but are only used to distinguish one component from another component. Accordingly, a configuration referred to as the first component in a certain part of the specification may also be referred to as the second component in other parts of the specification.

As used herein, singular forms are intended to include plural forms unless the context clearly indicates otherwise. For example, “insulating layer” may be used to mean not just a single insulating layer, but a plurality of insulating layers, such as two, three, or more.

Additionally, throughout the specification, references to directions such as upper surface, upper side, upper part, lower surface, lower side, and lower part are intended to aid description and understanding with reference to the drawings.

Hereinafter, a semiconductor package according to embodiments of the present disclosure will be described with reference to the drawings.

1 5 FIGS.- 100 110 130 130 140 150 160 g Referring to, a semiconductor packageA according to an embodiment may include a substrate, a chip stacking structure CS, an encapsulanthaving a groove portion, a passive element, a conductive pillar, and a semiconductor chip.

130 3 4 FIGS.and To clearly illustrate the layout of connection pads and conductive wires, the encapsulantis assumed to be transparent in.

110 The substratemay be a printed circuit board (PCB).

110 110 110 160 110 122 110 110 On an upper surface of the substrate, there may be padsP for electrical connection with other components mounted on the substrate, such as the chip stacking structure CS and the semiconductor chip. The padsP may each be bonded to a conductive wireand electrically connected to a wiring layer of the substrate. The material of the padP may be a conductive material such as copper (Cu), aluminum (Al), nickel (Ni), gold (Au), silver (Ag), palladium (Pd), titanium (Ti), or an alloy thereof.

110 110 120 The chip stacking structure CS is disposed on the substrateand electrically connected to the substrate, and may include a plurality of stacked semiconductor chips.

110 110 The number of chip stacking structures CS disposed on the substrateis not particularly limited and may be more or less than that shown in the drawings. For example, only a single chip stacking structure CS may be disposed on the substrate, or four, six, or more chip stacking structures CS may be so disposed.

120 120 The number of semiconductor chipsincluded in the chip stacking structure CS is not particularly limited and may be more or less than that shown in the drawings. For example, a chip stacking structure CS may include four, sixteen, or thirty-two stacked semiconductor chips.

120 120 120 120 120 Each semiconductor chipmay include connection padsP. The connection padsP may be arranged to deviate toward one edge of each semiconductor chip. For example, the connection padsP may be arranged in a first direction, e.g., the Y direction (Y).

122 150 120 122 150 120 120 120 120 The conductive wireand/or the conductive pillarmay be connected to the connection padP. For connection of the conductive wireand/or the conductive pillar, the semiconductor chipsmay be stacked in an offset manner so that the connection padsP are not covered by other semiconductor chips. For example, the semiconductor chipsmay be stacked with their edges offset in a second direction perpendicular to the first direction, e.g., the X direction (X).

120 120 130 120 120 110 g The semiconductor chipmay be disposed so that the surface on which the connection padP is disposed faces the groove portionin a vertical direction. In other words, the semiconductor chipmay be disposed so that the surface opposite to the surface on which the connection padP is disposed faces the substratein the vertical direction.

120 The material of the connection padP may be a conductive material such as copper (Cu), aluminum (Al), nickel (Ni), gold (Au), silver (Ag), palladium (Pd), titanium (Ti), or an alloy thereof.

120 140 150 120 120 150 140 120 1 120 140 150 120 2 Some of the connection padsP may be connected to the passive elementthrough the conductive pillar. In some embodiments, among the connection padsP, the connection padP that is not connected to the conductive pillarand the passive elementmay be referred to as a first connection padPand the connection padP that is connected to the passive elementthrough the conductive pillarmay be referred to a second connection padP.

120 The semiconductor chipmay include a memory chip. The memory chips may be stacked in the vertical direction to form memory devices such as 3D NAND flash memory, high bandwidth memory (HBM), and 3D DRAM.

120 120 110 121 121 120 110 120 121 120 110 120 Each semiconductor chipmay be attached to another semiconductor chipor the substratethrough an adhesive member. In other words, the adhesive membermay be disposed between the chip stacking structure CS (the lowest semiconductor chip among the semiconductor chipsof the chip stacking structure CS) and the substrate, and between the semiconductor chips. For example, the adhesive membermay be attached to another semiconductor chipor the substratewhile being attached to a lower surface (in the vertical direction) of the semiconductor chip.

121 An adhesive material such as a die attach film (DAF) may be used as the material of the adhesive member.

120 110 120 120 122 120 110 120 122 120 120 130 Each semiconductor chipmay be electrically connected to the substrateand/or another semiconductor chip. In an embodiment, each semiconductor chipmay have the conductive wirebonded thereto that connects the semiconductor chipto the substrateor to another semiconductor chip. The conductive wiremay be connected to the connection padP of the semiconductor chipand embedded in the encapsulant.

122 120 1 120 122 1 20 1 120 110 122 120 1 120 122 120 1 120 110 A first conductive wireA may connect the first connection padsPof the semiconductor chipsto each other. A second conductive wireB may connect the first connection padsPof the semiconductor chipto the substrate. For example, the first conductive wiresA may connect the first connection padsPof the adjacent semiconductor chipsto each other and the second conductive wiresB may connect the first connection padPof the lowest semiconductor chip among the semiconductor chipsto the substrate.

122 120 2 140 110 122 122 122 120 2 110 122 140 110 120 2 110 120 122 122 A third conductive wireC may electrically connect the second connection padP, the passive element, and the substrate. The third conductive wireC may be a long wire having a longer length than the first conductive wireA and the second conductive wireB. By connecting the second connection padPto the substratethrough the third conductive wireC, the electrical connection path between the passive elementand the substratemay be minimized. In some embodiments, the second connection padPmay be connected to the substratevia the semiconductor chipsthrough the second conductive wireB and the first conductive wireA.

122 The material of the conductive wiresmay be a conductive material such as copper (Cu), aluminum (Al), nickel (Ni), gold (Au), silver (Ag), palladium (Pd), titanium (Ti), or an alloy thereof.

122 120 110 120 In addition to the conductive wire, each semiconductor chipmay be electrically connected to the substrateand/or another semiconductor chipthrough other components such as a through silicon via (TSV); not shown in the figures.

122 150 The encapsulant 130 may cover at least a portion of each of the chip stacking structure CS, the conductive wire, and the conductive pillar.

130 140 130 130 140 130 g g g The groove portionfor disposing the passive elementmay be formed in the encapsulant. The groove portionmay include a bottom surface bs and a wall surface ws extending in the vertical direction, e.g., the Z direction (Z), perpendicular to the bottom surface bs. The passive elementmay be disposed on the bottom surface bs of the groove portionand surrounded by the wall surface ws.

130 130 130 130 130 130 g g g The groove portionmay be formed by removing a portion of the encapsulantin the vertical direction from an upper surface of the encapsulanttoward the bottom surface bs of the groove portion. When forming the groove portion, the encapsulantmay be processed using a mechanical drill, laser, or similar cutting methods.

130 130 120 150 140 120 130 150 g g g At least a portion of the groove portionmay be positioned on the chip stacking structure CS. For example, at least a portion of the groove portionmay be positioned on the semiconductor chipconnected to the conductive pillar. Accordingly, the passive elementand the semiconductor chipdisposed within the groove portionmay be connected by a short path through the conductive pillar.

130 1 5 140 2 6 1 2 5 6 g The groove portionmay have a first cross-sectional width win the second direction (e.g., the X direction) and a second cross-sectional width win the first direction (e.g., the Y direction). The passive elementmay have a first cross-sectional width win the second direction (e.g., the X direction) and a second cross-sectional width win the first direction (e.g., the Y direction). In some embodiments, the first width wmay be greater than or equal to the first width w. In some embodiments, the second width wmay be greater than or equal to the second width w. As used herein, the cross-sectional width means the width in the X direction (X) in the X-Z plane or the width in the Y direction (Y) in the Y-Z plane.

1 5 130 2 6 140 140 130 150 1 5 130 2 6 140 140 130 g g g g. For example, the cross-sectional widths wand wof the groove portionmay be slightly larger than the cross-sectional widths wand wof the passive element, and the passive elementmay be inserted into the groove portionso as to be aligned with the conductive pillar. Alternatively, the cross-sectional widths wand wof the groove portionmay be the same as the cross-sectional widths wand wof the passive element, and the passive elementmay fit snugly into the groove portion

1 130 1 140 1 130 1 140 140 130 140 141 140 1 130 1 140 141 1 130 1 140 140 130 g g g g g 2 FIG. A depth dof the groove portionin the vertical direction may be greater than or equal to a thickness tof the passive elementin the vertical direction (see). By forming the depth dof the groove portionto be greater than or equal to the thickness tof the passive element, the passive elementmay be entirely disposed within the groove portion, and the overall thickness of the semiconductor package may not increase due to the passive element. When a conductive memberis present on a lower surface of the passive element, the depth dof the groove portionmay be greater than the sum of the thickness tof the passive elementand a thickness of the conductive member. In some embodiments, the depth dof the groove portionmay be less than the thickness tof the passive elementand a portion of the passive element(for example, an upper end) may protrude above the encapsulantin the vertical direction.

130 130 As a material for the encapsulant, an insulating material such as polyimide, epoxy, or epoxy molding compound (EMC) may be used. In some embodiments, the encapsulantmay further include a filler such as silica or alumina dispersed in the insulating material.

140 130 130 g g. The passive elementmay be inserted into the groove portionso that at least a portion thereof is positioned within the groove portion

140 The passive elementmay be a multi-layer ceramic capacitor (MLCC), but may also be another type of capacitor, such as a tantalum capacitor, or another type of passive element, such as an inductor or a resistor.

140 140 140 The passive elementmay include a bodyB and an external electrodeE.

140 140 140 The bodyB may be a dielectric body formed by stacking dielectric sheets, such as ceramic green sheets. Internal electrodes connected to external electrodesE may be printed on an inside of the bodyB.

140 140 140 120 2 120 150 110 122 140 110 140 The external electrodeE may include a first external electrode and a second external electrode disposed at both ends of the bodyB along the first direction (e.g., the Y direction). Each external electrodeE may be electrically connected to the second connection padPof the semiconductor chipthrough a corresponding conductive pillarand may also be electrically connected to the substratethrough the third conductive wireC. One of the external electrodesE may be electrically connected to a power wiring of the substrate, and the other external electrodeE may be electrically connected to a ground wiring of the substrate.

140 140 The external electrodeE may include a conductive material such as tin (Sn), copper (Cu), aluminum (Al), nickel (Ni), gold (Au), silver (Ag), palladium (Pd), titanium (Ti), or an alloy thereof. In some embodiments, the external electrodeE may include a plurality of layers.

140 150 141 141 141 140 140 150 140 4 FIG. The passive elementmay be connected to the conductive pillarthrough the conductive member(the conductive memberis omitted in). The conductive membermay fill at least a portion of the space between the external electrodeE of the passive elementand the conductive pillar, and may extend over the external side surface of the external electrodeE along the first direction and the second direction.

141 140 140 150 The conductive membermay be formed, for example, of solder paste, and may be formed by applying solder paste to the external electrodeE, placing the passive elementon the conductive pillar, and then melting and cooling the solder paste through a solder reflow process.

141 140 141 140 The conductive membermay have a visible boundary with the external electrodeE. In some embodiments, the conductive membermay be integrated with the external electrodeE and may not have a visible boundary.

150 130 120 140 150 130 120 2 120 150 130 140 140 g The conductive pillarmay be at least partially embedded in the encapsulantto electrically connect one of the semiconductor chipsto the passive element. For example, one end (e.g., the lower end in the vertical direction) of the conductive pillarmay be embedded in the encapsulantand connected to the second connection padPof the semiconductor chip, and the other end (e.g., the upper end in the vertical direction) of the conductive pillarmay be exposed to the groove portionand connected to the external electrodeE of the passive element.

150 120 140 120 140 140 120 The conductive pillarmay extend in the vertical direction from the semiconductor chiptoward the passive elementand overlap the semiconductor chipand the passive elementin the vertical direction, thus connecting the passive elementand the semiconductor chipby a shortest path.

150 130 130 130 130 150 130 150 140 130 130 150 150 140 130 150 140 130 130 g g g g g g g The conductive pillarmay be embedded in the encapsulantand then exposed through the groove portionwhen the groove portionis formed. When forming the groove portion, a portion of the conductive pillarmay be removed together with the encapsulant. The end of the conductive pillarconnected to the passive elementmay be positioned at the same level in the vertical direction as the bottom surface bs of the groove portion. Alternatively, when forming the groove portion, the conductive pillarmay remain without being removed, and the end of the conductive pillarconnected to the passive elementmay be positioned at a level higher in the vertical direction than the bottom surface bs of the groove portion. In some embodiments, the end of the conductive pillarconnected to the passive elementmay be positioned at a level lower in the vertical direction than the bottom surface bs of the groove portionand exposed above the encapsulant.

150 3 4 120 2 3 150 4 120 2 122 120 2 2 FIG. The conductive pillarmay have a cross-sectional width win the second direction (e.g., the X direction) which may be less than or equal to a cross-sectional width win the second direction (e.g., the X direction) of the second connection padP(see). By forming the cross-sectional width wof the conductive pillarto be less than or equal to the cross-sectional width wof the second connection padP, a space for disposing the third conductive wireC on the second connection padPmay be provided.

150 The material of the conductive pillarmay be a conductive material such as copper (Cu), aluminum (Al), nickel (Ni), gold (Au), silver (Ag), palladium (Pd), titanium (Ti), or an alloy thereof.

160 110 110 The semiconductor chipmay be disposed on the substrateand electrically connected to the substrate.

160 110 161 110 162 The semiconductor chipmay be attached to the substratethrough an adhesive memberand connected to the substratethrough a conductive wire.

160 160 160 160 110 162 160 The semiconductor chipmay also include connection padsP. The semiconductor chipmay be disposed so that the surface opposite to the surface on which the connection padP is disposed (in the vertical direction) faces the substrate, and the conductive wiremay be connected to the connection padP.

160 The semiconductor chipmay include, for example, a controller chip.

In the semiconductor package industry, a multi-layer ceramic capacitor (MLCC) may be mounted side by side with a semiconductor chip on a substrate to improve signal quality, and the MLCC may be connected to the semiconductor chip through the substrate. When mounting the MLCC on a substrate, space for mounting the MLCC is needed and it may be difficult to utilize the MLCC mounting space as a wiring space.

140 130 130 110 140 110 140 120 150 g According to some embodiments, since the passive elementis disposed within the groove portionof the encapsulant, no space on the substrateis needed for mounting the passive element, so that the signal quality of the semiconductor package may be improved without increasing the size. In addition, the entire region of the substratemay be utilized as a wiring space, thereby increasing the freedom of wiring design. In addition, it may be possible to provide a semiconductor package having low inductance by connecting the passive elementand the semiconductor chipwith a short electrical path through the conductive pillar.

6 FIG. 100 140 140 130 120 150 140 120 120 140 130 130 g g g. Referring to, in a semiconductor packageB, a plurality of passive elementsmay be connected to each chip stacking structure CS. Each passive elementmay be disposed within the groove portionand connected to the semiconductor chipthrough the conductive pillar. The passive elementsmay be individually connected to different semiconductor chipsor may be connected together to the same semiconductor chip. In some embodiments, the passive elementsmay be disposed within different groove portionsto prevent electrical shorting between them or may be spaced apart from each other along the second direction (e.g., the X direction) within the same groove portion

100 6 FIG. The description of the semiconductor packageA may be equally applied to the description of the configuration shown in.

7 FIG. 100 120 120 110 110 122 122 140 130 150 g Referring to, a semiconductor packageC may include a single semiconductor chip. The semiconductor chipmay be disposed on the substrateand electrically connected to the substratethrough the conductive wiresB andC, and may also be electrically connected to the passive elementdisposed within the groove portionthrough the conductive pillar.

100 7 FIG. The description of the semiconductor packageA may be equally applied to the description of the configuration shown in.

8 12 FIGS.to 1 FIG. are manufacturing process diagrams of the semiconductor package shown in.

8 FIG. 120 160 110 120 160 110 122 Referring to, the chip stacking structures CS and semiconductor chipsandmay be disposed on the substrate. The semiconductor chipsandmay be connected to the substrateusing the conductive wires.

120 160 110 121 161 120 121 The chip stacking structure CS and the semiconductor chips,may be affixed to the substratethrough the adhesive membersand. Additionally, the semiconductor chipsof the chip stacking structure CS may be attached to each other through the adhesive member.

120 110 120 120 110 110 The chip stacking structure CS may be formed by sequentially stacking the semiconductor chipson the substratein the vertical direction, may be formed by stacking modules in which the plurality of semiconductor chips(e.g., four semiconductor chips) are stacked on the substrate, or may be formed separately and disposed on the substrate.

9 FIG. 150 120 120 120 150 120 Referring to, the conductive pillarconnected to the connection padP may be formed on the connection padP of the semiconductor chip. The conductive pillarmay be formed to extend in the vertical direction from the semiconductor chip.

10 FIG. 120 160 122 150 130 130 150 130 130 Referring to, the chip stacking structures CS, the semiconductor chips,, the conductive wires, and the conductive pillarsmay be sealed with the encapsulant. After the encapsulantis formed, the upper end of the conductive pillarin the vertical direction may be covered with the encapsulant. The encapsulantmay be formed by compression molding, transfer molding, or similar deposition methods.

11 FIG. 130 130 150 130 130 130 110 130 130 130 150 130 g g g g Referring to, the groove portionmay be formed in the encapsulantto expose the conductive pillar. The groove portionmay be formed, for example, by removing a portion of the encapsulantin the vertical direction from the upper surface of the encapsulanttoward the substrate. When forming the groove portion, the encapsulantmay be processed using a mechanical drill, laser, or similar cutting methods. When forming the groove portion, a portion of the conductive pillarmay be removed together with the encapsulantor may remain without being removed.

12 FIG. 140 130 150 g Referring to, the passive elementmay be disposed within the groove portionand connected to the conductive pillar.

130 140 130 150 130 g g g. Depending on the size of the groove portion, the passive elementmay be inserted into the groove portionso as to be aligned with the conductive pillar, or may be fitted snugly into the groove portion

140 150 141 141 140 140 150 The passive elementmay be connected to the conductive pillarby the conductive member. The conductive membermay be formed, for example, of solder paste, and may be formed by applying solder paste to the external electrodeE, placing the passive elementon the conductive pillar, and then melting and cooling the solder paste through a solder reflow process.

While the embodiments of the present disclosure have been described in detail, it is to be understood that the disclosure is not limited to the disclosed embodiments, but is intended to cover various modifications and equivalent arrangements included within the scope of the appended claims.

In addition, the embodiments of the present disclosure are not independent of each other and may be implemented in combination with each other unless they are specifically contradictory. Accordingly, combinations of embodiments should also be considered as being included in the present disclosure.