Semiconductor Device

The present disclosure relates generally to a semiconductor device, and more particularly to a semiconductor device including a die in a regular polygonal shape.

In the modern society, the IC devices are becoming smaller, more delicate and more diversified. As well known in the art, an IC device is produced from dies that are fabricated by conventional semiconductor manufacturing processes. The process for manufacturing a die starts with a wafer: first, different regions are marked on the wafer; secondly, conventional semiconductor manufacture processes such as deposition, photolithography, etching or planarization are used to form circuit trace(s); then, each region of the wafer is diced to form a die, and the dies are then assembled to form a chip, so as to obtain a complete assembling unit. Finally, the chip is attached onto a board, such as a printed circuit board (PCB) by electrically connecting to the pins of the PCB. By doing so, functions on the chip can be executed accordingly to form numerous electronic devices. In order to achieve the miniaturization demands, a hybrid bonding (also known as “metal/dielectric hybrid bonding”) may be a direct bonding technology used by the advanced semiconductor industry to process the package of the die. However, the current design and the current die saw process of die will easily lead to low yield in the subsequent package process, and need to be further improved to meet the semiconductor industrial requirements.

An object of the present disclosure is to provide a semiconductor device including a die in a regular polygonal shape, or including a multi-die package including a plurality of dies each in a regular polygonal shape, such that, each of the die will obtain the same distance from each side to a center thereof. Accordingly, the pressure is stressed on the semiconductor device of the present disclosure during a dicing process and/or a hybrid bonding process, in a more uniform manner, so as to gain the improved quality to the subsequent package process, and to avoid the low yield issue.

To achieve the aforementioned objects, the present disclosure provides a semiconductor device including a multi-die package, a testkey region, and a scribe line. The multi-die package includes a plurality of dies each in a regular polygonal shape, each of the plurality of dies includes a plurality of sides, and a number of the plurality of sides is a multiplier of four and is greater than four. The testkey region is disposed between the plurality of dies within the multi-die package, adjacent to at least one of the plurality sides of each of the plurality of dies. The testkey region is in an equilateral polygonal shape. The scribe line surrounds a periphery of each of the plurality of dies and a periphery of the testkey region.

To achieve the aforementioned objects, the present disclosure provides a semiconductor device including a die and a silicon scribe. The die includes a regular polygonal shape, wherein the die includes a plurality of sides, and a number of the plurality of sides is a multiplier of four and is greater than four. The silicon scribe line surrounds a periphery of the die.

These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.

To provide a better understanding of the presented disclosure, preferred embodiments will be described in detail. The preferred embodiments of the present disclosure are illustrated in the accompanying drawings with numbered elements. In addition, the technical features in different embodiments described in the following may be replaced, recombined, or mixed with one another to constitute another embodiment without departing from the spirit of the present disclosure.

1 FIG. 2 FIG. 1 FIG. 2 FIG. 1 FIG. 1 FIG. 10 10 10 10 110 130 140 110 120 10 110 110 120 Please refer toto, which are schematic diagrams of a semiconductor deviceaccording to a first embodiment of the present disclosure, whereinillustrates a schematic top view of the semiconductor deviceandillustrates a schematic cross-sectional view of the semiconductor device. Firstly, as shown in, the semiconductor deviceincludes a multi-die package, a testkey regionand a scribe line. The multi-die packageincludes a plurality of diessequentially arranged with each other. In one embodiment, the semiconductor devicemay include a plurality of the multi-die packages, with each of the multi-die packagesincludes four diesarranged with each other as shown in, but not limited thereto. In another embodiment, each multi-die package may optionally include the dies in another number or in another arrangement due to practical product requirement.

120 122 122 120 122 130 120 110 122 120 110 120 110 130 120 130 132 132 122 110 120 120 130 122 120 132 120 110 120 130 1 FIG. 1 FIG. Each of the diesfor example includes a regular polygonal shape that has a plurality of sideseach in the same length, and a number of the plurality of sidesis a multiplier of four and is greater than four. Then, each of the dieswill present in a regular octagonal shape having eight sidesin the same length (as shown in), or in a regular dodecagon shape having twelve sides in the length, but not limited thereto. The testkey regionis disposed between the dieswithin the multi-die package, and which is namely a region being together defined by one sideof each of the dieswithin the multi-die package, being adjacent to each diewithin the multi-die package. The testkey regionfor example includes an equilateral polygonal shape which is different from the shape (the regular polygonal shape) of each die. Preferably, the testkey regionalso includes a regular polygonal shape that has a plurality of edgesin the same length, and a number of the plurality of edgesis relative less than a number of the plurality of sides. For example, in the embodiment that the multi-die packageincluding four diesand each dieis in a regular octagon shape (having eight sides in an equal length), and the testkey regionis together defined by one sideof each of the four regular octagon-shaped dies, thereby presenting in a regular quadrilateral shape having four edgesin the same length, as shown in, but not limited thereto. In other words, the number of dieswithin the multi-die packageis defined by the minimum number of the dieswhich is required to define a single testkey region.

140 120 130 140 140 140 1 120 10 122 120 122 10 140 10 120 120 2 FIG. The scribe lineis disposed around a periphery of each of the plurality of diesand a periphery of the testkey region, and preferably only includes a silicon material. That is, there is no metal structure like a plug, a wire, a pad or an alignment mark disposed on the scribe line, as shown in, so as to prevent from uneven surfaces generated on the scribe lineafter undergoing the subsequent die saw process. In one embodiment, the scribe linefor example includes a width W, preferable being about 10 micrometers (μm) to 30 micrometers, but not limited thereto. It is noted that, since each diedisposed within the semiconductor deviceof the present embodiment is in the regular polygonal shape, the distance from each sideto a center (not shown in the drawings) of the diewill be the same with each other, thereby preventing from the uneven stress occurred on the sidesso as to improve the bonding quality of the semiconductor devicein the subsequent process. In addition, since there is no metal structure disposed on the scribe line, the semiconductor devicewill easily obtain an overall uniform surface after undergoing a die saw process performed subsequently. Then, the pressure may be stressed on each diein the subsequent hybrid bonding process in a more uniform manner, during a chip-to-chip bonding or in a chip-to-wafer bonding, so that, each dieis allowable to gain a preferably quality in the subsequent packaging process, and to sufficient improve the low-yield issue.

1 FIG. 2 FIG. 2 FIG. 2 FIG. 10 100 134 136 100 100 120 130 140 100 134 130 120 134 120 120 134 120 100 130 134 100 10 110 134 130 Further in view ofand, the semiconductor devicefurther includes a substrate, and at least one testkey structureand a bonding paddisposed on the substrate. The substratefor example includes a silicon substrate, an epitaxial silicon substrate, a silicon-containing substrate, or a silicon-on-insulator (SOI) substrate, and the aforementioned dies, the testkey regionand the scribe lineare respectively disposed on the substrate. Precisely speaking, the testkey structureis disposed within the testkey region, and which includes a complete layout or at least a partial structure of any required element to be tested within the dies, with the at least one testkey structurebeing corresponding to any active element or passive element like a transistor, a capacitor, a resistor, or even an analog circuit disposed on each die. Then, the structural health of these elements within each dieis allowable to be synchronously simulated by detecting the testkey structure. In one embodiment, each diefor example includes at least one interconnection structure (not shown in) disposed on the substrate, with the at least one interconnection structure for example including a plurality wires and a plurality of plug structures stacked in sequence. The at least one interconnection structure may include a low-resistant metal material like copper (Cu), aluminum (Al), tungsten (W), or titanium (Ti), and preferably including copper, but not limited thereto. On the other hand, the testkey regioncorrespondingly includes the at least one testkey structurealso disposed on the substrate, as shown in, for detecting the structural health of the at least one interconnection structure in the subsequent simulating process. Also, in the embodiment that the semiconductor deviceincluding a plurality of the multi-die packages, the testkey structurescorrespondingly disposed in a plurality of the testkey regionsmay respectively include an active element, a passive element, an alignment mark, a wafer acceptance test pad, or an analog circuit being different from each other.

134 102 100 130 100 100 138 134 136 134 136 102 10 136 140 120 130 102 140 The at least one testkey structureis disposed in a dielectric layeron the substrate, within the testkey region, and which can be coupled to an active element, a passive element, or a circuit (not shown in the drawings) disposed either on the substrateor in the substratethrough an interconnection structuredisposed underneath. The testkey structurealso includes a low-resistant metal material such as copper, aluminum, tungsten, or titanium, and preferably including copper, but not limited thereto. The bonding padis disposed on the at least one testkey structureto electrically connect thereto. It is noted that, a surface of the bonding padis exposed from the dielectric layer, so that, the semiconductor devicecan be further electrically connected to another die or another semiconductor device through the bonding pad, based on practical product requirements. In one embodiment, the formation of the scribe lineis for example accomplished by firstly forming a trench (not shown in the drawings) between each dieand the testkey regionby partially etching the dielectric layer, next filling in the trench with a silicon material like single-crystal silicon, polysilicon, or amorphous silicon by performing a deposition process or an epitaxial growing process, and finally obtaining the scribe lineonly including the silicon material by performing a planarization process to remove the redundant silicon material.

10 120 140 10 120 140 10 140 140 1 140 120 120 10 122 120 122 120 122 10 3 FIG. 4 FIG. Through these arrangements, the semiconductor devicecan be further diced into a plurality of diesas shown inandthrough processing the scribe linein the subsequent die saw process such as a laser dicing process or a plasma dicing process, but not limited thereto. In another embodiment, the semiconductor devicemay also be diced into the diesthrough selectively etching the silicon material of the scribe line, for example by performing an etching process. According to the semiconductor deviceof the present embodiment, since the scribe lineonly includes the silicon material without any metal structures disposed thereon, the width of the scribe linewill be dramatically shrunk, and the possible issues like metal residues, uneven surface, or pealing film will be sufficiently improved. For example, the width Wof the scribe linedisposed around each of the diesmay be about 10 micrometers to 30 micrometers, but not limited thereto. On the other hand, since each diedisposed within the semiconductor deviceof the present embodiment is in the regular polygonal shape, the distance from each sideto the center of the diewill be the same with each other. Then, the pressure will be stressed on each sideof the diein the subsequent hybrid bonding process in a more uniform manner, as being bonded to another die (not shown in the drawing) or another wafer (not shown in the drawing), thereby preventing from the uneven stress easily occurred on each side. Thus, the semiconductor deviceof the present embodiment is allowable to gain a preferably quality in the subsequent packaging process, and to sufficient improve the low-yield issue.

3 FIG. 4 FIG. 3 FIG. 4 FIG. 3 FIG. 20 20 20 20 120 240 120 20 120 10 120 122 122 142 120 Please refer toand, which are schematic diagrams of another semiconductor deviceaccording to the first embodiment of the present disclosure, whereinillustrates a schematic top view of the semiconductor deviceandillustrates a schematic cross-sectional view of the semiconductor device. Firstly, as shown in, the semiconductor deviceincludes a single dieand a scribe line. The structure of the diewithin the semiconductor deviceis substantially the same as that of each diewithin the semiconductor device, and all the similarity will not be redundantly described hereinafter. The dieincludes the regular polygonal shape that has the plurality of sidesin the same length, with the number of the plurality of sidesbeing a multiplier of four and greater than four, preferably for eight, but not limited thereto. Then, the scribe lineis disposed around the periphery of the die.

142 2 142 120 120 234 236 100 234 202 100 134 234 204 100 238 236 234 202 240 120 4 FIG. It is noted that, since there is no metal structure like a plug, a wire, a pad or an alignment mark disposed on the scribe line, a width Wof the scribe linesurrounding outside the periphery of the diewill be dramatically shrunk thereby, for example preferably being about 2.5 micrometers to 12.5 micrometers, but not limited thereto. As shown in, the dieprecisely includes at least one interconnection structureand a conductive paddisposed on the substrate. The at least one interconnection structureis disposed within a dielectric layerdisposed on the substrate, and which includes the same material and the same structure as that of the at least one testkey structure. The at least one interconnection structuremay be further electrically connected to a doped regionin the substratethrough another interconnection structuredisposed underneath. The conductive padis disposed on the at least one interconnection structure, with a surface thereof being exposed from the dielectric layer. Furthermore, a protection structuresuch as a guard ring may be additionally disposed at the periphery of the die.

120 20 20 236 120 120 120 122 120 122 120 Through these arrangements, the subsequent packaging process may be further performed on the dieof the semiconductor device, for example attaching the semiconductor deviceto a circuit board (not shown in the drawings) or other secondary packaging substrates via the bonding paddisposed on the die, to form the required integrated circuits. Alternatively, the diemay also be used directly as a chip scale package (CSP) of the wafer-level package, which is beneficial on thin and short packaging application. In this way, since the dieof the present embodiment is in the regular polygonal shape, the distance from each sideto the center of the diewill be the same with each other, thereby preventing from the uneven stress occurred on the sidesin the subsequent hybrid bonding process, during a chip-to-chip bonding or in a chip-to-wafer bonding. Accordingly, the dieis allowable to gain a preferably quality in the subsequent packaging process, and to sufficient improve the low-yield issue.

People well-skilled in the art should fully understand that the semiconductor device is not limited to be what is shown in the aforementioned embodiments, and which may further include other examples based on practical product requirements. The following description will detail other different embodiments or variant embodiments of the semiconductor device in the present disclosure. To simplify the description, the following description will detail the dissimilarities among the different embodiments and the identical features will not be redundantly described. In order to compare the differences between the embodiments easily, the identical components in each of the following embodiments are marked with identical symbols.

5 FIG. 6 FIG. 5 FIG. 6 FIG. 30 30 30 30 10 320 320 110 310 Please refer toand, which are schematic diagrams of a semiconductor deviceaccording to a second embodiment of the present disclosure, whereinillustrates a schematic top view of the semiconductor deviceandillustrates another schematic top view of the semiconductor device. The structure of the semiconductor devicein the present embodiment is substantially the same as that of the semiconductor devicein the aforementioned embodiment, and all the similarities will not be redundantly described hereinafter. The difference between the present embodiment and the aforementioned embodiment is mainly in the shape of diesand/or the number and the arrangement of the dieswithin the multi-die package,.

5 FIG. 5 FIG. 6 FIG. 110 320 320 322 330 320 110 322 320 310 320 330 322 322 330 310 320 330 322 320 310 322 320 310 320 320 310 320 330 a a. Precisely speaking, as shown in, the multi-die packagefor example includes four diesarranged sequentially, and each of the diesis in a regular dodecagonal shape including twelve sidesin the same length. The testkey regionis disposed between the dieswithin the multi-die package, and includes a region being together defined by at least two sidesof each of the dieswithin the multi-die package, thereby present in an equilateral polygonal shape which is different from the shape of each die, for example being in an equilateral octagonal shape as shown in, but not limited thereto. That is, the testkey regionincludes eight edgeseach in the same length, and the distance from each edgeto a center (not shown in the drawings) of the testkey regionis not the same with each other. However, in another embodiment, the multi-die packagemay optionally include three diesarranged sequentially, and the testkey regionwill be a region being together defined by one sidesof each of the dieswithin the multi-die package, thereby present in an equilateral triangular shape (including three edgesin the same length) which is different from the shape of each dieas shown in, but not limited thereto. That is, in the embodiment that the multi-die packageincluding three dies, the number of dieswithin the multi-die packageis also defined by the minimum number of the dieswhich is required to define a single testkey region

30 340 320 330 330 340 320 320 30 322 320 340 3 342 a, On the other hand, the semiconductor deviceincludes a scribe linedisposed around a periphery of each of the plurality of diesand a periphery of the testkey region/and preferably only includes a silicon material. In other words, there is no metal structure like a plug, a wire, a pad or an alignment mark disposed on the scribe line, so that, each diewill easily obtain the overall even surface after undergoing the subsequent die saw process. Accordingly, since each diedisposed within the semiconductor deviceof the present embodiment is in the regular polygonal shape (namely, the regular dodecagonal shape), the bonding quality in the subsequent hybrid bonding process will be dramatically improved, without leading to the uneven pressure possibly stressed on the sidesof the dies. Also, since there is no metal structure disposed on the scribe line, a width Wof the scribe linewill be dramatically shrunk thereby, for example preferably being about 10 micrometers to 30 micrometers, so as to gain a preferably quality in the subsequent packaging process, and to sufficient improve the low-yield issue.

30 320 340 40 40 320 342 320 322 342 320 342 4 342 320 7 FIG. 7 FIG. Through these arrangements, the semiconductor devicealso can be further diced into a plurality of the diesas shown inthrough processing the subsequent die saw process such as a laser dicing process or a plasma dicing process on the scribe line. As shown in, a schematic top view of another semiconductor deviceaccording to the second embodiment of the present disclosure is illustrated. The semiconductor deviceincludes a single dieand a scribe line. The dieis preferably in a regular dodecagonal shape, and includes twelve sideswith the same length. The scribe lineis disposed around the periphery of the die. It is noted that there is no metal structures like a plug or a wire disposed on the scribe line, so that, a width Wof the scribe linesurrounding outside the periphery of the diewill be dramatically shrunk thereby, for example preferably being about 2.5 micrometers to 12.5 micrometers, but not limited thereto.

320 40 320 30 320 40 40 320 The structure of the diewithin the semiconductor deviceis substantially the same as that of each diewithin the semiconductor device, and all the similarity will not be redundantly described hereinafter. Then, the subsequent packaging process may be further performed on the dieof the semiconductor device, for example attaching the semiconductor deviceto a circuit board (not shown in the drawings) or other secondary packaging substrates via a bonding pad (not shown in the drawings) disposed on the die, to form the required integrated circuits.

According to the semiconductor device in the present disclose, since a scribe line disposed within the semiconductor device only includes the silicon material without including any metal structures disposed thereon, the possible issues like metal residues, uneven surface, or pealing films will be sufficiently improved, the width of the scribe line will be dramatically shrunk, and the subsequent die saw process will be simplified thereby. Also, since a die or a plurality of dies of a multi-die package disposed within the semiconductor device is in the regular polygonal shape, the distance from each side to the center of the die will be the same with each other. Then, the pressure stressed on each die in the subsequent die saw process and/or the subsequent hybrid bonding process will be carried out in a more uniform manner, so that, the die is allowable to gain a preferably quality in the subsequent packaging process, and to sufficient improve the low-yield issue.

Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.