Display Device

The present application claims priority to Korean Patent Application No. 10-2024-0177401, filed in the Republic of Korea on Dec. 3, 2024, the entire contents of which are hereby expressly incorporated by reference into the present application.

The present disclosure relates to a display device and, more particularly, to a display device including a light-emitting element.

As the information society progresses, a demand for different types of display devices increases, and flat panel display devices (FPD), such as liquid crystal display devices and light-emitting diode display devices, have been developed and applied to various fields.

Among the flat panel display devices, light-emitting diode display devices emit light due to the radiative recombination of an exciton. The exciton is formed from an electron and a hole by injecting charges into a light-emitting layer between a cathode for injecting electrons and an anode for injecting holes in a light-emitting diode.

The light-emitting diode display device can offer various advantages and improved properties. For instance, compared to the liquid crystal display device, because it is self-luminous, the light-emitting diode display device has a wide viewing angle, and since a backlight unit is not required, the light-emitting diode display device has an ultra-thin thickness and light weight. In addition, the light-emitting diode display device is also advantageous in power consumption.

The light-emitting diode display device may include inorganic-based light-emitting elements and organic-based light-emitting elements. The inorganic-based light-emitting elements have relatively excellent stability, fast response characteristics, and high contrast ratios, and micro light-emitting diodes (micro LEDs or μLED) are widely used as the inorganic-based light-emitting elements for high resolution.

However, the inorganic-based light-emitting element may have a lower threshold voltage than the organic-based light-emitting element, so there is a potential problem in that light emission may occur in a black state, thereby resulting in a decrease in image quality.

Accordingly, embodiments of the present disclosure are directed to a display device that substantially obviate one or more of the problems due to limitations and disadvantages of the related art.

An aspect of the present disclosure is to provide a display device capable of improving image quality.

Additional features and aspects will be set forth in the description that follows, and in part will be apparent from the description, or can be learned by practice of the inventive concepts provided herein. Other features and aspects of the inventive concepts can be realized and attained by the structure particularly pointed out in the written description, or derivable therefrom, and the claims hereof as well as the appended drawings.

To achieve these and other aspects of the inventive concepts, as embodied and broadly described herein, a display device includes a substrate, a first transistor over the substrate and connected to a first power line, a second transistor over the substrate and connected to a second power line, a light-emitting element connected to the first transistor and the second transistor, and a connection element connected to the first power line and the light-emitting element, wherein the connection element overlaps at least a part of the first transistor.

It is to be understood that both the foregoing general description and the following detailed description are by way of example and explanatory and are intended to provide further explanation of the inventive concepts as claimed.

Advantages and features of the present disclosure and methods for achieving them will be made clear from example embodiments described below in detail with reference to the accompanying drawings. The present disclosure can, however, be implemented in many different forms and should not be construed as being limited to the example embodiments set forth herein, and the example embodiments are provided such that this disclosure will be more thorough and complete and will more fully convey the scope of the present disclosure to those skilled in the art to which the present disclosure pertains.

The shapes, sizes, dimensions (e.g., length, width, height, thickness, radius, diameter, area, etc.), ratios, angles, number of elements, and the like illustrated in the accompanying drawings for describing the example embodiments of the present disclosure are merely examples, and the present disclosure is not limited thereto.

A dimension including size and a thickness of each component illustrated in the drawing are illustrated for convenience of description, and the present disclosure is not limited to the size and the thickness of the component illustrated, but it is to be noted that the relative dimensions including the relative size, location, and thickness of the components illustrated in various drawings submitted herewith are part of the present disclosure.

The same reference numerals refer to the same components throughout this disclosure, unless otherwise specified.

Further, in the following description of example embodiments of the present disclosure, where a detailed description of a known related art may unnecessarily obscure a feature or aspect of the present disclosure, the detailed description of such known related art may be omitted herein or may be briefly discussed.

Where terms such as “including,” “having,” “comprising,” and the like are used in this disclosure, other parts can be added unless a more specific term like “only” is used herein.

Further, where a component is expressed as being singular, being plural is included unless otherwise specified.

In analyzing a component, an error range is to be interpreted as being included even where there is no explicit description.

In describing a positional relationship, for example, where a positional relationship of two parts/layers is described as being “over,” “on,” “above,” “below,” “under,” “next to,” or the like, one or more other parts/layers can be provided between the two parts/layers, unless a more specific term like “immediately” or “directly” is used therewith.

In describing a temporal relationship, for example, where a temporal predecessor relationship is described as being “after,” “subsequent,” “next to,” “prior to,” or the like, unless a more specific term like “immediately” or “directly” is used, cases that are not continuous or sequential can also be included.

As used herein, the terms “connected” and “coupled” are intended to have the broadest possible meaning. Specifically, the phrase “A is connected to B” encompasses both a direct connection—where no intervening components or elements are present—and an indirect connection, where one or more intermediate components or elements exist between A and B. In other words, “A is connected to B” includes both direct physical or electrical coupling and indirect coupling through one or more intervening components. Unless explicitly stated otherwise, these terms do not require direct physical or electrical contact. The terms “coupled” and “in contact” should be interpreted in the same manner. For example, the term “in contact with,” as used herein, encompasses both “indirect contact” and “direct contact.” Accordingly, where the phrase “A is in contact with B” is used, it implies that other components may be present between A and B, unless explicitly specified as, for example, “A is in direct contact with B.”

Although the terms first, second, and the like may be used to describe various components, these components are not substantially limited by these terms. These terms are used only to refer to one component separately from another component, and not to define any order or sequence. Therefore, a first component described below can substantially be a second component, and vice versa, within the technical spirit of the present disclosure.

Features of various embodiments of the present disclosure can be partially or entirely united or combined with each other, technically various interlocking and driving are possible, and each of the embodiments can be independently implemented with respect to each other or implemented together in an associated relationship.

Hereinafter, example embodiments of the present disclosure will be described in detail with reference to accompanying drawings.

1 FIG. is a schematic plan view of a display device according to one or more example embodiments of the present disclosure and shows one pixel.

1 FIG. 1 2 As shown in, in the display device according to one or more example embodiments of the present disclosure, a gate line GL and an emission line EL may extend in a first direction X. A data line DL, a first power line PL, a second power line PL, and a reference line RL may extend in a second direction Y and may cross the gate line GL and the emission line EL, thereby defining a plurality of sub-pixels SP. A light-emitting element, a plurality of transistors, and a storage capacitor may be provided in each sub-pixel SP, and this will be described in detail later.

1 2 The gate line GL may transmit a gate signal SCAN, and the emission line EL may transmit an emission signal EM. The data line DL may transmit a data voltage Vdata, and the reference line RL may transmit a reference voltage Vref. In addition, the first power line PLmay be a high potential power line transmitting a high potential voltage VDD, and the second power line PLmay be a low potential power line transmitting a low potential voltage VSS.

Each sub-pixel SP may be disposed between the gate line GL and the emission line EL in the second direction Y. For example, the gate line GL may be disposed at a lower portion of each sub-pixel SP, and the emission line EL may be disposed at an upper portion of each sub-pixel SP. However, embodiments of the present disclosure are not limited thereto, and the arrangement of the gate line GL and the emission line EL may vary.

1 2 1 1 2 2 1 2 One reference line RL may be disposed between two first power lines PLin the first direction X, and the second power line PLmay be disposed between the first power line PLand the reference line RL. One data line DL may be disposed between the first power line PLand the second power line PLand between the second power line PLand the reference line RL. That is, one of the first power line PL, the second power line PL, and the reference line RL may be disposed between adjacent two data lines DL.

2 1 2 Here, a distance between the data line DL and the second power line PLmay be greater than a distance between the data line DL and the first power line PLor a distance between the data line DL and the reference line RL. Each sub-pixel SP may be disposed between the data line DL and the second power line PL.

1 2 3 4 1 1 2 2 2 3 2 4 2 1 The data line DL may include first, second, third, and fourth data lines DL, DL, DL, and DL. The first data line DLmay be disposed between the first power line PLand the second power line PL. The second data line DLmay be disposed between the second power line PLand the reference line RL. The third data line DLmay be disposed between the reference line RL and one other second power line PL. The fourth data line DLmay be disposed between the other second power line PLand another first power line PL.

In addition, an auxiliary power line PLa and an auxiliary reference line RLa may extend in the first direction X. The gate line GL and the emission line EL may be disposed between the auxiliary power line PLa and the auxiliary reference line RLa. In this case, the auxiliary power line PLa may be disposed adjacent to the emission line EL, and the auxiliary reference line RLa may be disposed adjacent to the gate line GL. However, embodiments of the present disclosure are not limited thereto, and the arrangement of the auxiliary power line PLa and the auxiliary reference line RLa may vary.

1 2 3 4 1 2 1 The auxiliary power line PLa may cross and overlap the first, second, third, and fourth data lines DL, DL, DL, and DL, the first power line PL, the second power line PL, and the reference line RL and may be connected to the first power line PLto supply the high potential voltage VDD to each sub-pixel SP.

2 3 2 1 4 1 The auxiliary reference line RLa may cross and overlap the second and third data lines DLand DL, the second power line PL, and the reference line RL and may be connected to the reference line RL to supply the reference voltage Vref to each sub-pixel SP. The auxiliary reference line RLa may be spaced apart from the first and fourth data lines DLand DLand the first power line PL.

Each sub-pixel SP may have a substantially rectangular shape. However, embodiments of the present disclosure are not limited thereto, and the shape of each sub-pixel SP may vary.

1 2 3 4 1 2 3 4 1 2 3 4 The plurality of sub-pixels SP may constitute one pixel. For example, one pixel may include first, second, third, and fourth sub-pixels SP, SP, SP, and SP. The first, second, third, and fourth sub-pixels SP, SP, SP, and SPmay be sequentially arranged in the first direction X. Here, the first sub-pixel SPand the second sub-pixel SPmay be red sub-pixels, the third sub-pixel SPmay be a green sub-pixel, and the fourth sub-pixel SPmay be a blue sub-pixel. However, embodiments of the present disclosure are not limited thereto, and the number and arrangement of the sub-pixels SP included in one pixel may vary.

1 2 3 4 1 2 2 3 4 2 Two sub-pixels SP adjacent to each other in the first direction X may be symmetrical. For example, the first sub-pixel SPand the second sub-pixel SPmay be symmetrical with the third and fourth sub-pixels SPand SPwith respect to the reference line RL. The first sub-pixel SPmay be symmetrical with the second sub-pixel SPwith respect to the second power line PL, and the third sub-pixel SPmay be symmetrical with the fourth sub-pixel SPwith respect to another second power line PL.

The configuration of the sub-pixel of the display device according to example embodiments of the present disclosure will be described in detail with reference to accompanying drawings.

2 FIG. 1 FIG. is an equivalent circuit diagram for a sub-pixel of a display device according to a first example embodiment of the present disclosure and will be described with reference totogether.

2 FIG. In, one sub-pixel SP of the display device according to the first example embodiment of the present disclosure may include a switching transistor ST, a driving transistor DT, a sensing transistor NT, a storage capacitor Cst, and a light-emitting diode LD. The sub-pixel SP may have substantially a 3T1C structure including three transistors and one storage capacitor as a basic configuration, but embodiments of the present disclosure are not limited thereto. The number of the transistors and capacitor may vary. In addition, the sub-pixel SP may further include an emission transistor ET and a connection transistor CT.

For example, the switching transistor ST, the driving transistor DT, the sensing transistor NT, the emission transistor ET, and the connection transistor CT may be n-type transistors. However, embodiments of the present disclosure are not limited thereto. In other embodiments, the switching transistor ST, the driving transistor DT, the sensing transistor NT, the emission transistor ET, and the connection transistor CT may be p-type transistors.

1 1 The switching transistor ST may be switched according to the gate signal SCAN and may transmit the data voltage Vdata to a first node N. Specifically, a gate of the switching transistor ST may be connected to the gate line GL and may be supplied with the gate signal SCAN. A source of the switching transistor ST may be connected to the data line DL and may be supplied with the data voltage Vdata. A drain of the switching transistor ST may be connected to the first node N.

1 2 1 1 2 The driving transistor DT may be switched according to a voltage of the first node Nand may transmit the high potential voltage VDD to a second node N. Specifically, a gate of the driving transistor DT may be connected to the first node N. A drain of the driving transistor DT may be connected to the first power line PLand may be supplied with the high potential voltage VDD. A source of the driving transistor DT may be connected to the second node N.

2 2 2 2 The sensing transistor NT may be switched according to the gate signal SCAN and may transmit the reference voltage Vref to the second node Nor transmit a voltage of the second node Nto the reference line RL. Specifically, a gate of the sensing transistor NT may be connected to the gate line GL and may be supplied with the gate signal SCAN. A source of the sensing transistor NT may be connected to the reference line RL and may be supplied with the reference voltage Vref or transmit the voltage of the second node Nto the reference line RL. A drain of the sensing transistor NT may be connected to the second node N.

1 1 2 The storage capacitor Cst may maintain the data voltage Vdata supplied to the first node Nfor a frame and may store a threshold voltage Vth of the driving transistor DT. First and second capacitor electrodes of the storage capacitor Cst may be connected to the first node Nand the second node N, respectively.

2 3 The light-emitting diode LD may emit light with luminance proportional to a current of the driving transistor DT. Specifically, an anode of the light-emitting diode LD may be connected to the second node N, and a cathode of the light-emitting diode LD may be connected to a third node N.

3 2 3 In addition, the emission transistor ET may be switched according to the emission signal EM and may transmit the low potential voltage VSS to the third node N. Specifically, a gate of the emission transistor ET may be connected to the emission line EL and may be supplied with the emission signal EM. A source of the emission transistor ET may be connected to the second power line PLand may be supplied with the low potential voltage VSS. A drain of the emission transistor ET may be connected to the third node N.

3 1 3 1 3 The connection transistor CT may be a connection element for connecting the third node Nand the first power line PLand may be a diode-type transistor in which a gate and a drain are connected. The connection transistor CT may be switched according to the high potential voltage VDD and may transmit the high potential voltage VDD to the third node N. Specifically, the gate and the drain of the connection transistor CT may be connected to the first power line PLand may be supplied with the high potential voltage VDD. A source of the connection transistor CT may be connected to the third node N.

1 2 3 The gate of the driving transistor DT, the drain of the switching transistor ST, and the first capacitor electrode of the storage capacitor Cst may constitute the first node N. The source of the driving transistor DT, the drain of the sensing transistor NT, the second capacitor electrode of the storage capacitor Cst, and the anode of the light-emitting diode LD may constitute the second node N. The cathode of the light-emitting element LD, the drain of the emission transistor ET, and the source of the connection transistor CT may constitute the third node N.

3 As such, in the display device according to the first example embodiment of the present disclosure, by providing the connection transistor CT as the connection element and forming a voltage path, the cathode voltage of the light-emitting diode LD, i.e., the voltage of the third node Ncan be controlled. Accordingly, the light-emitting diode LD can be prevented or suppressed from emitting light in a black state.

3 FIG. A driving operation of the display device according to the first example embodiment of the present disclosure will be described with reference to.

3 FIG. 2 FIG. is a timing diagram of a plurality of signals and a plurality of node voltages used to drive the display device according to the first example embodiment of the present disclosure and will be described with reference totogether.

3 FIG. 1 2 3 4 As shown in, in the display device according to the first example embodiment of the present disclosure, one frame may include first, second, third, and fourth sections TP, TP, TP, and TP.

1 1 The first section TPmay be a writing section. In the first section TP, the gate signal SCAN may have a high level, and the emission signal EM may have a low level.

Accordingly, the switching transistor ST and the sensing transistor NT may be turned on, and the emission transistor ET may be turned off, so that the data voltage Vdata and the reference voltage Vref may be stored in the storage capacitor Cst.

1 2 3 Here, the first node Nmay be charged with the data voltage Vdata, the second node Nmay be charged with the reference voltage Vref, and the third node Nmay be charged with the high potential voltage VDD.

2 2 3 3 In this case, a voltage Vnof the second node Nmay be lower than a voltage Vnof the third node N, and a reverse bias voltage may be applied to the light-emitting diode LD. Therefore, no current Ioff may flow through the light-emitting diode LD, and the light-emitting diode LD may not emit light.

2 2 Next, the second section TPmay be a stabilizing section. In the second section TP, the gate signal SCAN and the emission signal EM may have low levels.

1 2 2 2 2 Accordingly, the switching transistor ST, the sensing transistor NT, and the emission transistor ET may be turned off, so that the first node Nand the second node Nmay be floating. Electric charges may be accumulated in the second node Nby a current flowing through the driving transistor DT, and thus the voltage Vnof the second node Nmay increase.

2 2 3 3 In this case, the increased voltage Vnof the second node Nmay be lower than the voltage Vnof the third node Ncharged with the high potential voltage VDD, and a reverse bias voltage may be applied to the light-emitting diode LD. Therefore, no current Ioff may flow through the light-emitting diode LD, and the light-emitting diode LD may not emit light.

3 3 Next, the third section TPmay be an emission section. In the third section TP, the gate signal SCAN may have a low level, and the emission signal EM may have a high level.

3 Accordingly, the switching transistor ST and the sensing transistor NT may be turned off, and the emission transistor ET may be turned on, so that the third node Nmay be charged with the low potential voltage VSS.

3 3 2 2 In this case, the voltage Vnof the third node Ncharged with the low potential voltage VSS may be lower than the voltage Vnof the second node N, and a forward bias voltage may be applied to the light-emitting diode LD. Therefore, a current Ion may flow through the light-emitting diode LD, and the light-emitting diode LD may emit light.

4 4 Next, the fourth section TPmay be a non-emission section. In the fourth section TP, the gate signal SCAN and the emission signal EM may have the low levels.

1 2 2 2 2 2 2 Accordingly, the switching transistor ST, the sensing transistor NT, and the emission transistor ET may be turned off, so that the first node Nand the second node Nmay be floating. Electric charges may be accumulated in the second node Nby the current flowing through the driving transistor DT, and thus the voltage Vnof the second node Nmay increase. The increase in the voltage Vnof the second node Nmay continue until the driving transistor DT is turned off.

3 2 2 3 3 In this case, the third node Nmay be charged with the high potential voltage VDD. The increased voltage Vnof the second node Nmay be lower than or equal to the voltage Vnof the third node N. Accordingly, a reverse bias voltage or no bias voltage may be applied to the light-emitting diode LD, so that no current Ioff may flow through the light-emitting diode LD and the light-emitting diode LD may not emit light.

3 3 2 2 1 2 4 3 As such, in the display device according to the first example embodiment of the present disclosure, by making the voltage Vnof the third node N, which is the voltage of the cathode of the light-emitting diode LD, higher than or equal to the voltage Vnof the second node N, the light-emitting diode LD may be prevented or suppressed from emitting light in the first, second, and fourth sections TP, TP, and TPexcept for the third section TP, which is the emission section. Accordingly, by preventing or suppressing light emission in the black state, a contrast ratio of the display device may be increased, and image quality of the display device may be improved.

4 FIG. A planar configuration of the display device according to the first example embodiment of the present disclosure will be described with reference to.

4 FIG. 1 FIG. 1 is a schematic plan view of a display device according to the first example embodiment of the present disclosure and shows one sub-pixel, which corresponds to the area Aof.

4 FIG. 1 2 In, the gate line GL and the emission line EL of the first direction X may cross the first power line PL, the second power line PL, and the data line DL of the second direction Y to define the sub-pixel SP. The switching transistor ST, the driving transistor DT, the sensing transistor NT, the emission transistor ET, the connection transistor CT, the storage capacitor Cst, and the light-emitting diode LD may be provided in the sub-pixel SP.

In the first direction X, the driving transistor DT and the emission transistor ET may be disposed adjacent to each other, and the switching transistor ST and the sensing transistor NT may be disposed adjacent to each other.

In the second direction Y, the storage capacitor Cst may be disposed between the driving and emission transistors DT and ET and the switching and sensing transistors ST and NT, and the connection transistor CT may be disposed between the driving and emission transistors DT and ET and the emission line EL.

Meanwhile, the light-emitting diode LD may be disposed to overlap the driving transistor DT.

5 FIG. A cross-sectional configuration of the display device according to the first example embodiment of the present disclosure will be described in detail with reference to.

5 FIG. is a schematic cross-sectional view of a display device according to the first example embodiment of the present disclosure and shows one sub-pixel.

5 FIG. 121 122 123 124 125 140 110 140 121 122 121 125 123 124 122 124 In, the display device according to the first example embodiment of the present disclosure may include first, second, third, and fourth transistors,,, and, a capacitor, and a light-emitting elementon a substrate. The light-emitting elementmay be electrically connected to the first transistorand the second transistor. The first transistormay be electrically connected to the capacitorand the third transistorand electrically connected to the fourth transistor. The second transistormay be electrically connected to the fourth transistor.

111 110 110 Specifically, a buffer layermay be provided on the substrate. The substratemay be a glass substrate or a plastic substrate. For example, polyimide can be used for the plastic substrate, but embodiments of the present disclosure are not limited thereto.

111 110 111 111 x x The buffer layermay be disposed substantially all over the substrate. The buffer layermay be formed as a single layer or multiple layers of an inorganic insulating material. For example, the inorganic insulating material of the buffer layermay include silicon nitride (SiN), silicon oxide (SiO), or silicon oxynitride (SiON).

110 111 121 Meanwhile, although not shown in the figure, a light-shielding layer may be provided between the substrateand the buffer layer. The light-shielding layer may overlap the first transistor.

121 122 123 124 111 121 122 123 124 121 122 123 124 121 122 123 124 121 122 123 124 a a a a a a a a a a a a a a a a a a a a First, second, third, and fourth active layers,,, andmay be provided on the buffer layer. Each of the first, second, third, and fourth active layers,,, andmay include a channel region at its central part and source and drain regions at both sides of the channel region. The first, second, third, and fourth active layers,,, andmay be formed of an oxide semiconductor material. Alternatively, the first, second, third, and fourth active layers,,, andmay be formed of polycrystalline silicon, and in this case, both ends of each of the first, second, third, and fourth active layers,,, andmay be doped with impurities.

112 121 122 123 124 111 112 110 112 112 a a a a x x A gate insulation layermay be provided on the first, second, third, and fourth active layers,,, andand the buffer layer. The gate insulation layermay be disposed substantially all over the substrate. The gate insulation layermay be formed as a single layer or multiple layers of an inorganic insulating material. For example, the inorganic insulating material of the gate insulation layermay include silicon nitride (SiN), silicon oxide (SiO), or silicon oxynitride (SiON).

121 122 123 124 125 112 121 122 123 124 121 122 123 124 121 122 123 124 121 122 123 124 g g g g a g g g, g a a a a g g g, g a a a a First, second, third, and fourth gate electrodes,,, andand a first capacitor electrodemay be formed on the gate insulation layer. The first, second, third, and fourth gate electrodes,,andmay overlap the first, second, third, and fourth active layers,,, and, respectively. The first, second, third, and fourth gate electrodes,,andmay be disposed to correspond to the central parts of the first, second, third, and fourth active layers,,, and, respectively.

121 122 123 124 125 121 122 123 124 125 121 122 123 124 125 g g g, g a g g g, g a g g g, g a The first, second, third, and fourth gate electrodes,,andand the first capacitor electrodemay be formed of a conductive material such as metal. For example, the first, second, third, and fourth gate electrodes,,andand the first capacitor electrodemay be formed of one or more of: aluminum (Al), copper (Cu), molybdenum (Mo), titanium (Ti), chromium (Cr), nickel (Ni), tungsten (W), and an alloy thereof. The first, second, third, and fourth gate electrodes,,andand the first capacitor electrodemay have a single-layered structure or a multiple-layered structure.

113 121 122 123 124 125 113 110 113 113 g g g, g a x x An interlayer insulation layermay be provided on the first, second, third, and fourth gate electrodes,,andand the first capacitor electrode. The interlayer insulation layermay be disposed substantially all over the substrate. The interlayer insulation layermay be formed as a single layer or multiple layers of an inorganic insulating material. For example, the inorganic insulating material of the interlayer insulation layermay include silicon nitride (SiN), silicon oxide (SiO), or silicon oxynitride (SiON).

121 122 123 124 121 122 123 124 125 127 128 129 113 s s s s d d d d b First, second, third, and fourth source electrodes,,, and, first, second, third, and fourth drain electrodes,,, and, a second capacitor electrode, a first line, a second line, and a third linemay be provided on the interlayer insulation layer.

121 122 123 124 121 122 123 124 125 127 128 129 121 122 123 124 121 122 123 124 125 127 128 129 121 122 123 124 121 122 123 124 125 127 128 129 s s s s d d d d b s s s s d d d d b s s s s d d d d b The first, second, third, and fourth source electrodes,,, and, the first, second, third, and fourth drain electrodes,,, and, the second capacitor electrode, the first line, the second line, and the third linemay be formed of a conductive material such as metal. For example, the first, second, third, and fourth source electrodes,,, and, the first, second, third, and fourth drain electrodes,,, and, the second capacitor electrode, the first line, the second line, and the third linemay be formed of one or more of: aluminum (Al), copper (Cu), molybdenum (Mo), titanium (Ti), chromium (Cr), nickel (Ni), tungsten (W), and an alloy thereof. The first, second, third, and fourth source electrodes,,, and, the first, second, third, and fourth drain electrodes,,, and, the second capacitor electrode, the first line, the second line, and the third linemay have a single-layered structure or a multiple-layered structure.

121 121 121 112 113 122 122 122 112 113 123 123 123 112 113 124 124 124 112 113 124 124 113 125 125 s d a s d a s d a s d a d g b a. The first source electrodeand the first drain electrodemay be in contact with the both ends of the first active layerthrough contact holes provided in the gate insulation layerand the interlayer insulation layer, respectively. The second source electrodeand the second drain electrodemay be in contact with the both ends of the second active layerthrough contact holes provided in the gate insulation layerand the interlayer insulation layer, respectively. The third source electrodeand the third drain electrodemay be in contact with the both ends of the third active layerthrough contact holes provided in the gate insulation layerand the interlayer insulation layer, respectively. In addition, the fourth source electrodeand the fourth drain electrodemay be in contact with the both ends of the fourth active layerthrough contact holes provided in the gate insulation layerand the interlayer insulation layer, respectively, and the fourth drain electrodemay be in contact with the fourth gate electrodethrough a contact hole provided in the interlayer insulation layer. The second capacitor electrodemay overlap the first capacitor electrode

121 125 121 128 122 129 122 124 123 127 123 125 112 124 122 124 128 s b d s d s s d a s d d The first source electrodemay be connected to the second capacitor electrode, and the first drain electrodemay be connected to the second line. The second source electrodemay be connected to the third line, and the second drain electrodemay be connected to the fourth source electrode. The third source electrodemay be connected to the first line, and the third drain electrodemay be connected to the first capacitor electrodethrough a contact hole provided in the gate insulation layer. The fourth source electrodemay be connected to the second drain electrode, and the fourth drain electrodemay be connected to the second line.

121 121 121 121 121 122 122 122 122 122 123 123 123 123 123 124 124 124 124 124 a g s d a g s d a g s d a g s d The first active layer, the first gate electrode, the first source electrode, and the first drain electrodemay constitute the first transistor. The second active layer, the second gate electrode, the second source electrode, and the second drain electrodemay constitute the second transistor. The third active layer, the third gate electrode, the third source electrode, and the third drain electrodemay constitute the third transistor. The fourth active layer, the fourth gate electrode, the fourth source electrode, and the fourth drain electrodemay constitute the fourth transistor.

125 125 125 113 a b The first capacitor electrodeand the second capacitor electrodemay constitute the capacitorwith the interlayer insulation layerinterposed therebetween as a dielectric.

121 122 123 124 125 2 FIG. 2 FIG. 2 FIG. The first transistormay be the driving transistor DT of, the second transistormay be the emission transistor ET of, the third transistormay be the switching transistor ST of, the fourth transistormay be the connection transistor CT, and the capacitormay be the storage capacitor Cst.

127 128 1 129 2 128 1 129 2 4 FIG. 4 FIG. 4 FIG. In addition, the first linemay be the data line DL of, the second linemay be the first power line PLofsupplying the high potential voltage VDD, and the third linemay be the second power line PLofsupplying the low potential voltage VSS. However, embodiments of the present disclosure are not limited thereto. In other embodiments, the second linemay be the first power line PLsupplying the low potential voltage VSS, and the third linemay be the second power line PLsupplying the high potential voltage VDD.

2 FIG. 110 121 122 123 Meanwhile, the sensing transistor NT ofmay be further provided on the substrateand may have substantially the same as the first, second, and third transistors,, and.

114 121 122 123 124 121 122 123 124 125 127 128 129 114 110 114 114 114 s s s s d d d d b x x Next, a first passivation layermay be provided on the first, second, third, and fourth source electrodes,,, and, the first, second, third, and fourth drain electrodes,,, and, the second capacitor electrode, the first line, the second line, and the third line. The first passivation layermay be disposed substantially all over the substrate. The first passivation layermay be formed as a single layer or multiple layers of an inorganic insulating material. For example, the inorganic insulating material of the first passivation layermay include silicon nitride (SiN), silicon oxide (SiO), or silicon oxynitride (SiON). The first passivation layermay be omitted.

115 114 115 110 115 115 An overcoat layermay be provided on the first passivation layer. The overcoat layermay be disposed substantially all over the substrate. The overcoat layermay eliminate a step difference due to the layers thereunder and may have a substantially flat top surface. The overcoat layermay be formed of an organic insulating material such as photosensitive acrylic polymer (photo acryl).

132 134 115 132 134 132 134 A reflection electrodeand a connection electrodemay be provided on the overcoat layer. The reflection electrodeand the connection electrodemay be formed of a metal having relatively high reflectance. For example, the reflection electrodeand the connection electrodemay be formed of aluminum (Al), silver (Ag), or chromium (Cr).

132 121 125 132 121 125 114 115 132 125 132 121 b s. The reflection electrodemay partially overlap the first transistorand the capacitor. The reflection electrodemay be electrically connected to the first transistorand the capacitorthrough a contact hole provided in the first passivation layerand the overcoat layer. In this case, the reflection electrodemay be in contact with the second capacitor electrodethrough the contact hole, but embodiments of the present disclosure are not limited thereto. Alternatively, the reflection electrodemay be in contact with the first source electrode

134 122 124 134 122 124 114 115 134 122 134 124 d s. The connection electrodemay partially overlap the second transistorand the fourth transistor. The connection electrodemay be electrically connected to the second transistorand the fourth transistorthrough a contact hole provided in the first passivation layerand the overcoat layer. In this case, the connection electrodemay be in contact with the second drain electrodethrough the contact hole, but embodiments of the present disclosure are not limited thereto. Alternatively, the connection electrodemay be in contact with the fourth source electrode

116 132 134 116 110 116 116 116 x x A second passivation layermay be provided on the reflection electrodeand the connection electrode. The second passivation layermay be disposed substantially all over the substrate. The second passivation layermay be formed as a single layer or multiple layers of an inorganic insulating material. For example, the inorganic insulating material of the second passivation layermay include silicon nitride (SiN), silicon oxide (SiO), or silicon oxynitride (SiON). The second passivation layermay be omitted.

117 116 117 110 140 An adhesive layermay be provided on the second passivation layer. The adhesive layermay be disposed substantially all over the substrateand may fix the light-emitting elementthat is transferred thereon.

117 117 117 117 The adhesive layermay have a substantially flat top surface. The adhesive layermay be formed of an organic insulating material such as a photocurable adhesive material that is cured by light and may have adhesion. For example, the adhesive layermay be formed of photosensitive acrylic polymer (photo acryl). However, embodiments of the present disclosure are not limited thereto. Alternatively, the adhesive layermay be formed of one of a polyimide (PI) resin, an epoxy resin, a urethane resin, and a polydimethylsiloxane (PDMS) resin.

140 117 140 132 140 121 125 The light-emitting elementmay be provided on the adhesive layer. The light-emitting elementmay overlap the reflection electrode. In addition, the light-emitting elementmay partially overlap the first transistorand the capacitor.

140 140 110 The light-emitting elementmay be provided in the form of a micro light-emitting diode chip (micro LED chip or μLED chip) including an n-electrode, an n-type layer, an active layer, a p-type layer, and a p-electrode. The light-emitting elementmay have a lateral structure in which the n-electrode and the p-electrode are provided on the same side (for example, a side opposite to another side facing the substrate) and light is emitted through the same side provided with the n-electrode and the p-electrode.

140 110 However, embodiments of the present disclosure are not limited thereto. In other embodiments, the light-emitting elementmay have a flip-chip structure in which the n-electrode and the p-electrode are provided on the same side (for example, a side facing the substrate) and light is emitted through another side opposite to the same side provided with the n-electrode and the p-electrode or a vertical structure in which the n-electrode and the p-electrode are provided on opposite sides, respectively.

140 141 142 143 144 145 146 2 FIG. The light-emitting elementmay be the light-emitting diode LD ofand may include a first element electrode, a second element electrode, a light-emitting structure,, and, and a protection layer.

141 142 143 144 145 141 142 142 141 The first element electrodeand the second element electrodemay be provided on the light-emitting structure,, andand may be spaced apart from each other. The first element electrodeand the second element electrodemay be disposed at different heights. For example, the second element electrodemay be disposed higher than the first element electrode.

141 142 142 141 141 142 141 142 The first element electrodemay be provided at opposite sides of the second element electrode. That is, the second element electrodemay be disposed between two portions of the first element electrode. In this case, the first element electrodemay surround the second element electrode. However, embodiments of the present disclosure are not limited thereto. In other embodiments, the first element electrodemay be provided at one side of the second element electrode.

141 142 141 142 Here, the first element electrodemay be an n-electrode, and the second element electrodemay be a p-electrode. The first element electrodemay be a cathode, and the second element electrodemay be an anode.

141 142 However, embodiments of the present disclosure are not limited thereto. Alternatively, in other embodiments, the first element electrodemay be a p-electrode, and the second element electrodemay be an n-electrode.

141 142 141 142 The first element electrodeand the second element electrodemay be formed of a conductive material. For example, the first element electrodeand the second element electrodemay be formed of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO) or an opaque conductive material such as titanium (Ti), gold (Au), silver (Ag), copper (Cu), or an alloy thereof. However, embodiments of the present disclosure are not limited thereto.

143 144 145 143 144 145 144 143 145 The light-emitting structure,, andmay include a first element layer, a light-emitting layer, and a second element layer. The light-emitting layermay be disposed between the first element layerand the second element layer.

144 145 143 143 144 145 143 143 141 143 142 145 The light-emitting layerand the second element layermay be disposed on the first element layerand may correspond to a central part of the first element layer. The light-emitting layerand the second element layermay have a smaller width and area than the first element layerto partially expose a top surface of the first element layer. The first element electrodemay be disposed on the exposed top surface of the first element layer, and the second element electrodemay be disposed on the second element layer.

143 145 143 145 The first element layerand the second element layermay be formed by doping n-type or p-type impurities into a semiconductor material. For example, the first element layerand the second element layermay be formed by doping n-type or p-type impurities into gallium nitride (GaN), indium aluminum phosphide (InAlP), or gallium arsenide (GaAs). In addition, for example, the n-type impurities may be silicon (Si), germanium (Ge), or indium (Sn), and the p-type impurities may be magnesium (Mg), zinc (Zn), or beryllium (Be). However, embodiments of the present disclosure are not limited thereto.

144 143 145 144 144 The light-emitting layermay receive electrons and holes from the first element layerand the second element layer, respectively, and emit light. The light-emitting layermay be formed of a single quantum well (SQW) structure or a multi quantum well (MQW) structure. For example, the light-emitting layermay be formed of indium gallium nitride (InGaN) or gallium nitride (GaN), but is not limited thereto.

146 141 142 143 144 145 146 141 142 143 144 145 141 142 The protection layermay be provided with the first element electrode, the second element electrode, and the light-emitting structure,, and. The protection layermay cover and protect the first element electrode, the second element electrode, and the light-emitting structure,, andand may partially expose top surfaces of the first element electrodeand the second element electrode.

146 146 x x The protection layermay be formed as a single layer or multiple layers of an inorganic insulating material. The inorganic insulating material of the protection layermay include silicon nitride (SiN), silicon oxide (SiO), or silicon oxynitride (SiON).

118 140 117 118 110 Next, a planarization layermay be provided on the light-emitting elementand the adhesive layer. The planarization layermay be disposed substantially all over the substrate.

118 140 140 118 140 143 118 141 142 141 142 The planarization layermay surround a portion of a side surface of the light-emitting elementand may fix and protect the light-emitting element. A thickness of the planarization layermay be smaller than a thickness of the light-emitting elementand also smaller than a thickness of the first element layer. A top surface of the planarization layermay be disposed lower than the first element electrodeand the second element electrodeto thereby expose the first element electrodeand the second element electrode.

118 The planarization layermay be formed of an organic insulating material such as photosensitive acrylic polymer (photo acryl), for example and may have a substantially flat top surface.

152 154 118 140 A first contact electrodeand a second contact electrodemay be provided on the planarization layerand the light-emitting element.

152 142 140 142 152 132 132 116 117 118 The first contact electrodemay overlap the second element electrodeof the light-emitting elementand may be in contact with the second element electrode. In addition, the first contact electrodemay overlap the reflection electrodeand may be in contact with and electrically connected to the reflection electrodethrough a contact hole provided in the second passivation layer, the adhesive layer, and the planarization layer.

152 121 121 125 125 132 142 140 121 121 125 125 152 132 s b s b Accordingly, the first contact electrodemay be electrically connected to the first source electrodeof the first transistorand the second capacitor electrodeof the capacitorthrough the reflection electrode. The second element electrodeof the light-emitting elementmay be electrically connected to the first source electrodeof the first transistorand the second capacitor electrodeof the capacitorthrough the first contact electrodeand the reflection electrode.

154 141 140 141 154 134 134 116 117 118 The second contact electrodemay overlap the first element electrodeof the light-emitting elementand may be in contact with the first element electrode. In addition, the second contact electrodemay overlap the connection electrodeand may be in contact with and electrically connected to the connection electrodethrough a contact hole provided in the second passivation layer, the adhesive layer, and the planarization layer.

154 122 122 124 124 134 141 140 122 122 124 124 154 134 d s d s Accordingly, the second contact electrodemay be electrically connected to the second drain electrodeof the second transistorand the fourth source electrodeof the fourth transistorthrough the connection electrode. The first element electrodeof the light-emitting elementmay be electrically connected to the second drain electrodeof the second transistorand the fourth source electrodeof the fourth transistorthrough the second contact electrodeand the connection electrode.

152 154 152 154 The first contact electrodeand the second contact electrodemay be formed of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). Alternatively, the first contact electrodeand the second contact electrodemay be formed of a metal, and may be formed of one or more of aluminum (Al), copper (Cu), molybdenum (Mo), titanium (Ti), chromium (Cr), nickel (Ni), tungsten (W), and an alloy thereof, for example.

124 124 121 122 123 As such, the display device according to the first example embodiment of the present disclosure may include the fourth transistoras the connection element. Since the fourth transistorhas substantially the same structure and is substantially on the same plane as the first, second, and third transistors,, and, the connection element can be easily formed without an additional process.

121 122 123 Meanwhile, by providing the connection element on a different plane from the first, second, and third transistors,, and, a design area of a pixel circuit can be secured.

6 8 FIGS.to A display device according to a second example embodiment of the present disclosure will be described with reference to. The display device according to the second example embodiment of the present disclosure has substantially the same or similar configuration as that of the first example embodiment, except for the connection element. The same parts as those of the first example embodiment are designated by the same or similar reference signs, and explanation for the same parts may be shortened or omitted.

6 FIG. 1 FIG. is an equivalent circuit diagram for a sub-pixel of a display device according to a second example embodiment of the present disclosure and will be described with reference totogether.

6 FIG. In, one sub-pixel SP of the display device according to the second example embodiment of the present disclosure may include a switching transistor ST, a driving transistor DT, a sensing transistor NT, a storage capacitor Cst, and a light-emitting diode LD. In addition, the sub-pixel SP may further include an emission transistor ET and a connection diode CD.

1 1 2 1 2 2 2 1 2 2 3 The switching transistor ST may be switched according to the gate signal SCAN and may transmit the data voltage Vdata to the first node N. The driving transistor DT is connected to the first node Nand a second node N. The driving transistor DT may be switched according to a voltage of the first node Nand may transmit the high potential voltage VDD to the second node N. The sensing transistor NT may be switched according to the gate signal SCAN and may transmit the reference voltage Vref to the second node Nor transmit a voltage of the second node Nto the reference line RL. First and second capacitor electrodes of the storage capacitor Cst may be connected to the first node Nand the second node N, respectively. The anode of the light-emitting diode LD may be connected to the second node N, and the cathode of the light-emitting diode LD may be connected to a third node N.

3 1 3 1 3 The connection diode CD may be a connection element for connecting the third node Nand the first power line PLand may transmit the high potential voltage VDD to the third node N. Specifically, an anode of the connection diode CD may be connected to the first power line PLand may be supplied with the high potential voltage VDD. A cathode of the connection diode CD may be connected to the third node N.

2 FIG. The connection diode CD may serve the same as the connection transistor CT of. The connection diode CD may be an organic diode based on an organic material, and this will be described in detail later.

3 As such, in the display device according to the second example embodiment of the present disclosure, by providing the connection diode CD as the connection element and forming a voltage path, the cathode voltage of the light-emitting diode LD, i.e., the voltage of the third node Ncan be controlled. Accordingly, the light-emitting diode LD can be prevented or suppressed from emitting light in a black state.

7 FIG. A planar configuration of the display device according to the second example embodiment of the present disclosure will be described with reference to.

7 FIG. 1 FIG. 1 is a schematic plan view of a display device according to the second example embodiment of the present disclosure and shows one sub-pixel, which corresponds to the area Aof.

7 FIG. 1 2 In, the gate line GL and the emission line EL of the first direction X may cross the first power line PL, the second power line PL, and the data line DL of the second direction Y to define the sub-pixel SP. The switching transistor ST, the driving transistor DT, the sensing transistor NT, the emission transistor ET, the connection diode CD, the storage capacitor Cst, and the light-emitting diode LD may be provided in the sub-pixel SP.

In the first direction X, the driving transistor DT and the connection diode CD may be disposed adjacent to the emission transistor ET, and the switching transistor ST and the sensing transistor NT may be disposed adjacent to each other.

In the second direction Y, the storage capacitor Cst may be disposed between the driving and emission transistors DT and ET and the switching and sensing transistors ST and NT, and the connection diode CD may be disposed substantially between the driving transistor DT and the emission line EL. In this case, the connection diode CD may partially overlap the driving transistor DT.

Meanwhile, the light-emitting diode LD may be disposed to overlap the driving transistor DT.

4 FIG. The display device according to the second example embodiment of the present disclosure including the connection diode CD may operate the same as the display device ofaccording to the first example embodiment of the present disclosure including the connection transistor CT and may increase widths and areas of the driving transistor DT and the emission transistor ET compared to the display device according to the first example embodiment.

8 FIG. A cross-sectional configuration of the display device according to the second example embodiment of the present disclosure will be described in detail with reference to.

8 FIG. is a schematic cross-sectional view of a display device according to the second example embodiment of the present disclosure and shows one sub-pixel.

8 FIG. 121 122 123 125 260 140 110 140 121 122 121 125 123 260 122 260 In, the display device according to the second example embodiment of the present disclosure may include first, second, and third transistors,, and, a capacitor, an organic diode, and a light-emitting elementon a substrate. The light-emitting elementmay be electrically connected to the first transistorand the second transistor. The first transistormay be electrically connected to the capacitorand the third transistorand electrically connected to the organic diode. The second transistormay be electrically connected to the organic diode.

124 5 FIG. Namely, in the display device according to the second example embodiment of the present disclosure, the fourth transistorofmay be omitted.

121 122 123 125 110 114 115 121 122 123 125 Specifically, the first, second, and third transistors,, andand the capacitormay be provided on the substrate. The first passivation layerand the overcoat layermay be sequentially provided on the first, second, and third transistors,, andand the capacitor.

132 134 115 132 134 132 134 Next, the reflection electrodeand the connection electrodemay be provided on the overcoat layer. The reflection electrodeand the connection electrodemay be formed of a metal having relatively high reflectance. For example, the reflection electrodeand the connection electrodemay be formed of aluminum (Al), silver (Ag), or chromium (Cr).

132 121 125 134 122 132 121 140 The reflection electrodemay be electrically connected to the first transistorand the capacitor, and the connection electrodemay be electrically connected to the second transistor. Further, the reflection electrodeis disposed between the first transistorand the light-emitting element.

262 115 262 132 134 In addition, a first electrodemay be provided on the overcoat layer. The first electrodemay include the same material and be disposed on the same layer as the reflection electrodeand the connection electrode.

262 121 121 114 115 262 121 121 d The first electrodemay partially overlap the first transistorand may be electrically connected to the first transistorthrough a contact hole provided in the first passivation layerand the overcoat layer. In this case, the first electrodemay be in contact with the first drain electrodeof the first transistorthrough the contact hole.

116 132 134 262 117 116 140 117 140 262 The second passivation layermay be provided on the reflection electrode, the connection electrode, and the first electrode. The adhesive layermay be provided on the second passivation layer. The light-emitting elementmay be provided on the adhesive layer. The light-emitting elementmay be spaced apart from the first electrode.

118 140 117 Next, the planarization layermay be provided on the light-emitting elementand the adhesive layer.

118 262 116 117 264 266 262 The planarization layermay have an opening that exposes the first electrodewith the second passivation layerand the adhesive layer. A first semiconductor layerand a second semiconductor layermay be sequentially provided on the first electrodeexposed through the opening.

264 266 264 266 264 266 At least one of the first semiconductor layerand the second semiconductor layermay include an organic material and may be formed through a soluble process. That is, at least one of the first semiconductor layerand the second semiconductor layermay be an organic layer. A height of the first semiconductor layerand the second semiconductor layermay increase from the center to the edge.

264 266 However, embodiments of the present disclosure are not limited thereto. In other embodiments, at least one of the first semiconductor layerand the second semiconductor layermay include an inorganic material and may be formed through an inkjet or vacuum deposition process.

264 266 264 266 The first semiconductor layermay be a p-type semiconductor layer, and the second semiconductor layermay be an n-type semiconductor layer. The first semiconductor layermay include at least one of a hole injection layer (HIL) and a hole transport layer (HTL). The second semiconductor layermay include at least one of an electron injection layer (EIL) and an electron transport layer (ETL).

264 266 However, embodiments of the present disclosure are not limited thereto. In other embodiments, the first semiconductor layermay be an n-type semiconductor layer, and the second semiconductor layermay be a p-type semiconductor layer.

152 154 118 140 152 142 140 154 141 152 141 140 154 142 140 The first contact electrodeand the second contact electrodemay be provided on the planarization layerand the light-emitting element. The first contact electrodemay be connected to the second element electrodeof the light-emitting element. The second contact electrodemay be connected to the first element electrodeof the light-emitting element. However, embodiments of the present disclosure are not limited thereto. In other embodiments, the first contact electrodemay be connected to the first element electrodeof the light-emitting element. The second contact electrodemay be connected to the second element electrodeof the light-emitting element.

268 266 268 152 154 268 154 154 Meanwhile, a second electrodemay be provided on the second semiconductor layer. The second electrodemay include the same material and be disposed on the same layer as the first contact electrodeand the second contact electrode. In this case, the second electrodemay be connected to the second contact electrodeand may be formed as one body with the second contact electrode.

268 134 154 122 122 154 134 268 141 140 d The second electrodemay be electrically connected to the connection electrodethrough the second contact electrodeand electrically connected to the second drain electrodeof the second transistorthrough the second contact electrodeand the connection electrode. In addition, the second electrodemay be electrically connected to the first element electrodeof the light-emitting element.

262 264 266 268 260 260 262 268 262 268 6 FIG. The first electrode, the first semiconductor layer, the second semiconductor layer, and the second electrodemay constitute the organic diode, and the organic diodemay be the connection diode CD of. In this case, the first electrodemay be an anode, and the second electrodemay be a cathode. However, embodiments of the present disclosure are not limited thereto. In other embodiments, the first electrodemay be a cathode, and the second electrodemay be an anode.

121 122 123 125 6 FIG. 6 FIG. 6 FIG. The first transistormay be the driving transistor DT of, the second transistormay be the emission transistor ET of, the third transistormay be the switching transistor ST of, and the capacitormay be the storage capacitor Cst.

260 260 121 122 123 121 122 As such, the display device according to the second example embodiment of the present disclosure may include the organic diodeas the connection element. Since the organic diodemay be disposed on the different plane from the first, second, and third transistors,, and, the areas of the first transistorand the second transistor, that is, the driving transistor DT and the emission transistor ET can be expanded, and it is possible to be applied to a high resolution display device.

In addition, by increasing channel widths of the driving transistor DT and the emission transistor ET, the driving current can be increased at a lower voltage, thereby reducing power consumption and shortening the on-off time of the driving and emission transistors.

By providing the connection electrode and forming the voltage path, the display device of the present disclosure can adjust the cathode voltage of the light-emitting element. Accordingly, the light-emitting element can be prevented or suppressed from emitting light in the black state, thereby improving the image quality of the display device.

In addition, by providing the organic diode as the connection element on the different plane from the transistors, the width and area of the transistors can be expanded, the display device of the present disclosure can be applied to a high resolution display device. The driving current can be increased at a lower voltage, thereby reducing power consumption and realizing low power consumption.

It will be apparent to those skilled in the art that various modifications and variations can be made in the display device of the present disclosure without departing from the technical idea or scope of the disclosure. Thus, it is intended that the present disclosure cover the modifications and variations of this disclosure provided they come within the scope of the appended claims and their equivalents.