Memory Device with Parity Block Allocation

This U.S. non-provisional application claims priority under 35 U.S.C. § 119(a) to Korean Patent Application No. 10-2024-0177960, filed on Dec. 3, 2024, and Korean Patent Application No. 10-2025-0168783, filed on Nov. 10, 2025, in the Korean Intellectual Property Office, the disclosures of which are herein incorporated by reference in their entirety.

Memory devices may be used to store data and may be classified into volatile memory devices and nonvolatile memory devices. Volatile memory devices may lose their stored data when their power supplies are interrupted. Among volatile memory devices, a dynamic random access memory (DRAM) may be used in various fields such as mobile systems, servers, graphics devices, or the like.

Implementations of the present disclosure provide a memory device satisfying a bounded fault (BF) condition while supporting an error correction code (ECC) operation and/or a metadata mode.

An aspect of the present disclosure provides a memory device that includes a bank array including a plurality of memory cells, a row decoder connected to the bank array through a plurality of wordlines, and a column decoder connected to the bank array through a plurality of column select lines. The bank array may include a first region including a plurality of normal sub-wordline drivers and a second region including at least one partial sub-wordline driver. One a plurality of column blocks corresponding to the plurality of normal sub-wordline drivers in the first region may be allocated as a parity block.

Another aspect of the present disclosure provides a memory device that includes a bank array each including a plurality of memory cells, a row decoder connected to the bank array through a plurality of wordlines, and a column decoder connected to the bank array through a plurality of column select lines. The bank array may include a first region adjacent to one side surface of the bank array and including column blocks disposed in a direction in which the column decoder is disposed, a second region adjacent to the first region and including column blocks disposed in the direction in which the column decoder is disposed, a third region adjacent to the second region and including column blocks disposed in the direction in which the column decoder is disposed, and a fourth region adjacent to another side surface of the bank array and including at least one column block arranged in the direction in which the column decoder is disposed. Parity data may be output from the second region.

Another aspect of the present disclosure provides a storage device includes a memory device including a plurality of banks and a memory controller configured to transmit and receive data packets to and from the plurality of banks. The memory device may include a bank array including a plurality of memory cells, a row decoder connected to the bank array through a plurality of wordlines, and a column decoder connected to the bank array through a plurality of column select lines. The bank array includes a first region including a plurality of normal sub-wordline drivers and a second region including at least one partial sub-wordline driver. One of a plurality of column blocks corresponding to the plurality of normal sub-wordline drivers in the first region is allocated as a parity block.

The following description with reference to the accompanying drawings is provided to assist in a comprehensive understanding of various implementations of the present disclosure.

1 FIG.A 1 FIG.B 10 is a block diagram illustrating a storage deviceA according to some implementations, andis a conceptual block diagram illustrating an example of a bank array according to some implementations.

10 1 1 2 1 2 The storage deviceA according to some implementations may include a plurality of banks Bankto Bank n, and each bank may include a bank array. Each bank array may include a first region RGand a second region RG. The first region RGmay mainly refer to a region including column blocks corresponding to a normal sub-wordline driver, and the second region RGmay mainly refer to a region including column blocks corresponding to a partial sub-wordline driver. For example, the number of column blocks corresponding to the normal sub-wordline driver may be greater than the number of column blocks corresponding to the partial sub-wordline driver.

10 1 The storage deviceA according to some implementations may select one of a plurality of normal sub-wordline drivers in the first region RGand allocate at least one of the column blocks corresponding to the selected normal sub-wordline driver as a parity block. The parity block may refer to a column block in which parity data for an error correction code operation (hereinafter, referred to as “ECC operation”) is stored.

As will be described below, the selected normal sub-wordline driver becomes non-bounded. Accordingly, the number of bounded sub-wordline drivers may be reduced compared to the case in which the column block corresponding to the partial sub-wordline driver is allocated as the parity block. Accordingly, design complexity for satisfying a bounded fault condition (hereinafter, referred to as “BF condition”) may be reduced.

10 The storage deviceA according to some implementations may allocate at least one of the column blocks of a non-bounded sub-wordline driver as a meta block. The meta block is a column block for supporting a metadata mode, and may refer to a column block in which metadata is stored in a meta-on mode and normal data is stored in a meta-off mode.

As will described below, the number of combinations of data blocks that need to be considered to satisfy the BF condition is reduced, or the data blocks no longer need to be considered. Accordingly, the design complexity for satisfying the BF condition may be reduced compared to the case in which the column block of the bounded sub-wordline driver is allocated as the meta block.

10 As a result, the storage deviceA according to some implementations may be implemented to satisfy the BF condition while supporting the ECC operation and/or the metadata mode.

1 FIG.A 1 FIG.B 10 100 200 Referring toand, the storage deviceA according to some implementations may include a memory controllerand a memory device.

100 200 100 200 100 200 The memory controllermay control the memory device. For example, the memory controllermay control the memory devicebased on requests from a processor supporting various applications such as a server application, a personal computer (PC) application, or a mobile application. For example, the memory controllermay be included in a host including a processor, and may control the memory devicebased on the requests from the processor.

100 200 200 100 200 200 The memory controllermay transmit commands and/or addresses to the memory deviceto control the memory device. In addition, the memory controllermay transmit data to the memory deviceor receive data from the memory device.

200 100 200 100 100 The memory devicemay receive data from the memory controllerand store the received data. The memory devicemay read the stored data in response to a request from the memory controllerand transmit the read data to the memory controller.

200 200 In some implementations, the memory devicemay be a memory device including volatile memory cells. For example, the memory devicemay be one of various DRAM devices such as a double data rate synchronous dynamic random access memory (DDR SDRAM) device, a DDR2 SDRAM device, a DDR3 SDRAM device, a DDR4 SDRAM device, a DDR5 SDRAM device, a DDR6 SDRAM device, a low power double data rate (LPDDR) SDRAM device, an LPDDR2 SDRAM device, an LPDDR3 SDRAM device, an LPDDR4 SDRAM device, an LPDDR4X SDRAM device, an LPDDR5 SDRAM device, a graphics double data rate synchronous graphics random access memory (GDDR SGRAM) device, a GDDR2 SGRAM device, a GDDR3 SGRAM device, a GDDR4 SGRAM device, a GDDR5 SGRAM device, or a GDDR6 SGRAM device.

200 In some examples, the memory devicemay be a stacked memory device in which DRAM dies are stacked, such as a high bandwidth memory (HBM) device, an HBM2 device, an HBM3 device, or an HBM4 device.

200 200 200 In some implementations, the memory devicemay be included in a memory module such as a dual in-line memory module (DIMM). For example, the memory devicemay be included in a registered DIMM (RDIMM), a load reduced DIMM (LRDIMM), an unbuffered DIMM (UDIMM), a fully buffered DIMM (FB-DIMM), a small outline DIMM (SO-DIMM). However, this is only an example, and the memory devicemay be included in another memory module such as a single in-line memory module (SIMM).

200 In some implementations, the memory devicemay be an SRAM device, a NAND flash memory device, a NOR flash memory device, an RRAM device, an FRAM device, a PRAM device, a TRAM device, or an MRAM device.

200 1 The memory devicemay include a plurality of banks Bankto Bank n.

1 1 1 1 1 Each of the plurality of banks Bankto Bank n may include a bank array, a row decoder, and a column decoder. For example, a first bank Bankmay include a first bank array BA, a first row decoder RD, and a first column decoder CD.

1 A plurality of bank arrays BAto BAn may each include memory cells storing data. The row decoder may activate a selected wordline among a plurality of wordlines based on a row address. The column decoder may activate a selected column select line among a plurality of column select lines based on a column address.

For ease of description, it is defined that each bank array includes DRAM cells. However, this is only an example, and each bank array may be implemented to include volatile memory cells other than DRAM cells. In some implementations, each bank array may be implemented to include memory cells of the same type, or implemented to include memory cells of different types.

1 1 2 Each of the plurality of bank arrays BAto BAn according to some implementations may include a first region RGand a second region RG.

1 1 The first region RGmay include column blocks corresponding to the normal sub-wordline driver. For example, normal sub-wordline drivers and column blocks corresponding thereto may be disposed in the first region RG.

1 FIG.B 1 2 3 1 1 1 1 For example, as illustrated in, three normal sub-wordline drivers SWD, SWD, and SWDand column blocks CB corresponding thereto may be disposed in the first region RG. However, this is merely an example, and the number of normal sub-wordline drivers disposed in the first region RGis not limited thereto. In addition, according to some implementations, the normal sub-wordline drivers in the first region RGmay be disposed to have a symmetrical structure of even and odd types. A portion of the partial sub-wordline drivers may be disposed in the first region RG.

2 2 The second region RGmay include column blocks corresponding to a partial sub-wordline driver. For example, partial sub-wordline drivers and column blocks corresponding thereto may be disposed in the second region RG.

1 FIG.B 4 2 2 2 For example, as illustrated in, a single partial sub-wordline driver SWDand a single column block CB corresponding thereto may be disposed in the second region RG. However, this is merely an example, and the number of partial sub-wordline drivers and the number of column blocks disposed in the second region RGare not limited thereto. According to some implementations, two or more partial sub-wordline drivers may be disposed in the second region RG. In addition, two or three column blocks may correspond to the partial sub-wordline driver.

The sub-wordline driver according to some implementations may be classified into a normal sub-wordline driver and a partial sub-wordline driver based on the number of corresponding column blocks.

1 FIG.B 1 2 3 In some implementations, the normal sub-wordline driver may be disposed at a middle and/or one side of the bank array. A sub-wordline may be connected to opposite sides of the normal sub-wordline driver. The normal sub-wordline driver may be electrically connected to column blocks through two corresponding sub-wordlines. For example, as illustrated in, a single sub-wordline SWL may correspond to two column blocks. Each of the normal sub-wordline drivers SWD, SWD, and SWDmay be electrically connected to four column blocks CB.

In some implementations, the partial sub-wordline driver may be disposed at an edge of the bank array. A sub-wordline may be connected to one side or opposite sides of the partial sub-wordline driver. The partial sub-wordline driver may be electrically connected to column blocks through one or two corresponding sub-wordlines.

1 FIG.B 4 For example, as illustrated in, the partial sub-wordline driver may be connected to a single sub-wordline SWL, and the single sub-wordline SWL may correspond to a single column block. The partial sub-wordline driver SWDmay be electrically connected to the single column block. However, this is merely an example, and implementations are not limited thereto.

4 For example, the partial sub-wordline driver may be connected to a single sub-wordline SWL, and the single sub-wordline SWL may correspond to two column blocks. The partial sub-wordline driver SWDmay be electrically connected to two column blocks.

4 For example, the partial sub-wordline driver may be connected to two sub-wordlines SWL. One of the two sub-wordlines SWL may correspond to two column blocks, and the other sub-wordline SWL may correspond to a single column block. The partial sub-wordline driver SWDmay be electrically connected to three column blocks.

The sub-wordline driver according to some implementations may be classified into a bounded sub-wordline driver and a non-bounded sub-wordline driver based on whether an error correction code (ECC) error that may occur during the ECC operation should be limited to a predetermined region to satisfy the BF condition.

For ease of description, it is defined that the BF condition is that data affected by a bounded fault is limited to a maximum of four sub-packets. In addition, it is defined that data output from a single data block form a single sub-packet.

1 1 2 3 1 1 1 1 In some implementations, when a fault occurs in a first normal sub-wordline driver SWDamong the normal sub-wordline drivers SWD, SWD, and SWDdisposed in the first region RG, a failure may also occur in the four column blocks corresponding to the first normal sub-wordline driver SWD. The four column blocks connected to the first normal sub-wordline driver SWDmay all be data blocks storing normal data ND. For example, the data output from the four column blocks connected to the first normal sub-wordline driver SWDmay form four sub-packets.

1 The Correction error should be limited to the four data blocks connected to the first normal sub-wordline driver SWDto satisfy the BF condition. For example, the Correction error occurring during the ECC operation should not propagate to a column block connected to another sub-wordline driver. As a result, the normal sub-wordline driver having corresponding column blocks all allocated as data blocks may be classified as a bounded sub-wordline driver.

2 1 2 3 1 2 2 2 In some implementations, when a fault occurs in a second normal sub-wordline driver SWDamong the normal sub-wordline drivers SWD, SWD, and SWDdisposed in the first region RG, a failure may also occur in the four column blocks corresponding to the second normal sub-wordline driver SWD. However, one of the four column blocks connected to the second normal sub-wordline driver SWDis a parity block storing parity data PD. The parity data PD does not form a sub-packet. For example, the parity block is irrelevant to the BF condition, and thus only the three column blocks connected to the second normal sub-wordline driver SWDneeds to considered to satisfy the BF condition.

2 The Correction error does not need to be limited to the column blocks connected to the second normal sub-wordline driver SWDto satisfy the BF condition. For example, even when the Correction error occurring during the ECC operation propagates to a data block connected to another sub-wordline driver, the number of failed sub-packets is four, which means that the BF condition is still satisfied. As a result, the normal sub-wordline driver in which at least one of the corresponding column blocks is allocated as the parity block may be classified as a non-bounded sub-wordline driver.

4 2 4 4 In some implementations, when a fault occurs in the partial sub-wordline driver SWDdisposed in the second region RG, a failure may also occur in the column block corresponding to the partial sub-wordline driver SWD. Only one column block is connected to the partial sub-wordline driver SWD, and thus the number of failed data blocks is also one.

Even when the Correction error propagates to a data block connected to another sub-wordline driver, the BF condition may still be satisfied. As a result, the partial sub-wordline driver may be classified as a non-bounded sub-wordline driver.

10 According to some implementations, the storage deviceA may support the ECC operation. An H-matrix must be designed for the ECC operation. For example, the H-matrix must be designed considering bounded sub-wordline drivers. As the number of bounded sub-wordline drivers among the sub-wordline drivers increases, the design complexity of the H-matrix increases. For example, as the number of non-bounded sub-wordline drivers among the sub-wordline drivers increases, the design complexity of the H-matrix be reduced. As described above, the non-bounded sub-wordline driver includes a sub-wordline driver to which the parity block is allocated, among normal sub-wordline drivers, and a partial sub-wordline driver.

10 1 The storage deviceA according to some implementations may select one of the plurality of normal sub-wordline drivers in the first region RGand allocate at least one of the column blocks corresponding to the selected normal sub-wordline driver as the parity block. Accordingly, the selected normal sub-wordline driver may be a non-bounded sub-wordline driver. Thus, the number of bounded sub-wordline drivers may be reduced compared to the case in which the column block corresponding to the partial sub-wordline driver is allocated as the parity block. As a result, the design complexity of the H-matrix for satisfying the BF condition may be reduced.

1 FIG.A 1 FIG.B 1 1 FIGS.A andB 10 1 2 2 3 Continuing to refer toand, the storage deviceaccording to some implementations may support a metadata mode. For example,illustrate an implementation in which two meta blocks are provided to support the metadata mode. The metadata mode may include a first mode Mode, a second A mode ModeA, a second B mode ModeB, and a third mode Mode.

1 200 200 200 200 The first mode Modemay be a mode in which normal data ND and metadata MD corresponding thereto are stored together in the memory deviceand read together from the memory device. The metadata is related to the normal data, and may be data used to improve performance of the memory deviceor reinforce security of the memory device. For example, the metadata may include information on a type, a length, and an attribute of the corresponding normal data, but implementations are not limited thereto.

1 In the first mode Mode, two meta blocks may be both used to store the metadata MD.

1 1 FIGS.A andB 1 2 1 4 2 1 For example, referring to, in the first mode Mode, a meta block connected to the second normal sub-wordline driver SWDin the first region RGmay store the metadata MD, and a meta block connected to the partial sub-wordline driver SWDin the second region RGmay store the metadata MD. The first mode Modemay be referred to as, for example, a ‘meta-on’ mode, because the metadata MD is input and output along with the normal data ND.

1 In the first mode Mode, a read operation or a write operation on the normal data ND and the metadata MD corresponding thereto may be performed simultaneously. For example, the normal data ND and the metadata MD corresponding thereto may be output from the data block and the meta block, respectively, through a single read operation. In addition, the normal data ND and the metadata MD corresponding thereto may be stored in the data block and the meta block, respectively, through a single write operation.

2 2 200 200 The second A mode ModeA and the second B mode ModeB may be modes in which the normal data ND and the metadata MD corresponding thereto are stored together in the memory deviceand read together from the memory device.

2 2 In the second A mode ModeA and the second B mode ModeB, one meta block may be used to store the metadata MD, and the other meta blocks may be used to store the normal data ND.

1 FIG.A 1 FIG.B 2 2 1 4 2 For example, referring toand, in the second A mode ModeA, a meta block connected to the second normal sub-wordline driver SWDin the first region RGmay store the metadata MD, and a meta block connected to the partial sub-wordline driver SWDin the second region RGmay store the normal data ND.

2 2 1 4 2 In the second B mode ModeB, a meta block connected to the second normal sub-wordline driver SWDin the first region RGmay store the normal data ND, and a meta block connected to the partial sub-wordline driver SWDin the second region RGmay store the metadata MD.

2 2 The second A mode ModeA and the second B mode ModeB may each be referred to as, for example, a ‘meta-on’ mode or a ‘half meta-on’ mode because the metadata MD is input and output along with the normal data ND.

2 2 In the second A mode ModeA and the second B mode ModeB, a read operation or a write operation on the normal data ND and the metadata MD corresponding thereto may be performed simultaneously. For example, the normal data ND and the metadata MD corresponding thereto may be output from the data block and the meta block, respectively, through a single read operation. In addition, the normal data ND and the metadata MD corresponding thereto may be stored in the data block and the meta block, respectively, through a single write operation.

3 200 200 The third mode Modemay be a mode in which only the normal data ND is stored in the memory deviceand read from the memory device.

3 3 2 1 4 2 3 1 FIG.A 1 FIG.B In the third mode Mode, the two meta blocks may be both used to store the normal data ND. For example, referring toand, in the third mode Mode, a meta block connected to the second normal sub-wordline driver SWDin the first region RGmay store the normal data ND, and a meta block connected to the partial sub-wordline driver SWDin the second region RGmay also store the normal data ND. The third mode Modemay be referred to as, for example, a ‘meta-off’ mode because the metadata MD is not input and output.

3 In the third mode Mode, a read operation or a write operation on the normal data ND stored in the data block and the meta block may be performed simultaneously. For example, the normal data ND stored in the data block and the normal data ND stored in the meta block may be output, respectively, through a single read operation. In addition, the normal data ND may be stored in the data block and the meta block, respectively, through a single write operation.

10 The storage deviceA according to some implementations may allocate at least one of the column blocks of the non-bounded sub-wordline driver as the meta block. For example, the meta block may be allocated to the non-bounded sub-wordline driver.

1 FIG.A 1 FIG.B 2 1 4 2 For example, referring toand, the two meta blocks may be allocated to the non-bounded sub-wordline driver. For example, the meta block may be allocated to the non-bounded second normal sub-wordline driver SWDin the first region RG. In addition, the meta block may be allocated to the non-bounded partial sub-wordline driver SWDin the second region RG.

2 1 1 2 2 3 4 2 1 2 2 3 The meta block allocated to the second normal sub-wordline driver SWDin the first region RGmay be used to store the metadata MD in the first mode Modeand the second A mode ModeA, and may be used to store the normal data ND in the second B mode ModeB and the third mode Mode. In addition, the meta block allocated to the partial sub-wordline driver SWDin the second region RGmay be used to store the metadata MD in the first mode Modeand the second B mode ModeB, and may be used to store the normal data ND in the second A mode ModeA and the third mode Mode.

When the meta block is used to store the normal data ND, the normal data ND stored in the meta block may be data that supplements or replaces other data blocks. For example, the normal data ND of the meta block may be mapped to other data blocks. Accordingly, when the meta block is allocated to the bounded sub-wordline driver, the number of data blocks that should be considered to design the H-matrix satisfying the BF condition increases by the number of data blocks to which the meta block is mapped. This means that the design complexity of the H-matrix may increase.

10 In contrast, the storage deviceA according to some implementations may allocate at least one of the column blocks of the non-bounded sub-wordline driver as a meta block. Accordingly, the number of combinations of data blocks that should be considered to satisfy the BF condition may be reduced or does not need to be considered. As a result, the design complexity for satisfying the BF condition may be reduced compared to the case in which the column block of the bounded sub-wordline driver is allocated as the meta block.

10 10 As discussed above, the storage deviceA according to some implementations may support the ECC operation and may allocate at least one of the column blocks corresponding to the normal sub-wordline driver as a parity block. Accordingly, the design complexity for satisfying the BF condition may be reduced. In addition, the storage deviceA according to some implementations supports the metadata mode and may allocate at least one of the column blocks of the non-bounded sub-wordline driver as a meta block. As a result, the design complexity for satisfying the BF condition may be reduced.

1 1 FIGS.A andB In, for ease of description, at least one of the column blocks corresponding to the normal sub-wordline driver is allocated as the parity block, and one of the column blocks of the non-bounded sub-wordline driver created by allocating the parity block is allocated as the meta block. However, this is merely an example, and implementations are not limited thereto. For example, the implementation in which the design complexity of the H-matrix is reduced by allocating at least one of the column blocks corresponding to the normal sub-wordline driver as the parity block and the implementation in which the design complexity of the H-matrix is reduced by allocating at least one of the column blocks of the non-bounded sub-wordline driver as the meta block may be implemented independently.

2 FIG. 2 FIG. 1 FIG.A 200 200 200 is a block diagram illustrating a configuration of a memory deviceaccording to some implementations. The memory deviceofmay correspond to the memory deviceof.

2 FIG. 200 210 220 230 400 240 250 260 270 310 285 290 350 320 Referring to, the memory devicemay include a control logic circuit, an address register, a bank control circuit, a refresh control circuit, a row address multiplexer, a column address latch, a row decoder group, a column decoder group, a memory cell array, a sense amplifier unit, an input/output gating circuit, an ECC engine, and a data input/output buffer.

310 310 1 310 310 1 310 n n The memory cell arraymay include a plurality of bank arrays_to_. Each of the plurality of bank arrays_to_may include a plurality of memory cells. For example, each of the plurality of memory cells may be formed at an intersection of a corresponding wordline and a corresponding bitline.

260 260 1 260 260 1 260 310 1 310 n n n. The row decoder groupmay include a plurality of row decoders_to_. Each of the plurality of row decoders_to_may be connected to a corresponding bank array among the plurality of bank arrays_to_

285 285 1 285 285 1 285 310 1 310 n n n. The sense amplifier unitmay include a plurality of sense amplifiers_to_. Each of the plurality of sense amplifiers_to_may be connected to a corresponding bank array among the plurality of bank arrays_to_

270 270 1 270 270 1 270 310 1 310 n n n The column decoder groupmay include a plurality of column decoders_to_. Each of the plurality of column decoders_to_may be connected to a corresponding bank array of the plurality of bank arrays_to_through column select lines.

310 1 310 1 2 1 2 n According to some implementations, each of the plurality of bank arrays_to_may include the first region RGand the second region RG. In the first region RG, normal sub-wordline drivers and column blocks corresponding thereto may be mainly disposed. In the second region RG, partial sub-wordline drivers and column blocks corresponding thereto may be mainly disposed.

1 According to some implementations, one of the plurality of normal sub-wordline drivers disposed in the first region RGis selected, and a parity block may be allocated to at least one of the column blocks corresponding to the selected normal sub-wordline driver. The selected normal sub-wordline driver may be non-bounded. Accordingly, the design complexity for satisfying the BF condition may be reduced.

1 2 According to some implementations, at least one of the column blocks of the non-bounded sub-wordline driver may be allocated as the meta block. For example, the column block of the normal sub-wordline driver to which the parity block is allocated, among the plurality of normal sub-wordline drivers in the first region RG, and/or the column block of the partial sub-wordline driver of the second region RGmay be allocated as the meta block. Accordingly, the design complexity for satisfying the BF condition may be reduced.

220 100 220 230 240 250 1 FIG.A The address registermay receive an address ADDR including a bank address BANK_ADDR, a row address ROW_ADDR, and a column address COL_ADDR from the memory controller(refer to). The address registermay provide the received bank address BANK_ADDR to the bank control circuit, may provide the received row address ROW_ADDR to the row address multiplexer, and may provide the received column address COL_ADDR to the column address latch.

230 260 1 260 270 1 270 n n The bank control circuitmay generate bank control signals in response to the bank address BANK_ADDR. As an example, a row decoder corresponding to the bank address BANK_ADDR among the row decoders_to_may be activated in response to the bank control signals. A column decoder corresponding to the bank address BANK_ADDR among the column decoders_to_may be activated in response to the bank control signals.

240 220 400 240 240 260 1 260 n. The row address multiplexermay receive the row address ROW_ADDR from the address registerand may receive a refresh row address REF_ADDR from the refresh control circuit. The row address multiplexermay selectively output the row address ROW_ADDR or the refresh row address REF_ADDR as a row address RA. The row address RA output from the row address multiplexermay be applied to each of the row decoders_to_

400 210 The refresh control circuitmay sequentially increase or decrease the refresh row address REF_ADDR in a normal refresh mode in response to refresh signals from the control logic circuit.

400 400 The refresh control circuitmay receive a hammer address HADDR in a hammer refresh mode. The refresh control circuitmay output an address of adjacent memory cell rows adjacent to an aggressor memory cell row as the refresh row address REF_ADDR based on the hammer address HADDR.

230 260 1 260 240 n A row decoder selected by the bank control circuit, among the plurality of row decoders_to_, may activate a wordline corresponding to the row address RA output from the row address multiplexer. For example, the selected row decoder may apply a wordline driving voltage to the wordline corresponding to the row address.

250 220 250 250 270 1 270 n. The column address latchmay receive the column address COL_ADDR from the address registerand may temporarily store the received column address COL_ADDR. In addition, for example, in a burst mode, the column address latchmay gradually increase the received column address COL_ADDR. The column address latchmay apply a column address COL_ADDR′ obtained by temporarily storing or gradually increasing the column address COL_ADDR to each of the column decoders_to_

230 270 1 270 290 n The column decoder activated by the bank control circuit, among the plurality of column decoders_to_, may activate the sense amplifier corresponding to the bank address BANK_ADDR and the column address COL_ADDR through the I/O gating circuit.

290 290 310 1 310 3101 310 n n. The I/O gating circuitmay include circuits to perform gating input and output data. In addition, the I/O gating circuitmay include data latches to store code words output from the bank arrays_to_and write drivers to write data in the bank arraysto_

310 1 310 290 350 320 320 100 n In some implementations, a code word CW read out from the selected bank array among the bank arrays_to_during the read operation may be sensed by the sense amplifier corresponding to the selected bank array and may be stored in the data latches of the I/O gating circuit. In addition, the code word CW stored in the data latches may be ECC decoded by the ECC engineand may be provided to the data I/O bufferas data DTA. The data I/O buffermay generate the data signal DQ based on the data DTA and may provide the data signal DQ together with the data strobe signal DQS to the memory controller.

310 1 310 320 320 350 350 290 290 n In some implementations, during the write operation, data DTA to be written in the selected bank array among the bank arrays_to_may be received as the data signal DQ by the data I/O buffer. The data I/O buffermay convert the data signal DQ into the data DTA and may provide the data DTA to the ECC engine. The ECC enginemay generate parity bits or parity data based on the data DTA and may provide the code word CW including the data DTA and the parity bits to the I/O gating circuit. The I/O gating circuitmay write the code word CW in the selected bank array.

320 350 320 350 The data I/O buffermay convert the data signal DQ into the data DTA during the write operation and may provide the data DTA to the ECC engine. The data I/O buffermay convert the data DTA provided from the ECC engineinto the data signal DQ during the read operation.

350 350 The ECC enginemay perform an ECC encoding operation on the data DTA during the write operation. The ECC enginemay perform an ECC decoding operation on the code word CW during the read operation.

210 200 210 200 210 211 100 212 200 The control logic circuitmay control an operation of the memory device. As an example, the control logic circuitmay generate the control signals to allow the memory deviceto perform the write operation, the read operation, the normal refresh operation, and the hammer refresh operation. The control logic circuitmay include a command decoderthat decodes a command CMD provided from the memory controllerand a mode register set (MRS)that sets an operation mode of the memory device.

211 211 The command decodermay decode the command CMD to generate internal command signals such as an internal active signal IACT, an internal precharge signal IPRE, an internal read signal IRD, an internal write signal IWR, etc. In addition, the command decodermay decode a chip select signal and command/address signals to generate control signals corresponding to the command CMD.

212 200 212 200 1 2 2 3 200 1 200 2 200 2 3 The mode register setmay set the operation mode of the memory device. According to some implementations, the mode register setmay include a mode register to set the operation mode of the memory deviceto the first mode Mode, the second A mode ModeA, the second B mode ModeB, or the third mode Mode. For example, when a first value is set in the mode register, the memory devicemay operate in the first mode Mode. When a second value is set in the mode register, the memory devicemay operate in the second A mode ModeA. Similarly, when a third value or a fourth value is set in the mode register, the memory devicemay operate in the second B mode ModeB or the third mode Mode.

1 2 1 2 1 2 According to some implementations, the first region RGand the second region RGmay be commonly connected to a plurality of wordlines. Therefore, when a single wordline corresponding to the row address among the plurality of wordlines is activated, a region corresponding to the activated wordline may be activated together in the first region RGand the second region RG. When the column address is applied, the column select lines of the first region RGcorresponding to the applied column address and the column select lines of the second region RGcorresponding to the applied column address may be activated simultaneously.

200 1 2 2 200 3 Accordingly, when the memory deviceoperates in the first mode Mode, the second A mode ModeA, and the second B mode ModeB, the normal data, the metadata, and the parity data may be input together or output together. In addition, when the memory deviceoperates in the third mode Mode, the normal data and the parity data may be input together or output together.

200 200 As described above, the memory deviceaccording to some implementations may support the ECC operation and may allocate at least one of the column blocks corresponding to the normal sub-wordline driver as a parity block. Accordingly, the design complexity for satisfying the BF condition may be reduced. The memory deviceaccording to some implementations may support the metadata mode and may allocate at least one of the column blocks of the non-bounded sub-wordline driver as a meta block. Accordingly, the design complexity for satisfying the BF condition may be reduced.

3 FIG. 3 FIG. 1 1 FIGS.A andB 2 FIG. 1 1 is a diagram illustrating an example of a bank array according to some implementations. The bank array BAofmay correspond to the bank array BAofand, but implementations are not limited thereto.

3 FIG. 1 0 0 0 0 Referring to, the first bank array BAmay include a plurality of wordlines WLto WLi, a plurality of bitlines BLto BLj, and a plurality of memory cells MC. The plurality of memory cells MC may be disposed at the intersection of the wordlines WLto WLi and the bitlines BLto BLj.

In some implementations, each memory cell MC may be a DRAM cell. For example, each memory cell MC may include a cell transistor, connected to a wordline and a bitline, and a cell capacitor connected to the cell transistor.

0 7 A single column select line CSL may be electrically connected to a plurality of bitlines. For example, the single column select line CSL may be electrically connected to eight bitlines BLto BL. In some examples, 8 bits of data may be read from or written in memory cells MCs through a single wordline and a single column select line CSL. However, this is merely an example, and the one column select line CSL may also be implemented to be electrically connected to a various number of bitlines other than 8.

1 1 In some implementations, the wordlines extending in a row direction may be referred to as a row of the bank array BA. In addition, the column select lines CSL extending in a column direction may be referred to as a column of the bank array BA.

4 FIG. 4 FIG. 1 FIG.A 2 FIG. 3 FIG. 200 is a diagram illustrating a bank structure of a memory device according to some implementations. A bank ofmay be, for example, one of the banks included in the memory deviceofor, but implementations are not limited thereto. For ease of description, similarly to, it is defined that a single column select line CSL corresponds to eight bitlines.

4 FIG. 4 FIG. Referring to, the bank may include a bank array BA, a row decoder RD corresponding to the bank array BA, and a column decoder CD corresponding to the bank array BA. In, WL may denote a wordline and CSL may denote a column select line.

0 0 0 0 The bank array BA may include a plurality of column blocks CBto CBj. At least one of the plurality of column blocks CBto CBj may be allocated as a parity block. At least one of the plurality of column blocks CBto CBj may be allocated as a meta block. Among the plurality of column blocks CBto CBj, column blocks excluding the meta block and the parity block may be allocated as data blocks.

0 1 2 It is defined that first to (j−1)-th column blocks CBto CBj−1 correspond to the above-described first region RGand j-th column block CBj corresponds to the above-described second region RG. In addition, it is defined that two meta blocks and one parity block are allocated.

0 1 At least one column block connected to a normal sub-wordline driver, among the first to (j−1)-th column blocks CBto CBj−1 in the first region RG, may be allocated as a parity block. For example, an (i+1)-th column block CBi+1 may be allocated as the parity block.

0 1 In addition, a column block adjacent to the (i+1)-th column block CBi+1 allocated as the parity block, among the first to (j−1)-th column blocks CBto CBj−1 in the first region RG, may be allocated as a meta block. For example, the i-th column block CBi corresponding to the same sub-wordline driver as the (i+1)-th column block CBi+1 may be allocated as the meta block.

2 In addition, the j-th column block CBj in the second region RGmay be allocated as a meta block. For example, a column block connected to the partial sub-wordline driver may be allocated as the meta block.

In addition, column blocks excluding the column blocks CBi, CBi+1, and CBj allocated as the parity block and the meta block may be allocated as data blocks.

0 0 0 0 In some implementations, the number of column select lines CSLto CSLl of the column blocks CBi, CBj allocated as the meta block may be different from the number of column select lines CSLto CSLk of the column block allocated as the data block. For example, the number of column select lines CSLto CSLl of the column blocks CBi, CBj allocated as the meta block may be 64 (for example, l=63), and the number of column select lines CSLto CSLk of the column block allocated as the data block may be 60 (for example, k=59). However, this is merely an example, and implementations are not limited thereto. According to some implementations, the number of column select lines of the column block allocated as the meta block may be the same as the number of column select lines of the column block allocated as the data block.

0 0 0 0 In addition, in some implementations, the number of column select lines CSLto CSLm of the column block CBi+1 allocated as the parity block may be different from the number of column select lines CSLto CSLk of the column block allocated as the data block. For example, the number of column select lines CSLto CSLm of the column block CBi+1 allocated as the parity block may be 64 (for example, m=63), and the number of column select lines CSLto CSLk of the column block allocated as the data block may be 60 (for example, k=59). However, this is merely an example, and implementations are not limited thereto. According to some implementations, the number of column select lines of the column block allocated as the parity block may be the same as the number of column select lines of the column block allocated as the data block.

0 0 The row decoder RD may activate a wordline corresponding to the applied row address, and the column decoder CD may activate a column select line corresponding to the applied column address. According to some implementations, the column decoder CD may include j+1 sub-column decoders SCDto SCDj, respectively corresponding to j+1 column blocks CBto CBj, and an operation of each column block may be controlled by a corresponding sub-column decoder. However, implementations are not limited thereto.

1 2 2 3 5 7 FIGS.to According to some implementations, the bank may support one of the above-described first mode Mode, second A mode ModeA, second B mode ModeB, and third mode Mode. This will be described in more detail inbelow.

5 7 FIGS.to 5 7 FIGS.to 5 7 FIGS.to 200 1 2 2 3 8 18 0 18 9 are diagrams illustrating an example in which the memory deviceaccording to some implementations operates in the first mode Mode, the second A mode ModeA, the second B mode ModeB, and the third mode Mode. For ease of description,illustrates an example in which the bank includes 19 column blocks, a column block allocated as a data block includes 60 column select lines, and a column block allocated as a meta block or the parity block includes 64 column select lines. In addition,illustrate an example in which two column blocks CBand CB, among the 19 column blocks CBto CB, are allocated as meta blocks, one column block CBis allocated as a parity block, and the remaining 16 column blocks are allocated as data blocks.

5 FIG. 1 0 1 Referring to, in the first mode Mode, the two meta blocks Mand Mmay be both used to store metadata MD. The bank may operate based on 60 column addresses, respectively corresponding to 60 column select lines.

0 0 0 0 18 For example, when a column address corresponding to one column select line (for example, CSL) is applied in a state where a first wordline WLis activated, the column decoder CD may activate the column select line CSLin each of the 19 column blocks CBto CB.

0 9 0 17 1 8 8 0 8 0 15 18 1 2 1 59 Each activated column select line CSLcorresponds to 8 bitlines. Therefore, the column block CBallocated as a parity block P, among the column blocks CBto CBof the first region RG, may input or outputbits of parity data PD, the column block CBallocated as the 0th meta block Mmay input or outputbits of metadata MD, and each of the remaining column blocks allocated as data blocks Dto Dmay input or output 8 bits of normal data ND. In addition, the column block CBallocated as a first meta block Mof the second region RGmay input or output 8 bits of metadata. This may be equally applied to the remaining column addresses CSLto CSL.

6 FIG.A 6 FIG.B 2 0 1 0 1 Referring toand, in the second A mode ModeA, among the two meta blocks Mand M, the 0th meta block Mmay be used to store the metadata MD and the first meta block Mmay be used to store the normal data ND. The bank may operate based on 64 column addresses, respectively corresponding to 64 column select lines.

1 0 15 1 0 15 1 In some implementations, the normal data ND stored in the first meta block Mmay be data for the 0th to 15th data blocks Dto D. For example, the column select lines of the first meta block Mmay be mapped to the 0th to 15th data blocks Dto Din units of 4, respectively. The 60 column select lines included in each data block and the 4 column select lines included in the first meta block Mmay form column addresses for a single data block.

0 1 0 0 1 For example, the 60 column select lines included in the 0th data block Dand the four column select lines included in the first meta block Mmay form a column address for the 0th data block D. The column addresses of the 60 column select lines included in the 0th data block Dmay be set to ‘0 to 59,’ and the column addresses of the 4 column select lines included in the first meta block Mmay be set to ‘60 to 63.’

1 1 1 1 1 In addition, for example, the 60 column select lines included in the first data block Dand the 4 column select lines included in the first meta block Mmay form a column address for the first data block D. The column addresses of the 60 column select lines included in the first data block Dmay be set to ‘0 to 55 and 60 to 63,’ and the column addresses of the 4 column select lines included in the first meta block Mmay be set to ‘56 to 59.’

2 15 1 Similarly, column addresses for the remaining data blocks Dto Dmay be configured using the column select lines of each data block and the corresponding first meta block M.

2 0 1 0 1 0 0 15 2 2 In the second B mode ModeB, among the two meta blocks Mand M, the 0th meta block Mmay be used to store the normal data ND and the first meta block Mmay be used to store the metadata MD. The normal data ND stored in the 0th meta block Mmay be data for the 0th to 15th data blocks Dto D. The operation of the second B mode ModeB is similar to the operation of the second A mode ModeA, and thus a detailed description thereof will be omitted.

2 2 According to the above-described mapping relationship, in the second A mode ModeA and the second B mode ModeB, the bank may operate based on 64 column addresses.

7 FIG. 3 0 1 Referring to, in the third mode Mode, the two meta blocks Mand Mmay be both used to store the normal data ND.

0 0 7 0 0 7 0 In some implementations, the normal data ND stored in the 0th meta block Mmay be data for the 0th to 7th data blocks Dto D. For example, the column select lines of the 0th meta block Mmay be mapped to the 0th to 7th data blocks Dto Din units of 8, respectively. The 60 column select lines included in each data block and the 8 column select lines included in the 0th meta block Mmay form column addresses for a single data block.

1 8 15 1 8 15 1 In some implementations, the normal data ND stored in the first meta block Mmay be data for the 8th to 15th data blocks Dto D. For example, the column select lines of the first meta block Mmay be mapped to the 8th to 15th data blocks Dto Din units of 8, respectively. The 60 column select lines included in each data block and the 8 column select lines included in the first meta block Mmay form column addresses for a single data block.

3 According to the above-described mapping relationship, in the third mode Mode, the bank may operate based on a maximum of 68 column addresses.

5 7 FIGS.to As described in, the storage device according to some implementations may support various modes by supporting the ECC operation and the metadata mode. In each mode, the storage device according to some implementations may read normal data, metadata, and/or parity data together from a bank array through a single read operation, or store the normal data, the metadata, and/or the parity data together in the bank array through a single write operation.

In addition, as will described below, the storage device according to some implementations may reduce the design complexity of an H-matrix by allocating at least one of the column blocks corresponding to the normal sub-wordline driver as a parity block or by allocating at least one of the column blocks of the non-bounded sub-wordline driver as a meta block. As a result, the memory device may be efficiently implemented.

8 FIG. is a diagram illustrating a structure of a data packet and a sub-packet according to some implementations.

8 FIG. 1 FIG. 1 FIG. 200 100 200 100 Referring to, a single data packet may include a plurality of sub-packets. The data packet may refer to a unit of data transmitted from the memory device(see) to the memory controller(see) or received by the memory devicefrom the memory controller.

5 7 FIGS.to In some implementations, a size of the sub-packet may be the same as a size of data input or output through a single column select line. For example, when a single column select line corresponds to 8 bitlines as illustrated in, a unit of data input or output to each data block may be 8 bits and a unit of the sub-packet may also be 8 bits.

100 100 100 The sub-packet may be data received from the memory controlleror data transmitted to the memory controller. Therefore, on-die ECC parity data that is not transmitted to the memory controllermay not form a sub-packet.

1 2 2 3 In some implementations, the sub-packet may include normal data. For example, in the above-described first mode Mode, the normal data output from each data block may form a single sub-packet. Alternatively, in the above-described second A mode ModeA, second B mode ModeB, or third mode Mode, the normal data output from each data block and the meta block may form a single sub-packet.

100 Alternatively, in some implementations, the sub-packet may include normal data and metadata. For example, when the metadata is data that should be transmitted to the memory controller, the metadata may also form a sub-packet.

9 9 FIGS.A andB are diagrams illustrating examples of the BF condition according to some implementations.

9 FIG.A Referring to, a data packet may be 128 bits. For example, 16 sub-packets of 8 bits may form a single data packet.

5 7 FIGS.to BF condition may be that data affected by a bounded fault is limited to a maximum of 4 sub-packets. For example, when 128 bits of data are output and fetched through one read operation as described in, the data affected by the bounded fault may be limited to a maximum of 4 sub-packets.

9 FIG.B Alternatively, referring to, the data packet may be 64 bits. For example, 8 sub-packets of 8 bits may form a single data packet.

A BF condition may be that data affected by a bounded fault is limited to a maximum of 3 sub-packets.

The storage device according to some implementations may be designed to satisfy the BF condition even when a fault occurs in the sub-wordline driver.

10 14 FIGS.to For example, the storage device according to some implementations may satisfy the BF condition while reducing the design complexity of the H-matrix by allocating at least one of the column blocks corresponding to the normal sub-wordline driver as the parity block. This will be described in more detail with reference tobelow.

15 18 FIGS.to Alternatively, the storage device according to some implementations may satisfy the BF condition while reducing the design complexity of the H-matrix by allocating at least one of the column blocks of the non-bounded sub-wordline driver as the meta block. This will be described in more detail with reference tobelow.

Hereinafter, for ease of description, it is defined that the BF condition is that data affected by a bounded fault is limited to a maximum of 4 sub-packets.

10 11 FIGS.toC 10 FIG. 11 FIG.A 11 FIG.B 11 FIG.C are diagrams illustrating sub-wordline drivers and column blocks corresponding to each sub-wordline driver according to some implementations. For example,illustrates a structure of a bank array of the memory device according to some implementations.illustrates a sub-wordline driver disposed at the left edge of the bank array and column blocks corresponding thereto.illustrates a sub-wordline driver disposed at the right edge of the bank array and column blocks corresponding thereto.illustrates a sub-wordline driver disposed in the middle of the bank array and column blocks corresponding thereto.

10 11 FIGS.toC 1 7 FIGS.to 5 7 FIGS.to 0 18 For example, the bank array ofmay be one of the bank arrays of the banks included in the memory device of, but implementations are not limited thereto. For ease of description, similarly to, it is defined that the bank array includes 19 column blocks CBto CB.

10 FIG. 0 18 0 5 0 4 0 18 Referring to, the bank array may include a plurality of column blocks CBto CBand a plurality of sub-wordline blocks O_SWBto O_SWBand E_SWBto E_SWBdisposed between the plurality of column blocks CBto CB.

0 18 0 18 0 18 5 7 FIGS.to The plurality of column blocks CBto CBmay each be allocated as one of a data block, a parity block, or a meta block. The plurality of column blocks CBto CBmay correspond to the column blocks CBto CBdescribed in.

0 5 0 4 0 18 0 5 0 4 The plurality of sub-wordline blocks O_SWBto O_SWBand E_SWBto E_SWBmay be disposed between the plurality of column blocks CBto CB. Each of the plurality of sub-wordline blocks O_SWBto O_SWBand E_SWBto E_SWBmay include at least one sub-wordline driver, and each sub-wordline driver may drive a corresponding sub-wordline.

0 5 0 4 0 5 0 4 The plurality of sub-wordline blocks O_SWBto O_SWBand E_SWBto E_SWBmay be classified into odd sub-wordline blocks O_SWBto O_SWBand even sub-wordline blocks E_SWBto E_SWB.

0 5 0 4 The odd sub-wordline blocks O_SWBto O_SWBand the even sub-wordline blocks E_SWBto E_SWBmay be alternately disposed.

0 0 1 2 1 3 4 1 5 6 2 5 2 4 For example, a 0th odd sub-wordline block O_SWBmay be disposed at the left edge of the bank array, and a 0th even sub-wordline block E_SWBmay be disposed between a first column block CBand a second column block CB. In addition, a first odd sub-wordline block O_SWBmay be disposed between a third column block CBand a fourth column block CB, and a first even sub-wordline block E_SWBmay be disposed between a fifth column block CBand a sixth column block CB. Similarly, second to fifth odd sub-wordline blocks O_SWBto O_SWBand second to fourth even sub-wordline blocks E_SWBto E_SWBmay be alternately disposed.

0 5 Each of the odd sub-wordline blocks O_SWBto O_SWBmay include a plurality of odd sub-wordline drivers.

0 0 1 1 2 5 For example, the 0th odd sub-wordline block O_SWBmay include a plurality of 0th odd sub-wordline drivers O_SWD. The first odd sub-wordline block O_SWBmay include a plurality of first odd sub-wordline drivers O_SWD. Similarly, the second to fifth odd sub-wordline blocks O_SWBto O_SWBmay each include a plurality of odd sub-wordline drivers.

0 5 The odd sub-wordline block disposed at the edge, among the odd sub-wordline blocks O_SWBto O_SWB, may include a partial sub-wordline driver.

10 FIG. 11 FIG.A 0 0 0 0 1 0 0 For example, as illustrated inand, the odd sub-wordline driver O_SWDincluded in the 0th odd sub-wordline block O_SWBdisposed at the left edge may drive a single sub-wordline O_SWLand may be electrically connected to two column blocks CBand CB. Therefore, the odd sub-wordline driver O_SWDincluded in the 0th odd sub-wordline block O_SWBmay be a partial sub-wordline driver.

10 FIG. 11 FIG.B 5 5 9 18 5 5 In addition, for example, as illustrated inand, the odd sub-wordline driver O_SWDincluded in the 5th odd sub-wordline block O_SWBdisposed at the right edge may drive a single sub-wordline O_SWLand may be electrically connected to a single column block CB. Therefore, the odd sub-wordline driver O_SWDincluded in the fifth odd sub-wordline block O_SWBmay be a partial sub-wordline driver.

0 5 The odd sub-wordline block disposed in the middle, among the odd sub-wordline blocks O_SWBto O_SWB, may include a normal sub-wordline driver.

10 FIG. 1 1 1 2 2 3 4 5 1 1 2 3 4 2 4 For example, as illustrated in, the odd sub-wordline driver O_SWDincluded in the first odd sub-wordline block O_SWBdisposed in the middle may drive two sub-wordlines O_SWLand O_SWLand may be electrically connected to four column blocks CB, CB, CB, and CB. Therefore, the odd sub-wordline driver O_SWDincluded in the first odd sub-wordline block O_SWBmay be a normal sub-wordline driver. Similarly, the odd sub-wordline drivers O_SWD, O_SWD, and O_SWDincluded in the second to fourth odd sub-wordline blocks O_SWBto O_SWBmay be normal sub-wordline drivers.

0 4 Each of the even sub-wordline blocks E_SWBto E_SWBmay include a plurality of even sub-wordline drivers.

0 0 1 1 2 4 For example, the 0th even sub-wordline block E_SWBmay include a plurality of 0th even sub-wordline drivers E_SWD. The first even sub-wordline block E_SWBmay include a plurality of first even sub-wordline drivers E_SWD. Similarly, the second to fourth even sub-wordline blocks E_SWBto E_SWBmay each include a plurality of even sub-wordline drivers.

0 4 The even sub-wordline block disposed at the edge, among the even sub-wordline blocks E_SWBto E_SWB, may include a partial sub-wordline driver.

10 FIG. 11 FIG.B 4 4 8 9 16 17 18 4 4 For example, as illustrated inand, the even sub-wordline driver E_SWDincluded in the fourth even sub-wordline block E_SWBdisposed at the right edge may drive two sub-wordlines E_SWLand E_SWLand may be electrically connected to three column blocks CB, CB, and CB. Therefore, the even sub-wordline driver E_SWDincluded in the fourth even sub-wordline block E_SWBmay be a partial sub-wordline driver.

0 4 The even sub-wordline block disposed in the middle among the even sub-wordline blocks E_SWBto E_SWBmay include a normal sub-wordline driver.

10 FIG. 11 FIG.C 1 1 2 3 4 5 6 7 1 1 0 2 3 0 2 3 For example, as illustrated inand, the even sub-wordline driver E_SWDincluded in the first even sub-wordline block E_SWBdisposed in the middle may drive two sub-wordlines E_SWLand E_SWLand may be electrically connected to four column blocks CB, CB, CB, CB. Therefore, the even sub-wordline driver E_SWDincluded in the first even sub-wordline block E_SWBmay be a normal sub-wordline driver. Similarly, the even sub-wordline drivers E_SWD, E_SWD, and E_SWDincluded in the 0th, second, and third even sub-wordline blocks E_SWB, E_SWB, and E_SWBmay be normal sub-wordline drivers.

10 FIG. Continuing to refer to, each wordline may include a plurality of sub-wordlines. Each sub-wordline may be driven by a corresponding sub-wordline driver.

0 0 9 0 0 1 2 1 3 4 2 5 6 3 7 8 4 9 5 For example, a 0th wordline WLmay include a plurality of odd sub-wordlines O_SWLto O_SWL. Each odd sub-wordline may be driven by a corresponding odd sub-wordline driver. For example, a 0th odd sub-wordline O_SWLmay be driven by a 0th odd sub-wordline driver O_SWD. First and second odd sub-wordline O_SWLand O_SWLmay be driven by a first odd sub-wordline driver O_SWD, third and fourth odd sub-wordline O_SWLand O_SWLmay be driven by a second odd sub-wordline driver O_SWD, fifth and sixth odd sub-wordline O_SWLand O_SWLmay be driven by a third odd sub-wordline driver O_SWD, and seventh and eighth odd sub-wordline O_SWLand O_SWLmay be driven by a fourth odd sub-wordline driver O_SWD. A ninth odd sub-wordline O_SWLmay be driven by a fifth odd sub-wordline driver O_SWD.

1 0 9 Similarly, a first wordline WLmay include a plurality of even sub-wordlines E_SWLto E_SWL, and each even sub-wordline may be driven by a corresponding even sub-wordline driver.

12 FIG. 10 11 FIGS.toC is a diagram simplifying a layout relationship of the sub-wordline drivers, sub-wordlines, and column blocks described in.

12 FIG. 0 4 Referring to, according to some implementations, 0th to 4th even sub-wordline drivers E_SWDto E_SWDmay be disposed in a bank array.

0 3 The 0th to third even sub-wordline drivers E_SWDto E_SWDmay each be a normal sub-wordline driver, and may correspond to four column blocks.

0 0 1 0 3 0 0 1 0 0 1 2 3 1 1 10 FIG. 10 FIG. 10 FIG. 10 FIG. For example, the 0th even sub-wordline driver E_SWDmay drive a 0th sub-wordline SWLand a first sub-wordline SWLand may be electrically connected to the 0th to third column blocks CBto CB. The 0th sub-wordline SWLis a sub-wordline corresponding to the 0th and first column blocks CBand CB, and may include a 0th odd sub-wordline O_SWL(see) and a 0th even sub-wordline E_SWL(see). In addition, the first sub-wordline SWLis a sub-wordline corresponding to the second and third column blocks CBand CB, and may include a first odd sub-wordline O_SWL(see) and a first even sub-wordline E_SWL(see).

4 The fourth even sub-wordline driver E_SWDis a partial sub-wordline driver and may correspond to three column blocks.

4 8 9 16 18 For example, the fourth even sub-wordline driver E_SWDmay drive an eighth sub-wordline SWLand a ninth sub-wordline SWLand may be electrically connected to the 16th to 18th column blocks CBto CB.

0 5 According to some implementations, 0th to fifth odd sub-wordline drivers O_SWDto O_SWDmay be disposed in the bank array.

1 4 The first to fourth odd sub-wordline drivers O_SWDto O_SWDmay each be a normal sub-wordline driver and may correspond to four column blocks, respectively.

1 1 2 2 5 For example, the first odd sub-wordline driver O_SWDmay drive a first sub-wordline SWLand a second sub-wordline SWLand may be electrically connected to the second to fifth column blocks CBto CB.

0 5 The 0th and fifth odd sub-wordline drivers O_SWDand O_SWDare each a partial sub-wordline driver and may correspond to two column blocks and a single column block, respectively.

0 0 0 1 5 9 18 For example, the 0th odd sub-wordline driver O_SWDmay drive the 0th sub-wordline SWLand may be electrically connected to the 0th and first column blocks CBand CB. The fifth odd sub-wordline driver O_SWDmay drive the ninth sub-wordline SWLand may be electrically connected to the 18th column block CB.

1 1 0 17 The first region RGmay include column blocks connected to the normal sub-wordline drivers. For example, the first region RGmay include 0th to 17th column blocks CBto CB.

2 15 2 3 0 1 0 1 The sub-wordline drivers corresponding to the second to 15th column blocks CBto CBmay all be normal sub-wordline drivers. For example, the second and third column blocks CBand CBcorrespond to the 0th even sub-wordline driver E_SWDand the first odd sub-wordline driver O_SWD, and the 0th even sub-wordline driver E_SWDand the first odd sub-wordline driver O_SWDmay both be normal sub-wordline drivers.

0 1 16 17 0 1 0 0 0 0 In addition, a portion of the sub-wordline drivers corresponding to the 0th, first, 16th, and 17th column blocks CB, CB, CB, and CBmay be normal sub-wordline drivers, and the remaining portion may be partial sub-wordline drivers. For example, the 0th and first column blocks CBand CBmay correspond to the 0th even sub-wordline driver E_SWDand the 0th odd sub-wordline driver O_SWD. The 0th even sub-wordline driver E_SWDmay be a normal sub-wordline driver, and the 0th odd sub-wordline driver O_SWDmay be a partial sub-wordline driver.

2 2 18 4 5 18 The second region RGmay include column blocks connected to the partial sub-wordline drivers. For example, the second region RGmay include the 18th column block CB. The sub-wordline drivers E_SWDand O_SWDcorresponding to the 18th column block CBmay both be partial sub-wordline drivers.

13 FIG. 13 FIG. 12 FIG. 0 is a diagram illustrating a comparative example in which a column block corresponding to a partial sub-wordline driver is allocated as a parity block. For ease of description, it is defined that a structure of a bank array ofis the same as the structure of the bank array of. In addition, it is defined that a fault occurs in the 0th even sub-wordline driver E_SWD.

13 FIG. 2 Referring to, in the comparative example, a column block of the second region RGis allocated as the parity block P.

4 5 4 5 0 1 The sub-wordline drivers E_SWDand O_SWDcorresponding to the parity block P are originally all partial sub-wordline drivers. Therefore, regardless of whether the parity block P is allocated, the sub-wordline drivers E_SWDand O_SWDmay be non-bounded sub-wordline drivers. In addition, the 0th odd sub-wordline driver O_SWDin the first region RGis also a partial sub-wordline driver, and thus may be a non-bounded sub-wordline driver.

0 3 1 4 0 3 1 4 In addition, column blocks corresponding to the eight normal sub-wordline drivers E_SWDto E_SWDand O_SWDto O_SWDare all allocated as either a data block and/or a meta block. Therefore, the eight normal sub-wordline drivers E_SWDto E_SWDand O_SWDto O_SWDmay all be bounded sub-wordline drivers.

0 0 3 5 4 Under these circumstances, when a fault occurs in one of the bounded sub-wordline drivers, failures may occur in all four column blocks connected thereto. In addition, when a correction error occurs during an ECC operation, the failure may propagate to another column block. For example, when a fault occurs in the 0th even sub-wordline driver E_SWD, a failure caused by the correction error mc may occur not only in the corresponding data blocks Dto Dbut also in another data block D. When the BF condition is limited to a maximum ofsub-packets as described above, the BF condition may not be satisfied.

13 FIG. Accordingly, to satisfy the BF condition, the correction error should not propagate to another column block even when a fault occurs in the bounded sub-wordline driver. For example, bounded sub-wordline drivers should be considered when designing an H-matrix. This means that as the number of bounded sub-wordline drivers increases, the design complexity of the H-matrix increases. In the comparative example of, eight bounded sub-wordline drivers should be considered when designing the H-matrix.

14 FIG. 14 FIG. 12 13 FIGS.and is a diagram illustrating examples in which a column block corresponding to a normal sub-wordline driver is allocated as a parity block. For ease of description, it is defined that a structure of a bank array ofis the same as the bank array of.

14 FIG. 1 1 Referring to, according to some implementations, one of the column blocks in the first region RGmay be allocated as a parity block P. For example, the ninth column block in the first region RGmay be allocated as the parity block P.

2 2 2 2 6 13 FIG. 14 FIG. The sub-wordline drivers E_SWDand O_SWDcorresponding to the parity block P are all normal sub-wordline drivers. As the parity block P is allocated, the sub-wordline drivers E_SWDand O_SWDmay be classified as non-bounded sub-wordline drivers. Accordingly, the number of bounded sub-wordline drivers may be reduced by 2. For example, while the number of bounded sub-wordline drivers is 8 in the comparative example of, the number of bounded sub-wordline drivers may be 6, which is reduced by 2, in the implementation of. Accordingly, onlybounded sub-wordline drivers need to be considered when designing the H-matrix, leading to a reduction in the design complexity of the H-matrix.

14 FIG. 14 FIG. 1 1 1 1 1 1 Continuing to refer to, the first region RGmay be classified into three regions RGA, RGB, and RGC. In the 1B region RGB, each column block may correspond to two normal sub-wordline drivers. Therefore, as illustrated in, when one of the column blocks in the 1B region RGB is allocated as the parity block P, two normal sub-wordline drivers may be non-bounded. For example, the number of bounded sub-wordline drivers may decrease by 2.

1 1 21 24 FIGS.to However, this is only an example, and implementations are not limited thereto. According to some implementations, one of the column blocks in the 1A region RGA or the 1C region RGC may also be allocated as a parity block. The number of bounded sub-wordline drivers may decrease by 1. This will be described in more detail inbelow.

15 FIG. 15 FIG. 12 14 FIGS.to 2 3 is a diagram illustrating a comparative example in which a column block corresponding to a bounded sub-wordline driver is allocated as a meta block. For ease of description, it is defined that a structure of a bank array ofis the same as those of. In addition, it is defined that a tenth column block is allocated as a parity block P, and a fault occurs in a second odd sub-wordline driver O_SWD. In addition, it is defined that the bank array operates in a third mode Mode.

15 FIG. 2 0 1 Referring to, in the comparative example, column blocks corresponding to the second odd sub-wordline driver O_SWD, which is a bounded sub-wordline driver, are allocated as meta blocks Mand M.

2 6 7 0 1 2 Under these circumstances, when a fault occurs in the second odd sub-wordline driver O_SWD, a failure may occur in four column blocks D, D, M, and Mconnected to the second odd sub-wordline driver O_SWD.

3 0 0 7 1 8 15 6 7 0 7 8 15 6 7 0 8 6 7 1 8 6 7 7 14 6 7 7 15 Similarly to the operation of the above-described third mode Mode, the column select lines of the 0th meta block Mmay be mapped to the 0th to 7th data blocks Dto D, and the column select lines of the first meta block Mmay be mapped to the eighth to 15th data blocks Dto D. Accordingly, a combination of data blocks in which the failure has occurred may be (D, D, Dto D, and Dto D). For example, a failure may occur in combinations of data blocks such as (D, D, D, D), (D, D, D, D), . . . , (D, D, D, D), and (D, D, D, D). As a result, when the BF condition is limited to a maximum of 4 sub-packets as described above, the H-matrix should be designed considering many such combinations of data blocks. This means that the design complexity of the H-matrix increases.

16 FIG. 16 FIG. 12 15 FIGS.to 14 FIG. is a diagram illustrating an example in which a column block corresponding to a non-bounded sub-wordline driver is allocated as a meta block. For ease of description, it is defined that a structure of a bank array ofis the same as those of. In addition, similarly to, it is defined that a ninth column block is allocated as a parity block P.

16 FIG. 1 2 2 1 Referring to, a ninth column block in a first region RGmay be allocated as a parity block P. Therefore, two normal sub-wordline drivers E_SWDand O_SWDmay be non-bounded. The first region RGmay be classified into a strong bound region SBRG, a weak bound region WBRG, and a non-bound region NBRG based on a bound status of the sub-wordline driver to which each column block corresponds.

0 1 0 0 1 1 For example, 0th and first data blocks Dand Dcorrespond to a single bounded sub-wordline driver E_SWD. Therefore, the 0th and first data blocks Dand Dmay belong to a first weak bound region WBRG.

2 5 2 3 0 1 4 5 1 1 2 5 1 For example, second to fifth data blocks Dto Dcorrespond to two bounded sub-wordline drivers. For example, the second and third data blocks Dand Dcorrespond to two bounded sub-wordline drivers E_SWDand O_SWD, and the fourth and fifth data blocks Dand Dcorrespond to two bounded sub-wordline drivers O_SWDand E_SWD. Therefore, the second to fifth data blocks Dto Dmay belong to a first strong bound region SBRG.

6 7 1 6 7 2 For example, sixth and seventh data blocks Dand Dcorrespond to a single bounded sub-wordline driver E_SWD. Therefore, the sixth and seventh data blocks Dand Dmay belong to a second weak bound region WBRG.

0 0 1 For example, the 0th meta block and the first parity block Mand P do not correspond to the bounded sub-wordline driver. Therefore, the 0th meta block and the first parity block Mand P may belong to a first non-bound region NBRG.

8 9 3 10 13 2 14 15 4 Similarly, eighth and ninth data blocks Dand Dmay belong to a third weak bound region WBRG, tenth to thirteenth data blocks Dto Dmay belong to a second strong bound region SBRG, and fourteenth and fifteenth data blocks Dand Dmay belong to a fourth weak bound region WBRG.

1 2 2 The first meta block Min the second region RGdoes not correspond to the bounded sub-wordline driver, and thus may belong to a second non-bound region NBRG.

0 1 0 0 Under these circumstances, according to some implementations, the 0th meta block Mmay be allocated to the first non-bound region NBRG. For example, the 0th meta block Mmay be disposed adjacent to the parity block P. For example, the 0th meta block Mand the parity block P may correspond to the same sub-wordline driver and the same sub-wordline.

2 6 7 0 6 7 0 7 For example, even when a fault occurs in the second odd sub-wordline driver O_SWD, the combination of column blocks that should be considered for the BF condition may be D, D, and M. For example, only three column blocks should be considered to satisfy the BF condition. When the BF condition is limited to a maximum of 4 sub-packets as described above, the BF condition may be satisfied in spite of occurrence of correction error. Accordingly, when an H-matrix is designed, the combination of data blocks does not need to be considered. Alternatively, when the combination of data blocks is considered, only the combination of D, D, and Dto Dneeds to be considered. As a result, the design complexity of the H-matrix may be reduced.

16 FIG. 1 2 1 2 In addition, according to some implementations, as illustrated in, the first meta block Mmay be allocated to the second non-bound region NBRG. For example, the first meta block Mmay be allocated to the second region RGcorresponding to partial sub-wordlines.

4 14 15 1 14 15 8 15 For example, even when a fault occurs in the fourth even sub-wordline driver E_SWD, the combination of column blocks that should be considered for the BF condition may be D, D, and M. Accordingly, when the BF condition is limited to a maximum of 4 sub-packets as described above, the BF condition may be satisfied in spite of occurrence of correction error. Accordingly, when the H-matrix is designed, the combination of data blocks does not need to be considered. Alternatively, when the combination of data blocks is considered, only the combination of D, D, and Dto Dneeds to be considered. As a result, the design complexity of the H-matrix may be reduced.

0 1 0 1 As a result, the storage device according to some implementations may reduce the design complexity of the H-matrix by arranging the meta blocks Mand Madjacent to the parity block P or by arranging the meta blocks Mand Mat the edge of the bank array.

16 FIG. 0 1 0 1 In, both the two meta blocks Mand Mhave been described as being allocated to the column block of the non-bound region. However, this is only an example, and implementations are limited thereto. According to some implementations, only one of the two meta blocks Mand Mmay be disposed in a non-bound region.

17 FIG. 18 FIG. 17 FIG. 17 18 FIGS.and 1 14 FIGS.and 10 is a block diagram illustrating a storage deviceB according to some implementations.is a diagram illustrating an example of the bank array of. The storage device and the bank array ofare similar to the storage device and the bank array of. Therefore, the same or similar configurations are denoted by the same or similar reference numerals, and redundant descriptions thereof will be omitted.

1 18 FIGS.to 1 18 FIGS.to 2 In, the second region RGhas been described as being formed at the right edge of the bank array. For example, in, partial sub-wordlines have been described as being disposed at the right edge of the bank array. However, this is merely illustrative, and implementations are not limited thereto.

17 18 FIGS.and 10 100 200 2 0 0 Referring to, the storage deviceB according to some implementations may include a memory controllerand a memory device. In a bank array of each bank, a second region RGmay be formed on a left side of the bank array. For example, a 0th even sub-wordline driver E_SWDand a 0th odd sub-wordline driver O_SWD, which are partial sub-wordline drivers, may be disposed at the left side of the bank array.

10 1 0 1 According to some implementations, the storage deviceB may select one of the plurality of normal sub-wordline drivers in the first region RGand allocate at least one of the column blocks corresponding to the selected normal sub-wordline driver as a parity block P. In addition, the 0th meta block Mmay be allocated to correspond to the same sub-wordline driver and the same sub-wordline as the parity block P, and the first meta block Mmay be allocated to correspond to the partial sub-wordline driver.

10 Accordingly, the storage deviceB may satisfy a BF condition while supporting an ECC operation and/or a meta data mode.

19 FIG. 20 FIG. 19 FIG. 21 FIG. 22 FIG. 21 FIG. 19 22 FIGS.to 1 14 FIGS.and 10 10 is a block diagram illustrating a storage deviceC according to some implementations.is a diagram illustrating an example of the bank array of.is a block diagram illustrating a storage deviceD according to some implementations.is a diagram illustrating an example of the bank array of. The storage device and the bank array ofare similar to the storage device and the bank array of. Therefore, the same or similar configurations are denoted by the same or similar reference numerals, and redundant descriptions will be omitted.

1 14 FIGS.and 1 1 1 1 1 In, the first region RGhas been described as being divided into three regions RGA, RGB, and RGC, and one of the column blocks in the first B region RGB has been described as being allocated as the parity block P. However, this is merely illustrative, and implementations are not limited thereto.

19 20 FIGS.and 10 1 Referring to, the storage deviceC may allocate one of the column blocks in the first A region RGA as a parity block P.

1 1 13 FIG. Column blocks in the first A region RGA may each correspond to a single normal sub-wordline driver and a single partial sub-wordline driver. Accordingly, when one of the column blocks in the first A region RGA is allocated as the parity block P, a single normal sub-wordline driver may be non-bounded. For example, the number of bounded sub-wordline drivers may decrease by 1. Accordingly, the design complexity of an H-matrix may be reduced compared to the comparative example of.

21 22 FIGS.and 10 1 Alternatively, referring to, a storage deviceD according to some implementations may allocate one of the column blocks in a first C region RGC as a parity block P.

1 1 13 FIG. Column blocks in the first C region RGC may each correspond to a single normal sub-wordline driver and a single partial sub-wordline driver. Accordingly, when one of the column blocks in the first C region RGC is allocated as a parity block P, a single normal sub-wordline driver may be non-bounded. For example, the number of bounded sub-wordline drivers may decrease by 1. Accordingly, the design complexity of an H-matrix may be reduced compared to the comparative example of.

23 FIG. 24 FIG. 23 FIG. 23 24 FIGS.and 1 18 FIGS.to 10 is a block diagram illustrating a storage deviceE according to some implementations, andis a diagram illustrating an example of the bank array of. The storage device and the bank array ofare similar to the storage device and the bank array of. Therefore, the same or similar configurations are denoted by the same or similar reference numerals, and redundant descriptions thereof will be omitted.

1 18 FIGS.to In, two meta blocks have been described as being provided. However, this is merely illustrative, and implementations are not limited thereto. According to some implementations, only one meta block may be provided, or no meta block may be provided.

23 24 FIGS.and 24 FIG. 10 0 0 1 2 0 2 2 Referring to, the storage deviceE according to some implementations may provide only one meta block M. For example, as illustrated in, the meta block Mmay be allocated to a column block adjacent to the parity block P allocated to a first B region RGB. An operation corresponding to the above-mentioned ModeA may be performed. Alternatively, the meta block Mmay be allocated to a column block of the second region RG, and an operation corresponding to the above-mentioned ModeB may be performed.

10 1 1 FIG.A As a result, the storage deviceE according to some implementations may provide only one meta block, and may support the meta data mode excluding the first mode Modeof.

As set forth above, according to some implementations, a memory device may satisfy a bounded fault condition while supporting an error correction operation and/or a meta data mode.

While this specification contains many specific implementation details, these should not be construed as limitations on the scope of any invention or on the scope of what may be claimed, but rather as descriptions of features that may be specific to particular implementations of particular inventions. Certain features that are described in this specification in the context of separate implementations can also be implemented in combination in a single implementation. Conversely, various features that are described in the context of a single implementation can also be implemented in multiple implementations separately or in any suitable subcombination. Moreover, although features may be described above as acting in certain combinations, one or more features from a combination can in some cases be excised from the combination, and the combination may be directed to a subcombination or variation of a subcombination.

While various implementations have been shown and described above, it will be apparent to those skilled in the art that modifications and variations could be made without departing from the scope of the present inventive concept as defined by the appended claims.