Three-Dimensional Memory Devices and Methods for Forming the Same

This application is a divisional of U.S. Application No. 17/843,636, filed on June 17, 2022, which is incorporated by reference herein in its entirety.

The present disclosure relates to memory devices and methods for forming memory devices, and more particularly, to three-dimensional (3D) memory devices and methods for forming 3D memory devices.

Planar semiconductor devices, such as memory cells, are scaled to smaller sizes by improving process technology, circuit design, programming algorithm, and fabrication process. However, as feature sizes of the semiconductor devices approach a lower limit, planar process and fabrication techniques become challenging and costly. A 3D semiconductor device architecture can address the density limitation in some planar semiconductor devices, for example, Flash memory devices.

A 3D semiconductor device can be formed by stacking semiconductor wafers or dies and interconnecting them vertically so that the resulting structure acts as a single device to achieve performance improvements at reduced power and a smaller footprint than conventional planar processes. Among the various techniques for stacking semiconductor substrates, bonding, such as hybrid bonding, is recognized as one of the promising techniques because of its capability of forming high-density interconnects.

In one aspect, a 3D memory device is disclosed. The 3D memory device includes a doped semiconductor layer, a source select gate line disposed on the doped semiconductor layer, a stack structure including interleaved conductive layers and dielectric layers formed on the source select gate line, and a channel structure extending through the stack structure and the source select gate line and in contact with the doped semiconductor layer. The channel structure includes a semiconductor channel and a memory film. The source select gate line is in contact with the semiconductor channel.

In some implementations, the source select gate line and the conductive layers comprise different materials. In some implementations, the doped semiconductor layer is in contact with the semiconductor channel.

In some implementations, the source select gate line comprises a source select gate dielectric layer and a source select gate conductive layer in contact with the source select gate dielectric layer, and the source select gate dielectric layer is in direct contact with the semiconductor channel. In some implementations, each of the dielectric layer is in direct contact with the memory film.

3 3 In another aspect, aD memory device is disclosed. TheD memory device includes a doped semiconductor layer, a source select gate line disposed on the doped semiconductor layer, a stack structure including interleaved word lines and dielectric layers formed on the source select gate line, and a channel structure extending through the stack structure and the source select gate line and in contact with the doped semiconductor layer. The source select gate line includes a source select gate conductive layer surrounded by a source select gate dielectric layer. Each word line includes a gate electrode surrounded by a gate dielectric layer. The channel structure includes a semiconductor channel and a memory film. The source select gate dielectric layer is in contact with the semiconductor channel, and the gate dielectric layer is in contact with the memory film.

In some implementations, the source select gate dielectric layer is between the source select gate conductive layer and the semiconductor channel. In some implementations, the gate dielectric layer and the memory film are between the gate electrode and the semiconductor channel. In some implementations, the source select gate dielectric layer is in direct contact with the semiconductor channel. In some implementations, the source select gate conductive layer includes polysilicon.

3 3 3 In still another aspect, a system is disclosed. The system includes aD memory device configured to store data and a memory controller. TheD memory device includes a doped semiconductor layer, a source select gate line disposed on the doped semiconductor layer, a stack structure including interleaved conductive layers and dielectric layers formed on the source select gate line, and a channel structure extending through the stack structure and the source select gate line and in contact with the doped semiconductor layer. The channel structure includes a semiconductor channel and a memory film. The source select gate line is in contact with the semiconductor channel. The memory controller is coupled to theD memory device and is configured to control operations of the channel structure through the source select gate line.

3 3 In yet another aspect, a system is disclosed. The system includes aD memory device configured to store data and a memory controller. TheD memory device includes a doped semiconductor layer, a source select gate line disposed on the doped semiconductor layer, a stack structure including interleaved word lines and dielectric layers formed on the source select gate line, and a channel structure extending through the stack structure and the source select gate line and in contact with the doped semiconductor layer. The source select gate line includes a source select gate conductive layer surrounded by a source select gate dielectric layer. Each word line includes a gate electrode surrounded by a gate dielectric layer. The channel structure includes a semiconductor channel and a memory film. The source select gate dielectric layer is in contact with the semiconductor channel, and the gate dielectric layer is in contact with the memory film. The memory controller is coupled to the 3D memory device and is configured to control operations of the channel structure through the source select gate line.

3 In yet another aspect, a method for forming aD memory device is disclosed. A first sacrificial layer is formed on a semiconductor layer. A dielectric stack including a plurality of first dielectric layers and a plurality of second dielectric layers is formed interleaved on the first sacrificial layer. The first sacrificial layer and the plurality of second dielectric layers include different materials. A channel structure is formed extending through the dielectric stack in contact with the first sacrificial layer. The channel structure includes a semiconductor channel and a memory film. The plurality of second dielectric layers are replaced with a plurality of word lines. The semiconductor layer and the first sacrificial layer are removed to expose a portion of the channel structure. A doped semiconductor layer is formed on the channel structure.

In some implementations, the first sacrificial layer has a high etch selectivity comparing to the first dielectric layers and the second dielectric layers. In some implementations, the first sacrificial layer comprises high dielectric constant (high-k) material. In some implementations, the first sacrificial layer comprises tungsten.

In some implementations, the channel structure and a dummy channel structure are formed extending vertically through the dielectric stack in contact with the first sacrificial layer. In some implementations, an opening is formed extending vertically through the dielectric stack to expose the first sacrificial layer. The plurality of second dielectric layers are removed through the opening to form a plurality of first cavities. The plurality of word lines are formed in the plurality of first cavities. A slit structure is formed in the opening.

In some implementations, the semiconductor layer is removed until being stopped by the first sacrificial layer. The first sacrificial layer and a portion of the memory film of the channel structure are removed to expose a portion of the semiconductor channel of the channel structure.

In some implementations, the doped semiconductor layer is formed on the portion of the semiconductor channel of the channel structure. The doped semiconductor layer is activated. In some implementations, an interconnection structure is formed on the doped semiconductor layer.

3 In yet another aspect, a method for forming aD memory device is disclosed. A first sacrificial layer is formed on a semiconductor layer. A dielectric stack including a plurality of first dielectric layers and a plurality of second dielectric layers is formed interleaved on the first sacrificial layer. The first sacrificial layer and the plurality of second dielectric layers include different materials. A channel structure is formed extending through the dielectric stack and the first sacrificial layer in contact with the semiconductor layer. The channel structure includes a semiconductor channel and a memory film. The first sacrificial layer is removed to form a first cavity and expose a portion of the channel structure. The memory film of the portion of the channel structure exposed by the first cavity is removed to expose the semiconductor channel of the portion of the channel structure. A source select gate line is formed in the first cavity in contact with the semiconductor channel of the portion of the channel structure. The plurality of second dielectric layers are replaced with a plurality of word lines.

In some implementations, an opening is formed extending through the dielectric stack and the first sacrificial layer to expose the semiconductor layer. The first sacrificial layer is removed through the opening to form the first cavity and expose the portion of the channel structure.

In some implementations, the memory film of the portion of the channel structure are removed through the opening and the first cavity to expose the semiconductor channel of the portion of the channel structure.

In some implementations, a third dielectric layer is formed on sidewalls of the opening and the first cavity. A first conductive layer is formed on the third dielectric layer. The first conductive layer and the third dielectric layer on sidewalls of the opening are removed.

In some implementations, the third dielectric layer is in contact with the semiconductor channel of the portion of the channel structure.

In some implementations, a fourth dielectric layer is formed on the first conductive layer exposed by the opening. The plurality of second dielectric layers are removed to form a plurality of second cavities. The plurality of word lines are formed in the plurality of second cavities. A slit structure is formed in the opening.

In some implementations, a second sacrificial layer is formed on the first sacrificial layer. The first sacrificial layer and the second sacrificial layer include different materials. In some implementations, the second sacrificial layer and the plurality of second dielectric layers include different materials.

In some implementations, the channel structure extends through the dielectric stack and the second sacrificial layer in contact with the first sacrificial layer.

Although specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. As such, other configurations and arrangements can be used without departing from the scope of the present disclosure. Also, the present disclosure can also be employed in a variety of other applications. Functional and structural features as described in the present disclosures can be combined, adjusted, and modified with one another and in ways not specifically depicted in the drawings, such that these combinations, adjustments, and modifications are within the scope of the present disclosure.

In general, terminology may be understood at least in part from usage in context. For example, the term “one or more” as used herein, depending at least in part upon context, may be used to describe any feature, structure, or characteristic in a singular sense or may be used to describe combinations of features, structures or characteristics in a plural sense. Similarly, terms, such as “a,” “an,” or “the,” again, may be understood to convey a singular usage or to convey a plural usage, depending at least in part upon context. In addition, the term “based on” may be understood as not necessarily intended to convey an exclusive set of factors and may, instead, allow for existence of additional factors not necessarily expressly described, again, depending at least in part on context.

It should be readily understood that the meaning of “on,” “above,” and “over” in the present disclosure should be interpreted in the broadest manner such that “on” not only means “directly on” something but also includes the meaning of “on” something with an intermediate feature or a layer therebetween, and that “above” or “over” not only means the meaning of “above” or “over” something but can also include the meaning it is “above” or “over” something with no intermediate feature or layer therebetween (i.e., directly on something).

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper,” and the like, may be used herein for ease of description to describe one element or feature’s relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may likewise be interpreted accordingly.

As used herein, the term “substrate” refers to a material onto which subsequent material layers are added. The substrate itself can be patterned. Materials added on top of the substrate can be patterned or can remain unpatterned. Furthermore, the substrate can include a wide array of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made from an electrically non-conductive material, such as a glass, a plastic, or a sapphire wafer.

As used herein, the term “layer” refers to a material portion including a region with a thickness. A layer can extend over the entirety of an underlying or overlying structure or may have an extent less than the extent of an underlying or overlying structure. Further, a layer can be a region of a homogeneous or inhomogeneous continuous structure that has a thickness less than the thickness of the continuous structure. For example, a layer can be located between any pair of horizontal planes between, or at, a top surface and a bottom surface of the continuous structure. A layer can extend horizontally, vertically, and/or along a tapered surface. A substrate can be a layer, can include one or more layers therein, and/or can have one or more layers thereupon, thereabove, and/or therebelow. A layer can include multiple layers. For example, an interconnect layer can include one or more conductors and contact layers (in which interconnect lines and/or vertical interconnect access (via) contacts are formed) and one or more dielectric layers.

3 As used herein, the term “D memory device” refers to a semiconductor device with vertically oriented strings of memory cell transistors (referred to herein as “memory strings,” such as NAND memory strings) on a laterally-oriented substrate so that the memory strings extend in the vertical direction with respect to the substrate. As used herein, the term “vertical/vertically” means nominally perpendicular to the lateral surface of a substrate.

3 3 In someD memory devices, such asD NAND memory devices, a stack of gate electrodes may be arranged over a substrate, with a plurality of semiconductor channels through and intersecting word lines, into the implanted substrate. The bottom/lower gate electrode or electrodes function as source select gate lines, which are also called bottom select gates (BSG) in some cases. The top/upper gate electrode or electrodes function as drain select gate lines, which are also called top select gates (TSG) in some cases. The gate electrodes between the top/upper select gate electrodes and the bottom/lower gate electrodes function as word lines (WLs). The intersection of a word line and a semiconductor channel forms a memory cell.

2 3 3 With the development of artificial intelligence (AI), big data, Internet of Things (IoT), mobile communication, mobile equipment and cloud storage, the NAND memory has gradually become a mainstream semiconductor memory. The conventional two-dimensional (D) NAND memory has reached its limitation and therefore theD NAND memory developed in the longitudinal direction has been developed. However, how to increase the storage capacity of theD NAND memory within the same semiconductor size is a problem that needs to be solved. The current practice is to increase the effective storage layers and the number of insulating layers in the longitudinal direction. The challenge is the difficulties of fabricating the staircase, the channel hole, the gate line slit, or even the oxide-nitride-oxide deposition in the increased layers.

3 Another challenge is the source select gate line structure. When the source select gate line contacts the channel structure with the oxide-nitride-oxide structures, the electric charge may be trimmed or erased frequently, and the reliability and durability of theD NAND memory will be affected.

To address one or more of the aforementioned issues, the present disclosure introduces a solution in which the source select gate line may be formed like the complementary metal-oxide-semiconductor (CMOS) structure to avoid the trimming operation. Moreover, consistent with the scope of the present disclosure, a sacrificial layer is formed under the effective storage layers, and when forming the channel hole, the gate line slit, or the contact, the sacrificial layer could be a etch stop layer to precisely control the etch process.

1 FIG. 3 100 3 100 152 154 152 152 154 156 illustrates a side view of a cross-section of an exemplaryD memory device, according to some aspects of the present disclosure. In some implementations,D memory deviceis a bonded chip including a first semiconductor structureand a second semiconductor structurestacked over first semiconductor structure. First and second semiconductor structuresandare jointed at a bonding interfacetherebetween, according to some implementations.

1 FIG. 152 158 152 3 100 160 158 As shown in, first semiconductor structurecan include a substrate, which can include silicon (e.g., single crystalline silicon, c-Si), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), or any other suitable materials. First semiconductor structureofD memory devicemay include peripheral circuitson substrate.

1 FIG. 3 100 158 3 100 158 It is noted that x and y axes are included into further illustrate the spatial relationship of the components inD memory device. Substrateincludes two lateral surfaces (e.g., a top surface and a bottom surface) extending laterally in the x-direction (i.e., the lateral direction). As used herein, whether one component (e.g., a layer or a device) is on, above, or below another component (e.g., a layer or a device) of a semiconductor device (e.g.,D memory device) is determined relative to the substrate of the semiconductor device (e.g., substrate) in the y-direction (i.e., the vertical direction) when the substrate is positioned in the lowest plane of the semiconductor device in the y-direction. The same notion for describing spatial relationships is applied throughout the present disclosure.

160 3 100 160 3 100 160 158 158 158 158 158 160 In some implementations, peripheral circuitis configured to control and senseD memory device. Peripheral circuitmay be any suitable digital, analog, and/or mixed-signal control and sensing circuits used for facilitating the operation ofD memory deviceincluding, but not limited to, a page buffer, a decoder (e.g., a row decoder and a column decoder), a sense amplifier, a driver (e.g., a word line driver), a charge pump, a current or voltage reference, or any active or passive components of the circuit (e.g., transistors, diodes, resistors, or capacitors). Peripheral circuitmay include transistors formed on substrate, in which the entirety or part of the transistors are formed in substrate(e.g., below the top surface of substrate) and/or directly on substrate. Isolation regions (e.g., shallow trench isolations (STIs)) and doped regions (e.g., source regions and drain regions of the transistors) can be formed in substrateas well. The transistors are high-speed with advanced logic processes (e.g., technology nodes of 90 nm, 65 nm, 45 nm, 32 nm, 28 nm, 20 nm, 16 nm, 14 nm, 10 nm, 7 nm, 5 nm, 3 nm, 2 nm, etc.), according to some implementations. It is understood that in some implementations, peripheral circuitmay further include any other circuits compatible with the advanced logic processes including logic circuits, such as processors and programmable logic devices (PLDs), or memory circuits, such as static random-access memory (SRAM) and dynamic RAM (DRAM).

152 3 100 160 160 In some implementations, first semiconductor structureofD memory devicefurther includes an interconnect layer (not shown) above peripheral circuitsto transfer electrical signals to and from peripheral circuits. The interconnect layer can include a plurality of interconnects (also referred to herein as contacts), including lateral interconnect lines and vertical interconnect access (VIA) contacts. As used herein, the term interconnects can broadly include any suitable types of interconnects, such as middle-end-of-line (MEOL) interconnects and back-end-of-line (BEOL) interconnects. The interconnect layer can further include one or more interlayer dielectric (ILD) layers (a.k.a. intermetal dielectric (IMD) layers) in which the interconnect lines and VIA contacts can form. That is, the interconnect layer can include interconnect lines and VIA contacts in multiple ILD layers. The interconnect lines and VIA contacts in the interconnect layer can include conductive materials including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicides, or any combination thereof. The ILD layers in the interconnect layer can include dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low dielectric constant (low-k) dielectrics, or any combination thereof.

154 152 156 156 Second semiconductor structuremay be bonded on top of first semiconductor structurein a face-to-face manner at bonding interface. In some implementations, bonding interfaceis disposed as a result of hybrid bonding (also known as “metal/dielectric hybrid bonding”), which is a direct bonding technology (e.g., forming bonding between surfaces without using intermediate layers, such as solder or adhesives) and may obtain metal-metal bonding and dielectric-dielectric bonding simultaneously.

154 3 100 156 In some implementations, second semiconductor structureofD memory devicefurther includes an interconnect layer (not shown) above bonding interfaceto transfer electrical signals. The interconnect layer can include a plurality of interconnects, such as MEOL interconnects and BEOL interconnects. The interconnect layer can further include one or more ILD layers in which the interconnect lines and VIA contacts can form. The interconnect lines and VIA contacts in the interconnect layer can include conductive materials including, but not limited to W, Co, Cu, Al, silicides, or any combination thereof. The ILD layers in the interconnect layer can include dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

3 100 112 112 118 110 118 110 122 118 110 122 3 100 122 118 110 1 FIG. In some implementations,D memory deviceis a NAND Flash memory device in which memory cells are provided in the form of an array of NAND memory strings. Each NAND memory string can include a respective channel structure. As shown in, each channel structuremay extend vertically through a plurality of pairs including interleaved conductive layersand first dielectric layers. The interleaved conductive layersand first dielectric layersare part of a memory stack. The number of the pairs of conductive layersand first dielectric layersin memory stackdetermines the number of memory cells inD memory device. It is understood that in some implementations, memory stackmay have a multi-deck architecture (not shown), which includes a plurality of memory decks stacked over one another. The numbers of the pairs of conductive layersand first dielectric layersin each memory deck can be the same or different.

122 118 110 118 110 122 122 118 110 110 118 118 118 118 122 110 Memory stackcan include a plurality of interleaved conductive layersand first dielectric layers. Conductive layersand first dielectric layersin memory stackmay alternate in the vertical direction. In other words, except the ones at the top or bottom of memory stack, each conductive layercan be adjoined by two first dielectric layerson both sides, and each first dielectric layercan be adjoined by two conductive layerson both sides. Conductive layerscan include conductive materials including, but not limited to, W, Co, Cu, Al, polysilicon, doped silicon, silicides, or any combination thereof. Each conductive layercan include a gate electrode (gate line) surrounded by an adhesive layer and a gate dielectric layer. The gate electrode of conductive layercan extend laterally as a word line, ending at one or more staircase structures of memory stack. First dielectric layerscan include dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

112 113 115 115 117 112 117 113 115 115 113 115 113 122 1 FIG. 1 FIG. In some implementations, each channel structureincludes a channel hole filled with a semiconductor channeland a composite dielectric film(also referred to herein as “memory film”). As shown in, the remaining space of the channel hole can be partially filled with a capping layerincluding dielectric materials, such as silicon oxide, and/or an air gap. Channel structurecan have a cylinder shape (e.g., a pillar shape). Capping layer, semiconductor channel, and composite dielectric filmare arranged radially from the center toward the outer surface of the pillar in this order, according to some implementations. Composite dielectric filmcan radially circumscribe semiconductor channelalong the lateral direction (e.g., the x-direction in). Composite dielectric filmcan be formed laterally between semiconductor channeland memory stack.

112 162 162 608 610 608 610 In some implementations, channel structuremay further extend vertically through one or more than one source select gate line, which may also be called a bottom select gate (BSG) line in some cases. In some implementations, source select gate linemay be formed by a source select gate dielectric layerand a source select gate conductive layer. In some implementations, an adhesive layer (not shown) may be further formed between source select gate dielectric layerand source select gate conductive layer.

610 608 608 112 608 113 112 608 610 162 610 608 1 FIG. In some implementations, source select gate conductive layermay be made from tungsten, the adhesion layer may include titanium/titanium nitride (Ti/TiN) or tantalum/tantalum nitride (Ta/TaN), and source select gate dielectric layermay be made from high-k dielectric materials. As shown in, source select gate dielectric layerdirectly contacts channel structure. Specifically, source select gate dielectric layerdirectly contacts semiconductor channelof channel structure. The adhesion layer may locate inside and in contact with source select gate dielectric layer, and source select gate conductive layerlocates inside and in contact with the adhesion layer. In some implementations, source select gate linemay include source select gate conductive layer, the adhesion layer, and source select gate dielectric layer.

610 610 118 In some implementations, source select gate conductive layermay include polysilicon material. In the situation that source select gate conductive layeris formed by the same material, e.g., W, with word lines (conductive layers), the threshold voltage (Vt) of the BSG transistor may have a shift in some working modes or under some voltage arrangements. For example, if a high voltage applied to the NAND memory string or the memory device is operated at a high temperature during the program/erase cycling, the threshold voltage (Vt) of the BSG transistor may have a shift. By forming the source select gate line like the CMOS structure, the induced threshold voltage (Vt) shift of BSG transistor can be improved.

610 608 In some implementations, source select gate conductive layermay be formed by other suitable conductive materials. In some implementations, source select gate dielectric layermay be formed by high dielectric constant (high-k) materials.

1 FIG. 154 3 100 612 122 113 112 612 612 As shown in, second semiconductor structureofD memory devicecan also include a doped semiconductor layerabove memory stack. In some implementations, semiconductor channelof channel structuremay be in contact with doped semiconductor layer. In some implementations, doped semiconductor layermay include polysilicon, high-k dielectric, or a metal. For example, a high-k dielectric may include any dielectric materials having a dielectric constant (k) higher than that of silicon oxide (e.g., k > 3.7).

112 118 110 122 162 612 113 112 612 Each channel structuremay extend vertically through interleaved conductive layersand first dielectric layersof memory stack, and source select gate line, and in contact with doped semiconductor layer. In some implementations, semiconductor channelat the source end of channel structuremay be exposed and in direct contact with doped semiconductor layer.

614 612 112 614 In some implementations, an interconnection structuremay be formed on doped semiconductor layer. The source end of channel structuremay be coupled to interconnection structurethrough a source contact.

2 7 FIGS.- 8 FIG. 2 7 FIGS.- 8 FIG. 2 7 FIGS.- 8 FIG. 3 200 300 3 200 3 200 300 300 illustrate a fabrication process for forming an exemplaryD memory device, according to some aspects of the present disclosure.illustrates a flowchart of an exemplary methodfor formingD memory device, according to some aspects of the present disclosure. For the purpose of better describing the present disclosure, the cross-sections ofD memory deviceinand methodinwill be discussed together. It is understood that the operations shown in methodare not exhaustive and that other operations may be performed as well before, after, or between any of the illustrated operations. Further, some of the operations may be performed simultaneously, or in a different order than shown inand.

2 FIG. 8 FIG. 302 104 102 102 102 104 102 As shown inand operationof, a first sacrificial layeris formed on a semiconductor layer. In some implementations, semiconductor layermay be a carrier substrate. In some implementations, the carrier substrate may be a doped semiconductor layer. In some implementations, a pad oxide layer may be formed between semiconductor layerand first sacrificial layerby depositing dielectric materials, such as silicon oxide, on semiconductor layer.

104 104 104 In some implementations, first sacrificial layermay include polysilicon, high-k dielectric, or metal. In some implementations, first sacrificial layermay include tungsten. First sacrificial layermay act as an etch stop layer when forming the channel structure, the dummy channel structure, the gate line slit structure, and/or the contact structure in a later operation.

2 FIG. 8 FIG. 304 106 110 108 104 104 108 106 110 108 110 108 106 Then, as shown inand operationof, a dielectric stackincluding interleaved first dielectric layersand second dielectric layersis formed on first sacrificial layer. First sacrificial layerand second dielectric layersare formed by different materials. The dielectric stackincludes interleaved first dielectric layersand second dielectric layersextending in the x-direction. In some implementations, each first dielectric layermay include silicon oxide, and each second dielectric layermay include silicon nitride. Dielectric stackmay be formed by one or more thin film deposition processes including, but not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

3 FIG. 8 FIG. 306 112 106 104 112 113 115 As shown inand operationof, channel structureis formed extending vertically through dielectric stackin contact with first sacrificial layer. Channel structureincludes semiconductor channeland memory film.

3 FIG. 3 FIG. 106 106 106 106 As illustrated in, a staircase structure is formed on the edge of dielectric stack. The staircase structure may be formed by performing a plurality of so-called “trim-etch” cycles to the dielectric layer pairs of dielectric stack. Due to the repeated trim-etch cycles applied to the dielectric layer pairs of dielectric stack, dielectric stackcan have one or more tilted edges and a top dielectric layer pair shorter than the bottom one, as shown in.

112 106 104 112 113 115 113 112 106 104 Channel structureis formed extending vertically through dielectric stackin contact with first sacrificial layer. Channel structureincludes semiconductor channel, and memory film, including a third dielectric layer, a fourth dielectric layer, and a fifth dielectric layer, over semiconductor channel. Here, “over” not only means the meaning of above something but can also include the meaning it is laterally on something with no intermediate feature or layer therebetween. In some implementations, to form channel structure, a channel hole extending through dielectric stackis formed, stopping at first sacrificial layer.

113 The third dielectric layer, the fourth dielectric layer, the fifth dielectric layer, and semiconductor channelare sequentially formed in the channel hole. In some implementations, the fourth dielectric layer includes a dielectric material different from the third and fifth dielectric layers. For example, the fourth dielectric layer may include silicon nitride, and the third and fifth dielectric layers may include silicon oxide.

106 104 112 112 104 104 112 104 104 Each channel hole is an opening extending vertically through and beyond dielectric stack, stopping at first sacrificial layer. In some implementations, a plurality of openings are formed, such that each opening becomes the location for growing an individual channel structurein the later process. In some implementations, fabrication processes for forming the channel holes of channel structuresinclude wet etching and/or dry etching, such as deep RIE (DRIE). The etching of the channel holes continues until being stopped by first sacrificial layer, such as silicon oxide or polysilicon, according to some implementations. In some implementations, the etching conditions, such as etching rate and time, can be controlled to ensure that each channel hole has reached and stopped by first sacrificial layerto minimize the gouging variations among the channel holes and channel structuresformed therein. It is understood that depending on the specific etching selectivity, one or more channel holes may extend into first sacrificial layerto a small extent, which is still viewed as being stopped by first sacrificial layerin the present disclosure.

115 113 115 113 115 115 113 Memory film(the third dielectric layer, the fourth dielectric layer, and the fifth dielectric layer), and semiconductor channelare sequentially formed in this order along sidewalls and the bottom surface of the channel hole. In some implementations, memory filmis first deposited along the sidewalls and bottom surface of the channel hole using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof. Semiconductor channelthen may be formed by depositing a semiconductor material, such as polysilicon (e.g., undoped polysilicon), over memory filmusing one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof. In some implementations, a first silicon oxide layer, a silicon nitride layer, a second silicon oxide layer, and a polysilicon layer (a “ONOP” structure) are sequentially deposited to form memory filmand semiconductor channel.

117 113 117 114 106 104 Capping layermay be formed in the channel hole and over semiconductor channelto fully or partially fill the channel hole (e.g., without or with an air gap). Capping layercan be formed by depositing a dielectric material, such as silicon oxide, using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof. A channel plug can then be formed in the top portion of the channel hole. In some implementations, one or more than one dummy channel structuremay also be formed extending vertically through dielectric stackin contact with first sacrificial layer.

3 FIG. 116 106 104 116 116 108 As illustrated in, an openingmay be formed extending vertically through dielectric stackand expose first sacrificial layer. In some implementations, fabrication processes for forming openinginclude wet etching and/or dry etching, such as DRIE. A gate replacement then can be performed through openingto replace second dielectric layerswith word lines in a later operation.

4 FIG. 8 FIG. 308 108 108 116 108 116 110 108 110 108 104 As shown inand operationof, the plurality of second dielectric layersare replaced with a plurality of word lines. In some implementations, a plurality of cavities may be first formed by removing second dielectric layersthrough opening. In some implementations, second dielectric layersare removed by applying etchants through opening, creating cavities interleaved between first dielectric layers. The etchants can include any suitable etchants that etch second dielectric layersselective to first dielectric layers. Furthermore, the etchants can include any suitable etchants that etch second dielectric layersselective to first sacrificial layer.

118 116 118 118 118 116 122 118 110 106 Then, the word lines (including conductive layersand adhesive layers) are deposited into the cavities through opening. In some implementations, a gate dielectric layer is deposited into the cavities prior to conductive layers, such that conductive layersare deposited on the gate dielectric layer. Conductive layers, such as metal layers, can be deposited using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof. In some implementations, the gate dielectric layer, such as a high-k dielectric layer, is formed along the sidewall and at the bottom of openingas well. Memory stackincluding interleaved conductive layersand first dielectric layersis thereby formed, replacing dielectric stack, according to some implementations.

162 122 104 162 118 162 118 In some implementations, one or more than one source select gate linemay be formed between memory stackand first sacrificial layer. In some implementations, source select gate linemay have the same structure as conductive layersand may be formed in the same processes. In some implementations, source select gate lineand conductive layersmay have different structures.

124 122 104 124 116 116 124 116 116 124 124 124 A slit structureextending vertically through memory stackis formed, stopping on first sacrificial layer. Slit structuremay be formed by depositing one or more dielectric materials, such as silicon oxide, into openingto fully or partially fill opening(with or without an air gap) using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof. In some implementations, slit structureincludes the gate dielectric layer (e.g., including high-k dielectrics) and a dielectric capping layer (e.g., including silicon oxide). In some implementations, the dielectric capping layer may partially fill opening, and a polysilicon core layer may fill the remaining space of openingas part of slit structureto adjust the mechanical properties, such as hardness or stress, of slit structure. After the formation of slit structure, local contacts, including channel local contacts, word line local contacts, and peripheral contacts may be formed. A bonding layer may be formed above channel local contacts, word line local contacts, and peripheral contacts.

5 FIG. 122 130 102 122 112 122 112 130 130 As shown in, a wafer bonding operation may be performed, such that memory stackis above a peripheral circuit structure. The bonding can include hybrid bonding. In some implementations, semiconductor layerand components formed thereon (e.g., memory stackand channel structuresformed therethrough) are flipped upside down. After the bonding, memory stackand channel structuresformed therethrough can be electrically connected to the peripheral circuits in peripheral circuit structureand are above peripheral circuit structure.

6 FIG. 8 FIG. 310 102 104 112 102 102 104 102 102 As shown inand operationin, semiconductor layerand first sacrificial layerare removed to expose a portion of channel structure. In some implementations, the removal may be performed from the backside of semiconductor layer. In some implementations, semiconductor layer(the carrier substrate) may be first removed, stopping at first sacrificial layer. In some implementations, semiconductor layermay be completely removed using chemical-mechanical polishing (CMP), grinding, dry etching, and/or wet etching. In some implementations, semiconductor layermay be peeled off.

104 112 104 113 112 Then, first sacrificial layermay be completely removed as well using wet etching with suitable etchants, such as phosphoric acid and hydrofluoric acid. In some implementations, part of channel structureextending into first sacrificial layeris removed, such that semiconductor channelat the upper end (the source end) of channel structureis exposed.

6 FIG. 8 FIG. 312 112 132 122 113 132 122 113 132 122 113 132 As shown inand operationin, a conductive layer is formed over channel structure. A doped semiconductor layeris formed on memory stackcovering the exposed semiconductor channel. In some implementations, to form doped semiconductor layer, a semiconductor layer (e.g., polysilicon) may be deposited on memory stackin contact with the exposed semiconductor channelusing one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof. The deposited semiconductor layer can be doped with N-type dopant(s), such as P, As, or Sb, using ion implantation and/or thermal diffusion. In some implementations, to form doped semiconductor layer, in-situ doping of N-type dopants, such as P, As, or Sb, is performed when depositing the semiconductor layer on memory stackcovering the exposed semiconductor channel. In some implementations, a CMP process may be further performed to remove any excess doped semiconductor layeras needed.

132 113 132 132 113 132 113 132 132 113 132 19 -3 21 -3 In some implementations, doped semiconductor layerand the part of semiconductor channelthat is in contact with doped semiconductor layerare locally activated. In some implementations, to locally activate, heat is applied in a confined area having doped semiconductor layerand the part of semiconductor channelto activate dopants in doped semiconductor layerand the part of semiconductor channel. The confined area can be between the stack structure and doped semiconductor layer. In some implementations, the doping concentration of doped semiconductor layerand the doping concentration of the part of semiconductor channelin contact with doped semiconductor layereach is between 10cmand 10cmafter the activation.

132 113 132 The local activation process can activate the dopants such that the dopants can occupy the silicon lattices to reduce the contact resistance between doped semiconductor layerand semiconductor channelas well as to reduce the sheet resistance of doped semiconductor layer. On the other hand, by confining the heat during the local activation process into an area without heat-sensitive structures, any potential damages to the heat-sensitive structures, such as the bonding interface and Cu interconnects used for connecting the peripheral circuits, can be reduced or avoided.

7 FIG. 132 134 132 134 132 112 As shown in, a source contact is formed in contact with doped semiconductor layer. In some implementations, an interconnection structuremay be formed on doped semiconductor layer. Interconnection structuremay include one or more ILD layers on doped semiconductor layerand a redistribution layer on the ILD layers. The source end of channel structuremay be coupled to the redistribution layer through the source contact.

9 17 FIGS.- 18 FIG. 9 17 FIGS.- 18 FIG. 9 17 FIGS.- 18 FIG. 3 400 500 3 400 3 400 500 500 illustrate a fabrication process for forming another exemplaryD memory device, according to some aspects of the present disclosure.illustrates a flowchart of another exemplary methodfor formingD memory device, according to some aspects of the present disclosure. For the purpose of better describing the present disclosure, the cross-sections ofD memory deviceinand methodinwill be discussed together. It is understood that the operations shown in methodare not exhaustive and that other operations may be performed as well before, after, or between any of the illustrated operations. Further, some of the operations may be performed simultaneously, or in a different order than shown inand.

9 FIG. 18 FIG. 502 402 102 102 102 402 102 402 402 As shown inand operationof, a second sacrificial layeris formed on semiconductor layer. In some implementations, semiconductor layermay be a carrier substrate. In some implementations, the carrier substrate may be a doped semiconductor layer. In some implementations, an oxide layer may be formed between semiconductor layerand second sacrificial layerby depositing dielectric materials, such as silicon oxide, on semiconductor layer. In some implementations, second sacrificial layermay include polysilicon, high-k dielectric, or metal. Second sacrificial layermay be used for forming the source select gate line in a later operation.

9 FIG. 18 FIG. 504 106 110 108 402 402 108 106 110 108 110 108 106 Then, as shown inand operationof, dielectric stackincluding first dielectric layersand second dielectric layersis formed on second sacrificial layer. Second sacrificial layerand second dielectric layersare formed by different materials. The dielectric stackincludes interleaved first dielectric layersand second dielectric layersextending in the x-direction. In some implementations, each first dielectric layermay include silicon oxide, and each second dielectric layersmay include silicon nitride. Dielectric stackmay be formed by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof.

10 FIG. 18 FIG. 506 112 106 112 113 115 As shown inand operationof, channel structureis formed extending vertically through dielectric stackand sacrificial layer. Channel structureincludes semiconductor channeland memory film.

10 FIG. 10 FIG. 106 402 106 402 106 106 As illustrated in, a staircase structure is formed on the edge of dielectric stackand second sacrificial layer. The staircase structure may be formed by performing a plurality of so-called “trim-etch” cycles to the dielectric layer pairs of dielectric stackand second sacrificial layer. Due to the repeated trim-etch cycles applied to the dielectric layer pairs of dielectric stack, dielectric stackcan have one or more tilted edges and a top dielectric layer pair shorter than the bottom one, as shown in.

112 106 402 112 113 115 113 112 106 402 Channel structureis formed extending vertically through dielectric stackand second sacrificial layer. Channel structureincludes semiconductor channel, and memory film, including the third dielectric layer, the fourth dielectric layer, and the fifth dielectric layer, over semiconductor channel. In some implementations, to form channel structure, a channel hole extending through dielectric stackand second sacrificial layeris formed.

113 The third dielectric layer, the fourth dielectric layer, and the fifth dielectric layer may be the blocking layer, the storage layer, and the tunneling layer. The blocking layer, the storage layer, the tunneling layer, and semiconductor channelare sequentially formed in the channel hole. In some implementations, the fourth dielectric layer includes a dielectric material different from the third and fifth dielectric layers. For example, the fourth dielectric layer may include silicon nitride, and the third and fifth dielectric layers may include silicon oxide.

106 402 112 112 Each channel hole is an opening extending vertically through and beyond dielectric stackand second sacrificial layer. In some implementations, a plurality of openings are formed, such that each opening becomes the location for growing an individual channel structurein the later process. In some implementations, fabrication processes for forming the channel holes of channel structuresinclude wet etching and/or dry etching, such as DRIE.

115 113 115 113 115 115 113 Memory film(the third dielectric layer, the fourth dielectric layer, and the fifth dielectric layer), and semiconductor channelare sequentially formed in this order along sidewalls and the bottom surface of the channel hole. In some implementations, memory filmis first deposited along the sidewalls and bottom surface of the channel hole using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof. Semiconductor channelthen may be formed by depositing a semiconductor material, such as polysilicon (e.g., undoped polysilicon), over memory filmusing one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof. In some implementations, a first silicon oxide layer, a silicon nitride layer, a second silicon oxide layer, and a polysilicon layer (a “ONOP” structure) are sequentially deposited to form memory filmand semiconductor channel.

117 113 117 114 106 402 Capping layermay be formed in the channel hole and over semiconductor channelto fully or partially fill the channel hole (e.g., without or with an air gap). Capping layercan be formed by depositing a dielectric material, such as silicon oxide, using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof. A channel plug can then be formed in the top portion of the channel hole. In some implementations, one or more than one dummy channel structuremay also be formed extending vertically through dielectric stackand second sacrificial layer.

10 FIG. 116 106 402 116 As illustrated in, openingmay be formed extending vertically through dielectric stackand second sacrificial layer. In some implementations, fabrication processes for forming openinginclude wet etching and/or dry etching, such as DRIE.

11 FIG. 18 FIG. 508 402 404 112 402 As illustrated inand operationin, second sacrificial layeris removed to form a cavityand expose a portion of channel structure. In some implementations, second sacrificial layermay be a polysilicon layer or a silicon nitride layer and may be removed by wet etch, dry etch, or other suitable processes.

12 FIG. 18 FIG. 510 112 115 112 404 113 508 510 402 404 115 404 508 510 Then, as shown inand operationin, a portion of sidewalls of channel structureis removed. Specifically, memory film, including the tunneling layer, the storage layer, and the blocking layer, on sidewalls of channel structureexposed to cavityis removed until exposing semiconductor channel. It is understood operationand operationmay be performed in one etch operation. For example, the etching operation may first remove second sacrificial layerto form cavityand then remove memory filmexposed to cavity. In some implementations, operationand operationmay be performed in different etching processes.

13 FIG. 14 FIG. 18 FIG. 13 FIG. 14 FIG. 512 404 113 112 408 406 404 116 406 113 406 406 408 406 404 116 408 As shown inand, and operationin, a source select gate line is formed in cavityin direct contact with semiconductor channelof channel structure. In some implementations, the formation of source select gate linemay include firstly forming dielectric layeron the sidewalls of cavityand opening, as shown in. Dielectric layerdirectly contacts semiconductor channel. In some implementations, dielectric layermay include silicon oxide and may be formed by ALD, PVD, CVD, or other suitable processes. In some implementations, dielectric layermay include silicon nitride, high-k dielectric materials, or other suitable materials. Then, source select gate lineis formed on dielectric layerin cavityand opening, as shown in. In some implementations, source select gate linemay include polysilicon. For example, the polysilicon layer may be formed by the atmospheric pressure CVD (APCVD) process to form in-situ n+ doped polysilicon.

15 FIG. 406 408 116 106 406 408 116 106 Then, as shown in, partials of dielectric layerand source select gate lineformed on sidewalls of openingand on dielectric stackare removed. In some implementations, partials of dielectric layerand source select gate lineformed on sidewalls of openingand on dielectric stackmay be removed by dry etch, wet etch, or other suitable processes.

15 FIG. 408 406 408 116 408 108 118 408 108 illustrates that source select gate lineinclude polysilicon. However, in some other implementations, after removing dielectric layerand source select gate lineformed on sidewalls of opening, source select gate lineand second dielectric layersmay be removed in the later processes. Then conductive layersmay be used to replace source select gate lineand second dielectric layers. In other words, in some other implementations, the word lines and the source select gate line may be formed by the same material, e.g., tungsten.

16 FIG. 410 408 116 410 408 410 408 116 410 408 116 408 116 410 As shown in, a dielectric layermay be formed on source select gate lineexposed to opening. In some implementations, dielectric layermay be used to protect source select gate lineduring a later word line replacement operation. In some implementations, dielectric layermay be formed by depositing a dielectric material onto source select gate lineexposed to opening. In some implementations, dielectric layermay be formed by performing an oxidation operation on source select gate lineexposed to openingto oxidate the surface of source select gate lineexposed to openingto dielectric layer.

17 FIG. 18 FIG. 514 108 108 116 108 116 110 108 110 408 410 408 514 As shown inand operationin, the plurality of second dielectric layersare replaced with a plurality of word lines. In some implementations, a plurality of cavities may be first formed by removing second dielectric layersthrough opening. In some implementations, second dielectric layersare removed by applying etchants through opening, creating cavities interleaved between first dielectric layers. The etchants can include any suitable etchants that etch second dielectric layersselective to first dielectric layers. Since source select gate lineis covered by dielectric layer, source select gate linewill not be removed in operation.

118 116 118 118 118 116 122 118 110 106 Then, the word lines (including conductive layersand adhesive layers) are deposited into the cavities through opening. In some implementations, a gate dielectric layer is deposited into the cavities prior to conductive layers, such that conductive layersare deposited on the gate dielectric layer. Conductive layers, such as metal layers, can be deposited using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof. In some implementations, the gate dielectric layer, such as a high-k dielectric layer, is formed along the sidewall and at the bottom of openingas well. Memory stackincluding interleaved conductive layersand first dielectric layersis thereby formed, replacing dielectric stack, according to some implementations.

124 122 124 116 116 124 116 116 124 124 Slit structureextending vertically through memory stackis formed. Slit structuremay be formed by depositing one or more dielectric materials, such as silicon oxide, into openingto fully or partially fill opening(with or without an air gap) using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof. In some implementations, slit structureincludes the gate dielectric layer (e.g., including high-k dielectrics) and a dielectric capping layer (e.g., including silicon oxide). In some implementations, the dielectric capping layer may partially fill opening, and a polysilicon core layer may fill the remaining space of openingas part of slit structureto adjust the mechanical properties, such as hardness or stress, of slit structure.

19 30 FIGS.- 31 FIG. 19 30 FIGS.- 31 FIG. 19 30 FIGS.- 31 FIG. 3 600 700 3 600 3 600 700 700 illustrate a fabrication process for forming an exemplaryD memory device, according to some aspects of the present disclosure.illustrates a flowchart of an exemplary methodfor formingD memory device, according to some aspects of the present disclosure. For the purpose of better describing the present disclosure, the cross-sections ofD memory deviceinand methodinwill be discussed together. It is understood that the operations shown in methodare not exhaustive and that other operations may be performed as well before, after, or between any of the illustrated operations. Further, some of the operations may be performed simultaneously, or in a different order than shown inand.

19 FIG. 31 FIG. 702 602 102 102 102 602 102 As shown inand operationof, a third sacrificial layeris formed on semiconductor layer. In some implementations, semiconductor layermay be a carrier substrate. In some implementations, the carrier substrate may be a doped semiconductor layer. In some implementations, a pad oxide layer may be formed between semiconductor layerand third sacrificial layerby depositing dielectric materials, such as silicon oxide, on semiconductor layer.

602 602 602 In some implementations, third sacrificial layermay include polysilicon, high-k dielectric, or metal. In some implementations, third sacrificial layermay include tungsten. Third sacrificial layermay act as an etch stop layer when forming the channel structure, the dummy channel structure, the gate line slit structure, and/or the contact structure in a later operation.

19 FIG. 31 FIG. 704 604 602 602 604 604 604 As shown inand operationof, a fourth sacrificial layeris formed on third sacrificial layer. Third sacrificial layerand fourth sacrificial layermay be formed by different materials. In some implementations, fourth sacrificial layermay include polysilicon, high-k dielectric, or metal. Fourth sacrificial layermay be used for forming the source select gate line in a later operation.

19 FIG. 31 FIG. 706 106 110 108 604 604 108 106 110 108 110 108 106 Then, as shown inand operationof, dielectric stackincluding first dielectric layersand second dielectric layersis formed on fourth sacrificial layer. Fourth sacrificial layerand second dielectric layersare formed by different materials. The dielectric stackincludes interleaved first dielectric layersand second dielectric layersextending in the x-direction. In some implementations, each first dielectric layermay include silicon oxide, and each second dielectric layermay include silicon nitride. Dielectric stackmay be formed by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof.

20 FIG. 31 FIG. 708 112 106 604 602 112 113 115 As shown inand operationof, channel structureis formed extending vertically through dielectric stackand fourth sacrificial layerin contact with third sacrificial layer. Channel structureincludes semiconductor channeland memory film.

20 FIG. 20 FIG. 106 604 106 604 106 604 106 604 As illustrated in, a staircase structure is formed on the edge of dielectric stackand fourth sacrificial layer. The staircase structure may be formed by performing a plurality of so-called “trim-etch” cycles to the dielectric layer pairs of dielectric stackand fourth sacrificial layer. Due to the repeated trim-etch cycles applied to the dielectric layer pairs of dielectric stackand fourth sacrificial layer, dielectric stackand fourth sacrificial layercan have one or more tilted edges and a top dielectric layer pair shorter than the bottom one, as shown in.

112 106 604 602 112 113 115 113 112 106 604 602 Channel structureis formed extending vertically through dielectric stackand fourth sacrificial layerin contact with third sacrificial layer. Channel structureincludes semiconductor channel, and memory film, including the third dielectric layer, the fourth dielectric layer, and the fifth dielectric layer, over semiconductor channel. In some implementations, to form channel structure, a channel hole extending through dielectric stackand fourth sacrificial layeris formed, stopping at third sacrificial layer.

113 The third dielectric layer, the fourth dielectric layer, the fifth dielectric layer, and semiconductor channelare sequentially formed in the channel hole. In some implementations, the fourth dielectric layer includes a dielectric material different from the third and fifth dielectric layers. For example, the fourth dielectric layer may include silicon nitride, and the third and fifth dielectric layers may include silicon oxide.

106 604 602 112 112 602 602 112 602 602 Each channel hole is an opening extending vertically through and beyond dielectric stackand fourth sacrificial layer, stopping at third sacrificial layer. In some implementations, a plurality of openings are formed, such that each opening becomes the location for growing an individual channel structurein the later process. In some implementations, fabrication processes for forming the channel holes of channel structuresinclude wet etching and/or dry etching, such as DRIE. The etching of the channel holes continues until being stopped by third sacrificial layer, such as silicon oxide or polysilicon, according to some implementations. In some implementations, the etching conditions, such as etching rate and time, can be controlled to ensure that each channel hole has reached and stopped by third sacrificial layerto minimize the gouging variations among the channel holes and channel structuresformed therein. It is understood that depending on the specific etching selectivity, one or more channel holes may extend into third sacrificial layerto a small extent, which is still viewed as being stopped by third sacrificial layerin the present disclosure.

115 113 115 113 115 115 113 Memory film(the third dielectric layer, the fourth dielectric layer, and the fifth dielectric layer), and semiconductor channelare sequentially formed in this order along sidewalls and the bottom surface of the channel hole. In some implementations, memory filmis first deposited along the sidewalls and bottom surface of the channel hole using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof. Semiconductor channelthen may be formed by depositing a semiconductor material, such as polysilicon (e.g., undoped polysilicon), over memory filmusing one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof. In some implementations, a first silicon oxide layer, a silicon nitride layer, a second silicon oxide layer, and a polysilicon layer (a “ONOP” structure) are sequentially deposited to form memory filmand semiconductor channel.

117 113 117 114 106 604 602 Capping layermay be formed in the channel hole and over semiconductor channelto fully or partially fill the channel hole (e.g., without or with an air gap). Capping layercan be formed by depositing a dielectric material, such as silicon oxide, using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof. A channel plug can then be formed in the top portion of the channel hole. In some implementations, one or more than one dummy channel structuremay also be formed extending vertically through dielectric stackand fourth sacrificial layerin contact with third sacrificial layer.

20 FIG. 116 106 604 602 116 116 108 116 604 As illustrated in, openingmay be formed extending vertically through dielectric stackand fourth sacrificial layerand expose third sacrificial layer. In some implementations, fabrication processes for forming openinginclude wet etching and/or dry etching, such as DRIE. A gate replacement then can be performed through openingto replace second dielectric layerswith word lines in a later operation. In addition, a source select gate line formation operation may also be performed through openingto replace sacrificial layerswith source select gate line in a later operation.

21 FIG. 31 FIG. 710 604 606 112 604 As illustrated inand operationof, fourth sacrificial layeris removed to form a cavityand expose a portion of channel structure. In some implementations, fourth sacrificial layermay be a polysilicon layer or a silicon nitride layer and may be removed by wet etch, dry etch, or other suitable processes.

22 FIG. 31 FIG. 712 112 115 112 606 113 710 712 604 606 115 606 710 712 Then, as shown inand operationin, a portion of sidewalls of channel structureis removed. Specifically, memory film, including the tunneling layer, the storage layer, and the blocking layer, on sidewalls of channel structureexposed to cavityis removed until exposing semiconductor channel. It is understood operationand operationmay be performed in one etch operation. For example, the etching operation may first remove fourth sacrificial layerto form cavityand then continue to remove memory filmexposed to cavity. In some implementations, operationand operationmay be performed in different etching processes.

23 FIG. 24 FIG. 31 FIG. 23 FIG. 24 FIG. 714 610 606 113 112 610 608 606 116 608 113 608 608 610 608 606 116 610 As shown inand, and operationin, source select gate conductive layeris formed in cavityin direct contact with semiconductor channelof channel structure. In some implementations, the formation of source select gate conductive layermay include firstly forming source select gate dielectric layeron the sidewalls of cavityand opening, as shown in. Source select gate dielectric layerdirectly contacts semiconductor channel. In some implementations, source select gate dielectric layermay include silicon oxide and may be formed by ALD, PVD, CVD, or other suitable processes. In some implementations, source select gate dielectric layermay include silicon nitride, high-k dielectric materials, or other suitable materials. Then, source select gate conductive layeris formed on source select gate dielectric layerin cavityand opening, as shown in. In some implementations, source select gate conductive layermay be formed by polysilicon. For example, the polysilicon layer may be formed by APCVD process to form in-situ n+ doped polysilicon.

25 FIG. 608 610 116 106 608 610 116 106 Then, as shown in, partials of source select gate dielectric layerand source select gate conductive layerformed on sidewalls of openingand on dielectric stackare removed. In some implementations, partials of source select gate dielectric layerand source select gate conductive layerformed on sidewalls of openingand on dielectric stackmay be removed by dry etch, wet etch, or other suitable processes.

25 FIG. 610 608 610 116 610 108 118 610 108 illustrates that source select gate conductive layerinclude polysilicon. However, in some other implementations, after removing source select gate dielectric layerand source select gate conductive layerformed on sidewalls of opening, source select gate conductive layerand second dielectric layersmay be removed in the later processes. Then conductive layersmay be used to replace source select gate conductive layerand second dielectric layers. In other words, in some other implementations, the word lines and the source select gate line may be formed by the same material, e.g., tungsten.

26 FIG. 618 610 116 618 610 618 610 116 618 610 116 610 116 618 As shown in, a dielectric layermay be formed on source select gate conductive layerexposed to opening. In some implementations, dielectric layermay be used to protect source select gate conductive layerduring a later word line replacement operation. In some implementations, dielectric layermay be formed by depositing a dielectric material onto source select gate conductive layerexposed to opening. In some implementations, dielectric layermay be formed by performing an oxidation operation on source select gate conductive layerexposed to openingto oxidate the surface of source select gate conductive layerexposed to openingto dielectric layer.

27 FIG. 31 FIG. 716 108 118 108 116 108 116 110 108 110 108 602 610 618 610 716 As shown inand operationof, the plurality of second dielectric layersare replaced with a plurality of word lines. In some implementations, a plurality of cavities may be first formed by removing second dielectric layersthrough opening. In some implementations, second dielectric layersare removed by applying etchants through opening, creating cavities interleaved between first dielectric layers. The etchants can include any suitable etchants that etch second dielectric layersselective to first dielectric layers. Furthermore, the etchants can include any suitable etchants that etch second dielectric layersselective to third sacrificial layer. Since source select gate conductive layeris covered by dielectric layer, source select gate conductive layerwill not be removed in operation.

118 116 118 118 118 116 122 118 110 106 Then, the word lines (including conductive layersand adhesive layers) are deposited into the cavities through opening. In some implementations, a gate dielectric layer is deposited into the cavities prior to conductive layers, such that conductive layersare deposited on the gate dielectric layer. Conductive layers, such as metal layers, can be deposited using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof. In some implementations, the gate dielectric layer, such as a high-k dielectric layer, is formed along the sidewall and at the bottom of openingas well. Memory stackincluding interleaved conductive layersand first dielectric layersis thereby formed, replacing dielectric stack, according to some implementations.

124 122 602 124 116 116 124 116 116 124 124 124 A slit structureextending vertically through memory stackis formed, stopping on third sacrificial layer. Slit structuremay be formed by depositing one or more dielectric materials, such as silicon oxide, into openingto fully or partially fill opening(with or without an air gap) using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof. In some implementations, slit structureincludes the gate dielectric layer (e.g., including high-k dielectrics) and a dielectric capping layer (e.g., including silicon oxide). In some implementations, the dielectric capping layer may partially fill opening, and a polysilicon core layer may fill the remaining space of openingas part of slit structureto adjust the mechanical properties, such as hardness or stress, of slit structure. After the formation of slit structure, local contacts, including channel local contacts, word line local contacts, and peripheral contacts may be formed. A bonding layer may be formed above channel local contacts, word line local contacts, and peripheral contacts.

28 FIG. 130 122 122 130 102 122 112 130 130 122 122 112 130 130 As shown in, peripheral circuit structureand memory stackare bonded in a face-to-face manner, such that memory stackis above peripheral circuit structure. The bonding can include hybrid bonding. In some implementations, semiconductor layerand components formed thereon (e.g., memory stackand channel structuresformed therethrough) are flipped upside down. The bonding layer facing down is bonded with the bonding layer of peripheral circuit structurefacing up, i.e., in a face-to-face manner, thereby forming a bonding interface between peripheral circuit structureand memory stack. In some implementations, a treatment process, e.g., a plasma treatment, a wet treatment, and/or a thermal treatment, is applied to the bonding surfaces prior to the bonding. After the bonding, memory stackand channel structuresformed therethrough can be electrically connected to the peripheral circuits in peripheral circuit structureand are above peripheral circuit structure.

29 FIG. 31 FIG. 718 102 602 112 102 102 602 102 102 As shown inand operationin, semiconductor layerand third sacrificial layerare removed to expose a portion of channel structure. In some implementations, the removal may be performed from the backside of semiconductor layer. In some implementations, semiconductor layer(the carrier substrate) may be first removed, stopping at third sacrificial layer. In some implementations, semiconductor layermay be completely removed using CMP, grinding, dry etching, and/or wet etching. In some implementations, semiconductor layermay be peeled off.

602 112 602 113 112 Then, third sacrificial layermay be completely removed as well using wet etching with suitable etchants, such as phosphoric acid and hydrofluoric acid. In some implementations, part of channel structureextending into third sacrificial layeris removed, such that semiconductor channelat the upper end (the source end) of channel structureis exposed.

112 116 106 122 50 116 106 122 The removal of parts of channel structurefrom the backside is much less challenging and has a higher production yield compared with the known solutions using front side wet etching via openingthrough dielectric stack/memory stackwith a high aspect ratio (e.g., greater than). By avoiding the issues introduced by the high aspect ratio of opening, the fabrication complexity and cost can be reduced, and the yield can be increased. Also, the vertical scalability (e.g., the increasing level of dielectric stack/memory stack) can be improved as well.

29 FIG. 31 FIG. 720 112 612 122 113 612 122 113 612 122 113 612 As shown inand operationin, a conductive layer is formed over channel structure. A doped semiconductor layeris formed on memory stackcovering the exposed semiconductor channel. In some implementations, to form doped semiconductor layer, a semiconductor layer (e.g., polysilicon) may be deposited on memory stackin contact with the exposed semiconductor channelusing one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof. The deposited semiconductor layer can be doped with N-type dopant(s), such as P, As, or Sb, using ion implantation and/or thermal diffusion. In some implementations, to form doped semiconductor layer, in-situ doping of N-type dopants, such as P, As, or Sb, is performed when depositing the semiconductor layer on memory stackcovering the exposed semiconductor channel. In some implementations, a CMP process may be further performed to remove any excess doped semiconductor layeras needed.

612 113 612 612 113 612 113 612 612 113 612 19 -3 21 -3 In some implementations, doped semiconductor layerand the part of semiconductor channelthat is in contact with doped semiconductor layerare locally activated. In some implementations, to locally activate, heat is applied in a confined area having doped semiconductor layerand the part of semiconductor channelto activate dopants in doped semiconductor layerand the part of semiconductor channel. The confined area can be between the stack structure and doped semiconductor layer. In some implementations, the doping concentration of doped semiconductor layerand the doping concentration of the part of semiconductor channelin contact with doped semiconductor layereach is between 10cmand 10cmafter the activation.

612 113 612 The local activation process can activate the dopants such that the dopants can occupy the silicon lattices to reduce the contact resistance between doped semiconductor layerand semiconductor channelas well as to reduce the sheet resistance of doped semiconductor layer. On the other hand, by confining the heat during the local activation process into an area without heat-sensitive structures, any potential damages to the heat-sensitive structures, such as the bonding interface and Cu interconnects used for connecting the peripheral circuits, can be reduced or avoided.

30 FIG. 612 614 612 614 612 112 As shown in, a source contact is formed in contact with doped semiconductor layer. In some implementations, an interconnection structuremay be formed on doped semiconductor layer. Interconnection structuremay include one or more ILD layers on doped semiconductor layerand a redistribution layer on the ILD layers. The source end of channel structuremay be coupled to the redistribution layer through the source contact.

32 FIG. 32 FIG. 800 800 800 808 802 804 806 808 808 804 illustrates a block diagram of an exemplary systemhaving a memory device, according to some aspects of the present disclosure. Systemcan be a mobile phone, a desktop computer, a laptop computer, a tablet, a vehicle computer, a gaming console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an argument reality (AR) device, or any other suitable electronic devices having storage therein. As shown in, systemcan include a hostand a memory systemhaving one or more memory devicesand a memory controller. Hostcan be a processor of an electronic device, such as a central processing unit (CPU), or a system-on-chip (SoC), such as an application processor (AP). Hostcan be configured to send or receive data to or from memory devices.

804 804 806 804 808 804 806 804 808 806 804 3 100 806 112 3 100 162 162 3 100 804 800 Memory devicecan be any memory device disclosed in the present disclosure. As disclosed above in detail, memory device, such as a NAND Flash memory device, may have a controlled and predefined discharge current in the discharge operation of discharging the bit lines. Memory controlleris coupled to memory deviceand hostand is configured to control memory device, according to some implementations. Memory controllercan manage the data stored in memory deviceand communicate with host. For example, memory controllermay be coupled to memory device, such asD memory devicedescribed above, and memory controllermay be configured to control operations of channel structureofD memory devicethrough source select gate line. By forming source select gate lineinD memory deviceas a CMOS structure, the induced threshold voltage (Vt) shift of the BSG transistor can be prevented. The reliability of memory devicecan be therefore improved by preventing unpredictable failure caused by the induced threshold voltage (Vt) shift. As a result, the performance of systemcan be improved.

806 806 806 804 806 804 806 804 806 804 806 808 806 In some implementations, memory controlleris designed for operating in a low duty-cycle environment like secure digital (SD) cards, compact Flash (CF) cards, universal serial bus (USB) Flash drives, or other media for use in electronic devices, such as personal computers, digital cameras, mobile phones, etc. In some implementations, memory controlleris designed for operating in a high duty-cycle environment SSDs or embedded multi-media-cards (eMMCs) used as data storage for mobile devices, such as smartphones, tablets, laptop computers, etc., and enterprise storage arrays. Memory controllercan be configured to control operations of memory device, such as read, erase, and program operations. Memory controllercan also be configured to manage various functions with respect to the data stored or to be stored in memory deviceincluding, but not limited to bad-block management, garbage collection, logical-to-physical address conversion, wear leveling, etc. In some implementations, memory controlleris further configured to process error correction codes (ECCs) with respect to the data read from or written to memory device. Any other suitable functions may be performed by memory controlleras well, for example, formatting memory device. Memory controllercan communicate with an external device (e.g., host) according to a particular communication protocol. For example, memory controllermay communicate with the external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnection (PCI) protocol, a PCI-express (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial-ATA protocol, a parallel-ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a Firewire protocol, etc.

806 804 802 806 804 902 902 902 904 902 808 806 804 906 906 908 906 808 906 902 33 FIG.A 32 FIG. 33 FIG.B 32 FIG. Memory controllerand one or more memory devicescan be integrated into various types of storage devices, for example, be included in the same package, such as a universal Flash storage (UFS) package or an eMMC package. That is, memory systemcan be implemented and packaged into different types of end electronic products. In one example as shown in, memory controllerand a single memory devicemay be integrated into a memory card. Memory cardcan include a PC card (PCMCIA, personal computer memory card international association), a CF card, a smart media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a UFS, etc. Memory cardcan further include a memory card connectorcoupling memory cardwith a host (e.g., hostin). In another example as shown in, memory controllerand multiple memory devicesmay be integrated into an SSD. SSDcan further include an SSD connectorcoupling SSDwith a host (e.g., hostin). In some implementations, the storage capacity and/or the operation speed of SSDis greater than those of memory card.

The foregoing description of the specific implementations can be readily modified and/or adapted for various applications. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed implementations, based on the teaching and guidance presented herein.

The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary implementations, but should be defined only in accordance with the following claims and their equivalents.