Semiconductor Devices and Data Storage Systems Including the Same

This application claims benefit of priority to Korean Patent Application No. 10-2024-0176364 filed on Dec. 2, 2024 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

A semiconductor device that is capable of storing high-capacity data in a data storage system has been desired. Accordingly, a method for increasing data storage capacity of a semiconductor device has been researched. For example, to increase integration density of a semiconductor device, a semiconductor device including memory cells arranged three-dimensionally, instead of two-dimensionally, has been suggested.

An example implementation of the present disclosure is to provide a semiconductor device having improved reliability, and a data storage system including the same.

According to an example implementation of the present disclosure, a semiconductor device includes a first semiconductor structure including a substrate, circuit devices on the substrate, and circuit interconnections on the circuit devices; and a second semiconductor structure on the first semiconductor structure, the second semiconductor structure having a first region and a second region, wherein the second semiconductor structure includes: a plate layer; gate electrodes stacked and spaced apart from each other on the plate layer in a vertical direction perpendicular to an upper surface of the plate layer, the gate electrodes extending to different lengths in a first direction intersecting the vertical direction in the second region, and each of the gate electrodes including a pad region, an upper surface of the pad region being exposed; interlayer insulating layers disposed alternately with the gate electrodes; a channel structure extending through the gate electrodes and the interlayer insulating layers in the first region, the channel structure extending in the vertical direction; contact plugs extending through the pad region of each of the gate electrodes in the second region, the contact plugs extending in the vertical direction, and the contact plugs electrically connecting the gate electrodes to at least one corresponding circuit interconnection of the circuit interconnections; dummy vertical structures extending through the gate electrodes and the interlayer insulating layers in the second region, the dummy vertical structures extending in the vertical direction and being spaced apart from the contact plugs in a horizontal direction; and contact insulating structures disposed alternately with the interlayer insulating layers, the contact insulating structures being at corresponding pad regions of the gate electrodes, the contact insulating structures surrounding the contact plugs, wherein the pad region of each of the gate electrodes includes a first pad region, and a first contact plug of the contact plugs extends through the first pad region, wherein the dummy vertical structures include a first dummy vertical structure adjacent to the first contact plug, and wherein the contact insulating structures include first contact insulating structures in contact with the first contact plug and the first dummy vertical structure, the first contact insulating structures being at the first pad region.

According to an example implementation of the present disclosure, a semiconductor device includes a stack pattern having a memory cell array region and a staircase region; a stack structure extending from the memory cell array region to the staircase region, the stack structure being on the stack pattern, wherein the stack structure includes interlayer insulating layers and gate electrodes disposed alternately in a vertical direction, and the gate electrodes include gate contact pads, the gate contact pads defining a staircase in the staircase region; a channel structure extending through the stack structure in the memory cell array region in the vertical direction; a first contact plug extending through the gate electrodes and the interlayer insulating layers in the staircase region; a first dummy vertical structure extending through the gate electrodes and the interlayer insulating layers in the staircase region, the first dummy vertical structure being adjacent to the first contact plug; first contact insulating structures disposed alternately with the interlayer insulating layers, the first contact insulating structures surrounding the first contact plug; and first dummy insulating structures disposed alternately with the interlayer insulating layers, the first dummy insulating structures surrounding the first dummy vertical structure, wherein the first contact insulating structures are spaced apart from the first dummy insulating structures, wherein each of the first dummy insulating structures includes a first dummy insulating pattern surrounding a first portion of the first dummy vertical structure, a second dummy insulating pattern surrounding a second portion of the first dummy vertical structure, the second portion of the first dummy vertical structure extending from the first portion, and a dummy insulating liner surrounding the first dummy insulating pattern and the second dummy insulating pattern, wherein the first dummy insulating pattern includes a first insulating material, and wherein the second dummy insulating pattern includes a second insulating material different from the first insulating material.

According to an example implementation of the present disclosure, a data storage system includes a semiconductor storage device comprising: a first semiconductor structure including circuit devices and circuit interconnections electrically connected to the circuit devices, a second semiconductor structure on the first semiconductor structure, the second semiconductor structure including a first region and a second region, and an input/output pad electrically connected to the circuit devices; and a controller electrically connected to the semiconductor storage device through the input/output pad, the controller electrically being configured to control the semiconductor storage device, wherein the second semiconductor structure includes: a plate layer; gate electrodes stacked and spaced apart from each other in a vertical direction on an upper surface of the plate layer, the gate electrodes extending to different lengths in a first direction intersecting the vertical direction in the second region, and each of the gate electrodes including a pad region, an upper surface of the pad region being exposed; interlayer insulating layers disposed alternately with the gate electrodes; channel structures extending through the gate electrodes and the interlayer insulating layers in the first region, the channel structures extending in the vertical direction; contact plugs extending through the pad region of each of the gate electrodes in the second region, the contact plugs extending in the vertical direction, the contact plugs electrically connecting the gate electrodes to at least one corresponding circuit interconnection of the circuit interconnections; dummy vertical structures extending through the gate electrodes and the interlayer insulating layers in the second region, the dummy vertical structures extending in the vertical direction and being spaced apart from the contact plugs in a horizontal direction intersecting the vertical direction; and contact insulating structures disposed alternately with the interlayer insulating layers, the contact insulating structures being at corresponding pad regions of the gate electrodes, the contact insulating structures surrounding the contact plugs, wherein the pad region of each of the gate electrodes includes a first pad region, and a first contact plug of the contact plugs extends through the first pad region, wherein the dummy vertical structures include a first dummy vertical structure adjacent to the first contact plug, and wherein each of the contact insulating structures includes a first contact insulating pattern in contact with the first contact plug and a first portion of the first dummy vertical structure at the first pad region, and second contact insulating patterns in contact with second portions of the first dummy vertical structure, the second portions of the first dummy vertical structure being connected to the first portion of the first dummy vertical structure.

Hereinafter, implementations of the present disclosure will be described as follows with reference to the accompanying drawings.

1 FIG.A 1 FIG.B 1 FIG.A 1 FIG.C 1 FIG.A 1 FIG.D 1 FIG.A is a plan diagram illustrating a semiconductor device in example implementations.is a cross-sectional diagram illustrating a semiconductor device taken along line I-I′ inaccording to an example implementation.is a cross-sectional diagram illustrating a semiconductor device taken along line II-II′ inaccording to an example implementation.is a cross-sectional diagram illustrating a semiconductor device taken along line III-III′ inaccording to an example implementation.

1 1 1 1 FIGS.A,B,C, andD 100 201 101 Referring to, a semiconductor devicemay include a peripheral circuit region PERI, which is a first semiconductor structure including a substrate, and a memory cell region CELL, which is a second semiconductor structure including a plate layer. The memory cell region CELL may be disposed on the peripheral circuit region PERI. In another example, the memory cell region CELL may be disposed below the peripheral circuit region PERI.

201 205 201 210 220 201 290 270 280 The peripheral circuit region PERI may include a substrate, impurity regionsin the substrate, device isolation layers, circuit devicesdisposed on the substrate, a peripheral region insulating layer, a circuit contact plug, and circuit interconnection lines.

201 201 210 205 201 201 The substratemay have an upper surface extending in the first direction (X-direction) and the second direction (Y-direction). The substratemay have an active region defined by the device isolation layers. The impurity regionsincluding impurities may be disposed in a portion of the active region. The substratemay include a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. The substratemay be provided as a bulk wafer or an epitaxial layer.

220 220 222 224 225 225 205 201 The circuit devicesmay include a planar transistor. Each of the circuit devicesmay include a circuit gate dielectric layer, a spacer layer, and a circuit gate electrode. On both sides of the circuit gate electrode, the impurity regionsmay be disposed in the substrateas source/drain regions.

290 220 201 290 290 The peripheral region insulating layermay be disposed on the circuit deviceon the substrate. The peripheral region insulating layermay include a plurality of insulating layers formed in different processes. The peripheral region insulating layermay be formed of an insulating material.

270 280 220 205 270 280 220 270 280 270 225 280 270 270 280 270 280 The circuit contact plugsand the circuit interconnection linesmay form a circuit interconnection structure electrically connected to the circuit devicesand the impurity regions. The circuit contact plugsmay have a cylindrical shape, and the circuit interconnection linesmay have a line shape. An electrical signal may be applied to the circuit deviceby the circuit contact plugsand the circuit interconnection lines. In the region not illustrated, the circuit contact plugsmay also be connected to the circuit gate electrode. The circuit interconnection linesmay be connected to the circuit contact plugs, may have a line shape, and may be disposed in a plurality of layers. The circuit contact plugsand the circuit interconnection linesmay include a conductive material, for example, tungsten (W), copper (Cu), aluminum (Al), and each component may further include a diffusion barrier. In example implementations, the number of layers of the circuit contact plugsand the circuit interconnection linesmay be varied.

1 2 101 130 120 130 1 130 170 130 2 175 170 110 130 2 121 101 180 170 192 194 196 130 The memory cell region CELL may include a first region Rand a second region R. The memory cell region CELL may include a source structure SS including a plate layer, gate electrodesstacked on the source structure SS and included in the gate structure GS, interlayer insulating layersalternately stacked with the gate electrodesand included in the gate structure GS, channel structures CH disposed to penetrate the gate structure GS in the first region R, isolation regions MS (also referred to as isolation structure in the present disclosure) extending by penetrating the gate structure GS, auxiliary isolation regions US disposed to penetrate a portion disposed in an upper portion of the gate electrodes, and contact plugsconnected to the gate electrodesand extending vertically in the second region R, and dummy vertical structuresdisposed to penetrate the gate structure GS and disposed around the contact plugs. In an example, the memory cell region CELL may further include a horizontal insulating layerdisposed below the gate electrodesin the second region R, substrate insulating layersdisposed to penetrate the plate layer, studson the channel structure CH and the contact plugs, and first to third cell region insulating layers,, andcovering the gate electrodes.

1 130 1 2 130 2 2 1 1 2 In the memory cell region CELL, in the first region R, the gate electrodesmay be vertically stacked and the channel structure CH may be disposed, and the memory cells may be disposed in the first region R. In the second region R, the gate electrodesmay extend to different lengths and may form gate pad regions GP, and the second region Rmay be configured to electrically connect the memory cells to the peripheral circuit region PERI. The second region Rmay be disposed at least in one direction, for example, in the first direction (X-direction) on at least one end of the first region R. In example implementations, the first region Rmay be referred to as a memory cell array region, and the second region Rmay be referred to as a staircase region.

101 102 104 1 The source structure SS may include a plate layer, a first horizontal conductive layer, and a second horizontal conductive layerstacked in order in the first region R. However, in example implementations, the number of conductive layers included in the source structure SS may be varied. In example implementations, the source structure SS may be referred to as a stack pattern.

101 100 101 101 101 101 101 The plate layermay have a plate shape and may function as at least a portion of a common source line of the semiconductor device. The plate layermay have an upper surface extending in the first direction (X-direction) and the second direction (Y-direction). The plate layermay include a conductive material. For example, the plate layermay include a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. For example, the group IV semiconductor may include silicon, germanium, or silicon-germanium. The plate layermay further include impurities. The plate layermay be provided as a polycrystalline semiconductor layer, such as a polycrystalline silicon layer, or an epitaxial layer.

102 104 101 1 102 2 104 2 102 100 101 102 140 140 104 101 2 102 110 1 FIG.D The first and second horizontal conductive layersandmay be stacked in order on an upper surface of the plate layerin the first region R. The first horizontal conductive layermay not extend to the second region R, and the second horizontal conductive layermay extend to the second region R. The first horizontal conductive layermay function as a portion of a common source line of the semiconductor device, for example, may function as a common source line together with the plate layer. As illustrated in, the first horizontal conductive layermay be directly connected to the channel layeraround the channel layer. The second horizontal conductive layermay be in contact with the plate layerat partial regions of the second region Rin which the first horizontal conductive layerand the horizontal insulating layerare not disposed.

102 104 102 101 104 102 104 The first and second horizontal conductive layersandmay include a semiconductor material, for example, may include polycrystalline silicon. In this case, at least the first horizontal conductive layermay be a layer doped with impurities of conductivity-type the same as that of the plate layer, and the second horizontal conductive layermay be a doped layer or a layer including impurities diffused from the first horizontal conductive layer. However, the material of the second horizontal conductive layeris not limited to a semiconductor material, and may also be replaced with an insulating layer.

110 101 102 2 110 111 112 2 101 110 102 100 The horizontal insulating layermay be disposed on the plate layerat the same level as the first horizontal conductive layerin at least a portion of the second region R. The horizontal insulating layermay include first and second horizontal insulating layersandalternately stacked on the second region Rof the plate layer. The horizontal insulating layermay be layers remaining after a portion is replaced with the first horizontal conductive layerin a process of manufacturing the semiconductor device.

110 111 112 111 120 112 120 The horizontal insulating layermay include silicon oxide, silicon nitride, silicon carbide, or silicon oxynitride. The first horizontal insulating layerand the second horizontal insulating layermay include different insulating materials. For example, the first horizontal insulating layersmay be formed of the same material as a material of the interlayer insulating layers, and the second horizontal insulating layermay be formed of a material different from a material of the interlayer insulating layers.

121 101 110 104 2 121 1 121 104 121 The substrate insulating layersmay be disposed to penetrate the plate layer, the horizontal insulating layer, and the second horizontal conductive layerin a portion of the second region R. The substrate insulating layersmay further be disposed in the first region R, for example, in a region in which a through-via extending from the memory cell region CELL to the peripheral circuit region PERI is disposed. An upper surface of the substrate insulating layermay be coplanar with an upper surface of the second horizontal conductive layer. The substrate insulating layermay include an insulating material, for example, silicon oxide, silicon nitride, silicon carbide, or silicon oxynitride.

130 101 120 1 2 3 130 1 2 3 The gate electrodesmay be vertically stacked and spaced apart from each other on the plate layerand may be included in a gate structure GS together with interlayer insulating layers. The gate structure GS may include first, second and third stack structures GS, GSand GS, vertically stacked. However, in example implementations, the number of stack structures included in the gate structure GS may be varied. For example, the gate structure GS may include four or more stack structures, or may include a single stack structure or two stack structures. The number of the gate electrodesincluded in each of the first, second and third stack structures GS, GSand GSmay be the same or different.

130 130 130 130 130 100 130 130 130 130 130 130 130 130 130 130 130 130 130 The gate electrodesmay include lower gate electrodesL forming gates of ground select transistors, memory gate electrodesM included in a plurality of memory cells, and upper gate electrodesU included in gates of string select transistors. The number of the memory gate electrodesM included in the memory cells may be determined depending on capacity of the semiconductor device. In example implementations, each of the number of the upper gate electrodesU and the number of the lower gate electrodesL may be 1 to 4 or more, and the upper and lower gate electrodesU andL may have a structure the same as or different from as the memory gate electrodesM. In example implementations, the gate electrodesmay further include gate electrodesincluded in an erase transistor disposed adjacent to the upper gate electrodesU and/or the lower gate electrodesL and used in an erase operation using a gate induced drain leakage (GIDL) phenomenon. Also, a portion of the gate electrodes, for example, the memory gate electrodesM adjacent to the upper or lower gate electrodesU andL, may be dummy gate electrodes.

1 FIG.A 130 1 2 130 130 130 As illustrated in, the gate electrodesmay be isolated from each other in the second direction (Y-direction) by isolation regions MS extending continuously from the first region Rand the second region R. The gate electrodesmay form one memory block between a pair of isolation regions MS, but the range of the memory block is not limited thereto. A portion of the gate electrodes, for example, the memory gate electrodesM, may form each layer in one memory block.

130 1 1 2 170 130 The gate electrodesmay be stacked vertically spaced apart from each other on the first region R, may extend from the first region Rto the second region Rwith different lengths and may form step structures in the form of a staircase in the gate pad regions GP. The gate pad regions GP may be defined as regions including gate pads connected to the contact plugsof the gate electrodes.

1 FIG.B 130 1 2 3 130 2 3 1 3 2 1 1 1 2 3 1 2 3 130 As illustrated in, the gate electrodesmay have a form in which the gate pad regions GP are removed from an upper portion of one of the first to third stack structures GS, GS, and GSby a predetermined depth. The gate pad regions GP may be disposed so as not to overlap each other in the third direction (Z-direction), which is the vertical direction. The gate electrodesincluded in the second and third stack structures GSand GSon the gate pad regions GP of the first stack structure GSmay extend horizontally. In the example implementation, the gate pad regions GP may be disposed in the order of the third stack structure GS, the second stack structure GS, and the first stack structure GSfrom the first region Rin the first direction (X-direction). Only one gate pad region GP may be disposed in each of the first, second and third stack structures GS, GS, and GSas illustrated, or a plurality of gate pad regions GP may be disposed in each of the first, second, and third stack structures GS, GS, and GS. However, the arrangement shape, arrangement order, and depth of the gate pad regions GP in the example implementations may be varied. In an example, the gate electrodesmay not be disposed on the gate pad regions GP.

130 1 1 2 The gate electrodesmay form first and second step structures in an asymmetrical shape in the first direction (X-direction) in each gate pad region GP. The first step structure may be a staircase structure relatively adjacent to the first region Rand having a level decreasing in the first direction (X-direction), and the second step structure may be a staircase structure positioned relatively far from the first region Rand having a level increasing in the first direction (X-direction). For example, a slope of the first step structure in each gate pad regions GP may be less than a slope of the second step structure in the second region R. However, in some example implementations, the first and second step structures may have a symmetrical shape.

130 170 130 170 130 130 130 170 170 2 1 FIG.B In the first step structure, the gate electrodesmay be connected to the contact plugs, and in the second step structure, the gate electrodesmay form a dummy region not connected to the contact plugs. In example implementations, a specific shape of the step structure, and the number of gate electrodesforming each step structure are not limited to the example illustrated in. In some example implementations, the gate electrodesmay be disposed to have step structures in the second direction (Y-direction) as well. The gate electrodesmay include contact regions (not illustrated) connected to the contact plugs. The contact regions may be regions of the gate electrode layer not covered by other gate electrodes in one stack structure, and may be defined as regions in which gate pads in contact with the contact plugsin each of the stack structures GS disposed in the second region Rare disposed.

130 130 130 The gate electrodesmay include a metal material, for example, tungsten (W). In example implementations, the gate electrodesmay include polycrystalline silicon or a metal silicide material. In example implementations, the gate electrodesmay further include a diffusion barrier, for example, the diffusion barrier may include tungsten nitride (WN), tantalum nitride (TaN), titanium nitride (TiN), or a combination thereof.

120 130 120 101 130 1 2 3 120 120 120 120 The interlayer insulating layersmay be disposed between the gate electrodes. The interlayer insulating layersmay also be disposed to be spaced apart from each other in the vertical direction and to extend in the first direction (X-direction) on the upper surface of the plate layer, similarly to the gate electrodes. In each of the first, second, and third stack structures GS, GS, and GS, thicknesses of the interlayer insulating layersmay not be the same. In an example, at least a portion of the interlayer insulating layersmay have different thicknesses from other portions. Also, the number of interlayer insulating layersmay be varied from the illustrated example. The interlayer insulating layersmay include an insulating material such as silicon oxide or silicon nitride.

101 1 101 1 Each of the channel structures CH may form a memory cell string and may be spaced apart from each other in rows and columns on the plate layerin the first region R. The channel structures CH may be disposed in a grid pattern in the X-Y plane, or in a zigzag pattern in one direction. The channel structures CH may have a columnar shape and may have sloped side surfaces having a width decreasing toward the plate layerdepending on an aspect ratio. In example implementations, at least a portion of the channel structures CH disposed on an end of the first region Rmay be dummy channel structures.

1 FIG.D 1 2 3 1 2 3 1 2 3 1 2 1 3 2 1 2 3 1 2 3 1 1 101 Referring to, each of the channel structures CH may include first, second, and third channel portions CH, CH, and CHstacked in the third direction (Z-direction). The first, second, and third channel portions CH, CH, and CHmay penetrate the first, second, and third stack structures GS, GS, and GSof the gate structure GS, respectively. The channel structure CH may have a form in which the first channel portion CH, the second channel portion CHof the upper portion of the first channel portion CH, and the third channel portion CHof the upper portion of the second channel portion CHare connected to each other. The first, second, and third channel portions CH, CH, and CHmay have a form in which a width of an upper surface of the channel portion disposed in a lower portion is greater than a width of a lower surface of the channel portion disposed in an upper portion in a connected region or an interfacial surface. The channel structure CH may have bent portions due to a difference in width at an interfacial surface between the first, second, and third channel portions CH, CH, and CH. However, the number of the channel portions stacked in the third direction (Z-direction) in the channel structure CH may be varied in example implementations. The first channel portion CHmay further penetrate a portion of the source structure SS, and a lower end of the first channel portion CHmay be positioned in the plate layer.

140 145 147 149 140 145 147 1 2 3 Each of the channel structures CH may include a channel layer, a gate dielectric layer, a channel filling insulating layer, and a channel paddisposed in a channel hole. The channel layer, the gate dielectric layer, and the channel filling insulating layermay be connected to each other between the first, second, and third channel portions CH, CH, and CH.

140 147 140 147 140 102 140 The channel layermay be formed in an annular shape surrounding the channel filling insulating layertherein, but in example implementations, the channel layermay also have a columnar shape such as a cylindrical shape or a prism shape without the channel filling insulating layer. The channel layermay be connected to the first horizontal conductive layerin a lower portion. The channel layermay include a semiconductor material such as polycrystalline silicon or single crystal silicon.

145 130 140 145 140 145 130 2 3 4 2 3 4 The gate dielectric layermay be disposed between the gate electrodesand the channel layer. Although not specifically illustrated, the gate dielectric layermay include a tunneling layer, a charge storage layer, and a blocking layer stacked in order from the channel layer. The tunneling layer may tunnel electric charge into the charge storage layer and may include, for example, silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), or a combination thereof. The charge storage layer may be a charge trap layer or a floating gate conductive layer. The blocking layer may include, for example, silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), a high-k dielectric material, or a combination thereof. In example implementations, at least a portion of the gate dielectric layermay extend in the horizontal direction along the gate electrodes.

149 3 149 The channel padmay be disposed only on an upper end of the third channel portion CHin an upper portion. The channel padmay include, for example, doped polycrystalline silicon.

130 1 2 2 1 2 1 FIG.A 1 FIG.A The isolation regions MS may penetrate at least a portion of the gate electrodesand may extend in the first direction (X-direction). As illustrated in, the isolation regions MS may be disposed in parallel with each other. A portion of the isolation regions MS may extend along the first region Rand the second region Ras an integrated region, and the other portion may extend only to a portion of the second region R, or may be disposed intermittently in the first region Rand the second region R. However, in example implementations, the arrangement, number, or the like, of the isolation regions MS are not limited to the example illustrated in.

130 101 102 104 101 101 The isolation regions MS may penetrate the gate electrodesstacked on the plate layer, may further penetrate the first and second horizontal conductive layersandtherebelow and may be connected to the plate layer. The isolation regions MS may have a shape of which a width decreases toward the plate layerdue to a high aspect ratio. For example, a side surface of the isolation regions MS may have a substantially constant slope such that a width may decrease continuously or consecutively, and may not have a bent portion on the side surface.

105 105 In the isolation regions MS, the first isolation insulating layermay be disposed. The first isolation insulating layermay include, for example, silicon oxide, silicon nitride, or silicon oxynitride.

1 1 FIGS.A andD 2 1 130 130 130 130 130 Referring to, the auxiliary isolation regions US may extend in the first direction (X-direction) between adjacent isolation regions MS. The auxiliary isolation regions US may be disposed in a portion of the second region Rand the first region R. The auxiliary isolation regions US may penetrate a portion of the gate electrodes, including the upper gate electrodeU of the uppermost portion of the gate electrodes. The auxiliary isolation regions US may isolate, for example, three gate electrodesfrom each other in the second direction (Y-direction). However, the number of gate electrodesisolated by the auxiliary isolation regions US may be varied in example implementations.

103 103 In the auxiliary isolation region US, a second isolation insulating layermay be disposed. The second isolation insulating layermay include, for example, silicon oxide, silicon nitride, or silicon oxynitride.

170 130 2 170 192 194 196 130 170 130 104 110 101 280 170 130 160 170 101 110 104 121 The contact plugsmay be connected to gate pad regions GP of the gate electrodesin the second region R. The contact plugsmay penetrate at least a portion of the cell region insulating layers,, and, and may be connected to each of the gate pad regions GP of the gate electrodesof which upper surfaces are exposed. The contact plugsmay penetrate the gate electrodesabove and below the gate pad regions GP, and may penetrate the second horizontal conductive layer, the horizontal insulating layer, and the plate layerand may be connected to circuit interconnection linesin the peripheral circuit region PERI. The contact plugsmay be spaced apart from the gate electrodesabove and below the gate pad regions GP by the contact insulating structures. The contact plugsmay be spaced apart from the plate layer, the horizontal insulating layer, and the second horizontal conductive layerby the substrate insulating layers.

170 170 1 2 3 1 2 3 1 2 3 1 121 1 2 3 201 1 2 3 1 121 1 The contact plugsmay have a shape corresponding to the channel structures CH. Each of the contact plugsmay include first to third contact portions MC, MC, and MCstacked from a lower portion. The first, second, and third contact portions MC, MC, and MCmay penetrate the first, second, and third stack structures GS, GS, and GSof the gate structure GS, respectively. The first contact portion MCmay further penetrate the substrate insulating layer. The first to third contact portions MC, MC, and MCmay have a cylindrical shape of which a width decreases toward the substratedue to an aspect ratio. Each of the first to third contact portions MC, MC, and MCmay have a substantially constant slope. The first contact portion MCmay further include a landing region of which a width is enlarged below the substrate insulating layer. However, in some example implementations, the first contact portion MCmay not include the landing region.

1 2 3 170 1 2 3 The first, second, and third contact portions MC, MC, and MCmay have a shape in which a width of an upper surface of the contact portion disposed in a lower portion is greater than a width of a lower surface of the contact portion disposed in an upper portion in an interconnected region or on an interfacial surface. Accordingly, similarly to the channel structure CH, the contact plugmay have bent portions due to a difference in widths at interfacial surfaces between the first, second, and third contact portions MC, MC, and MC.

1 2 1 2 1 1 2 2 A level of an interfacial surface between the first contact portion MCand the second contact portion MCmay be the same as a level of an interfacial surface between the first channel portion CHand the second channel portion CH. In an example, a level of an upper surface of the first contact portion MCmay be the same as a level of an upper surface of the first channel portion CH, and a level of an upper surface of the second contact portion MCmay be the same as a level of an upper surface of the second channel portion CH.

170 170 The contact plugsmay include a conductive material, for example, at least one of tungsten (W), copper (Cu), aluminum (Al), and alloys thereof. In some example implementations, the contact plugsmay include a barrier layer extending along a side surface and a bottom surface, or may have an air gap therein.

160 170 160 160 160 160 160 170 160 170 160 130 160 The contact insulating structuresmay be disposed to surround a side surface of each of the contact plugsabove and below the gate pad region GP. In some implementations, the contact insulating structuresmay be disposed above a corresponding gate pad region GP. In some implementations, the contact insulating structuresmay be disposed above and below a corresponding gate pad region GP. In some implementations, the contact insulating structuresmay be disposed below a corresponding gate pad region GP. In the present disclose, the contact insulating structuresthat are disposed above and/or below the corresponding gate pad region GP can also be described as being disposed at the corresponding gate pad region GP. The contact insulating structuresmay be spaced apart from each other in the third direction (Z-direction) around each of the contact plugs. The contact insulating structuresmay extend horizontally from a side surface of each of the contact plugs. The contact insulating structuresmay be disposed at substantially the same level as the gate electrodes, respectively. The contact insulating structuresmay include an insulating material, for example, silicon oxide, silicon nitride, or silicon oxynitride.

160 160 160 160 160 170 160 170 175 a b a a a b b b. The contact insulating structuresmay include a first contact insulating structureand a second contact insulating structuredistinct from the first contact insulating structure. In an example, the first contact insulating structuremay surround the first contact plug. The second contact insulating structuremay surround the second contact plugand the second dummy vertical structure

170 170 170 170 160 170 160 a b a a b b. The contact plugsmay include the first contact plugand the second contact plug. The first contact plugmay be a contact plug surrounded by the first contact insulating structure, and the second contact plugmay be a contact plug surrounded by the second contact insulating structure

1 1 1 FIGS.A,B, andC 1 FIG.A 175 2 175 170 175 170 175 170 160 b b. Referring to, the dummy vertical structuresmay be spaced apart from each other in rows and columns in the second region R. The dummy vertical structuresmay be disposed to surround each of the contact plugs. For example, as illustrated in, when viewed on a plane, four dummy vertical structuresmay surround the contact plugs, respectively. In an example, at least one of the four dummy vertical structuresmay share a second contact plugand a second contact insulating structure

1 FIG.C 175 170 175 175 As illustrated in, the dummy vertical structuresmay be regularly arranged in regions in which the contact plugsare spaced apart from each other in the first direction (X-direction). However, in example implementations, the arrangement shape of the dummy vertical structuresmay be varied. When viewed on a plane, the dummy vertical structuresmay have a circular shape, oval shape, or a shape similar thereto.

175 170 175 1 2 3 1 2 3 1 101 1 2 3 101 The dummy vertical structuresmay have a shape corresponding to the contact plugs. Each of the dummy vertical structuresmay include first to third dummy extension portions IC, IC, and ICstacked from a lower portion. The first to third dummy extension portions IC, IC, and ICmay penetrate the gate structure GS. A lower surface of the first dummy extension portion ICmay be buried in the plate layer. The first to third dummy extension portions IC, IC, and ICmay have a cylindrical shape of which a width decreases toward the plate layerdue to an aspect ratio.

1 2 3 170 175 1 2 3 The first to third dummy extension portions IC, IC, and ICmay have a shape of which a width of an upper surface of the dummy extension portion disposed in the lower portion is greater than a width of a lower surface of the dummy extension portion disposed in an upper portion in a connected region or on an interfacial surface. Accordingly, similarly to the contact plug, the dummy vertical structuresmay also have bent portions due to a difference in widths at an interfacial surface between the first to third dummy extension portions IC, IC, and IC.

175 175 175 175 The dummy vertical structuresmay have a structure the same as or different from the channel structures CH. When the dummy vertical structuresare formed together with the channel structures CH, the dummy vertical structuresmay have the same structure as the channel structures CH. A diameter or a maximum width of the dummy vertical structuresmay be greater than a diameter of the channel structures CH, but an example implementation thereof is not limited thereto.

175 170 175 175 175 When the dummy vertical structuresare formed using a portion during in process of forming the contact plugs, the dummy vertical structuresmay have a structure different from the channel structures CH. The dummy vertical structuresdo not include a conductive layer and may include an insulating material. For example, dummy vertical structuresmay include silicon oxide, silicon nitride, or silicon oxynitride.

175 100 The dummy vertical structuresmay not be electrically connected to interconnection structures in an upper portion, and may not form a memory cell string, differently from the channel structures in the semiconductor device.

175 175 175 170 175 150 175 170 175 170 160 175 a b a a b b b b.” The dummy vertical structuresmay include first dummy vertical structuresand second dummy vertical structures. The dummy vertical structure disposed adjacent to the first contact plugamong the dummy vertical structuresand surrounded by the dummy insulating structuresmay be the “first dummy vertical structure,” and the dummy vertical structure disposed adjacent to the second contact plugamong the dummy vertical structuresand sharing the second contact plugand the second contact insulating structuremay be the “second dummy vertical structure

150 175 150 120 130 150 160 160 a a b. The dummy insulating structuresmay be spaced apart from each other in the third direction (Z-direction) around each of the first dummy vertical structures. The dummy insulating structuresmay be disposed alternately with the interlayer insulating layersand disposed at substantially the same level as each of the gate electrodes. Each of the dummy insulating structuresmay be disposed at the same level as the first and second contact insulating structuresand

180 180 170 130 180 180 The studsmay form a cell interconnection structure electrically connected to memory cells in the memory cell region CELL. The studsmay be connected to the channel structures CH and the contact plugsand may be electrically connected to the channel structures CH and the gate electrodes. The studsmay have a form of plugs, but an example implementation thereof is not limited thereto, and may also have a line form. In example implementations, the number of plugs and interconnection lines included in the cell interconnection structure may be varied. The studsmay include a metal, for example, tungsten (W), copper (Cu), aluminum (Al), or the like.

192 194 196 1 2 3 192 194 196 1 2 3 192 194 196 192 194 196 120 120 192 194 196 120 The first to third cell region insulating layers,, andmay be disposed to cover the first, second, and third stack structures GS, GS, and GS, respectively. The first to third cell region insulating layers,, andmay be disposed in an uppermost portion of the first, second, and third stack structures GS, GS, and GS. Each of the first, second, and third cell region insulating layers,, andmay be formed of an insulating material, and may be formed in a plurality of insulating layers. When the first, second, and third cell region insulating layers,, andinclude the same material as that of the interlayer insulating layers, interfacial surfaces between the interlayer insulating layersmay not be distinct. The first, second, and third cell region insulating layers,, andand the interlayer insulating layersmay be collectively referred to as interlayer insulating layers in example implementations.

In example implementations, the first direction (X-direction) and the second direction (Y-direction) may be perpendicular to each other. The first direction (X-direction) and the second direction (Y-direction) may be perpendicular to the third direction (Z-direction). The horizontal direction may indicate the first direction (X-direction) and the second direction (Y-direction), or a direction that is angled relative to the first direction or the second direction, and the vertical direction may indicate the third direction (Z-direction). The horizontal direction, the first direction and the second direction can be horizontal.

2 FIG. 1 FIG.B is an enlarged diagram illustrating region C of the semiconductor device in.

2 FIG. 2 FIG. 1 FIG.A 2 FIG. 1 FIG.B 170 130 130 170 170 170 160 160 160 a a b a b Referring to, the contact plugsmay be connected to the first gate electrode portionof the gate electrodesthrough the gate pad regions GP. The contact plugdescribed with reference tomay be also applied to the first and second contact plugsandin, and the contact insulating structuredescribed with reference tomay also be applied to the first and second contact insulating structuresandin.

170 130 170 170 130 120 170 170 a The contact plugmay have a form enlarged in the horizontal direction toward the first gate electrode portion. In an example, the contact plugsmay include a vertical extension portionV penetrating the gate electrodesand the interlayer insulating layersand extending in the third direction (Z-direction), and a horizontal extension portionH enlarged in the horizontal direction from the vertical extension portionV and in contact with the gate pad region GP.

130 170 170 Each of the gate electrodesmay include a gate pad region GP and a gate stack region GN, which is a region other than the gate pad region GP. The gate pad region GP may be a region of the gate electrode layer not covered by other gate electrodes due to a step structure. The gate stack region GN may be another region of the gate electrode layer covered by other gate electrodes. The gate pad region GP may be in contact with the horizontal extension portionH of the contact plug.

130 130 130 130 130 a b a b Each of the gate electrodesmay include a first gate electrode portioncorresponding to the gate pad region GP and a second gate electrode portioncorresponding to the gate stack region GN. In example implementations, the first gate electrode portionmay be referred to as a gate contact pad, and the second gate electrode portionmay be referred to as a gate stack structure.

160 120 130 130 160 170 160 170 170 170 130 160 b b The contact insulating structuresmay be disposed alternately with the interlayer insulating layersand may be disposed at the same level as the second gate electrode portionsof the gate electrodesin a lower portion of the gate pad region GP. The contact insulating structuresmay be disposed between the gate stack region GN and the vertical extension portionV. The contact insulating structuresmay overlap the horizontal extension portionH of the contact plugin the third direction (Z-direction). The contact plugmay be electrically isolated from the second gate electrode portionin a lower portion of the gate pad region GP by the contact insulating structure.

160 164 170 162 164 162 130 130 164 162 164 162 b Each of the contact insulating structuresmay include a contact insulating patternsurrounding a side surface of the contact plugsand a contact insulating linersurrounding an external side surface of the contact insulating pattern. The contact insulating linermay be in contact with the second gate electrode portionof the gate electrode. The contact insulating patternmay include a first insulating material, and the contact insulating linermay include a second insulating material different from the first insulating material. For example, the contact insulating patternmay include silicon nitride, and the contact insulating linermay include silicon oxide.

3 FIG. 1 FIG.A 4 FIG. 3 FIG. 3 FIG. 2 FIG. 170 160 175 150 130 a a a b is an enlarged diagram illustrating region A of the semiconductor device in.is a cross-sectional diagram illustrating a semiconductor device taken along line A-A′ inaccording to an example implementation.is a plan diagram illustrating the first contact plug, the first contact insulating structure, the first dummy vertical structure, and the dummy insulating structuresdisposed at the same level as the second gate electrode portionsin.

3 4 FIGS.and 1 FIG.B 100 170 175 170 160 170 150 175 a a a a a a Referring to, region A of the semiconductor devicemay include a first contact plugdisposed between the isolation regions MS, first dummy vertical structuresadjacent to the first contact plug, first contact insulating structuressurrounding the first contact plugand spaced apart from each other in the third direction (Z-direction) in a lower portion of the gate contact region (e.g., the gate pad region GP of), and dummy insulating structuressurrounding the first dummy vertical structures, respectively, and spaced apart from each other in the third direction (Z-direction).

170 a The isolation regions MS may extend in the first direction (X-direction) and may be spaced apart from each other in the second direction (Y-direction). For example, the isolation regions MS may include a first isolation region extending in a first direction (X-direction) and a second isolation region spaced apart from the first isolation region in the second direction (Y-direction). The first contact plugmay be disposed between the first isolation region and the second isolation region.

160 170 170 160 120 160 164 170 170 162 164 164 162 164 162 a a a a a a a a a a a a 2 FIG. The first contact insulating structuresmay surround the vertical extension portion of the first contact plug(e.g., the vertical extension portionV of) and may be spaced apart from each other in a third direction (Z-direction). The first contact insulating structuresmay be disposed alternately with the interlayer insulating layersin the third direction (Z-direction). Each of the first contact insulating structuresmay include a 1-1 contact insulating patternsurrounding a vertical extension portionV of the first contact plugand a first contact insulating linersurrounding the 1-1 contact insulating pattern. In an example, the 1-1 contact insulating patternmay include a first insulating material, and the first contact insulating linermay include a second insulating material different from the first insulating material. For example, the 1-1 contact insulating patternmay include silicon nitride, and the first contact insulating linermay include at least one of silicon oxide, silicon carbide, or silicon oxynitride.

175 170 170 175 170 175 1751 1752 1753 1754 1751 170 1752 170 1753 170 1754 170 1751 1752 170 1753 1754 170 a a a a a a a a a a a a a a a a a a a a a a a a The first dummy vertical structuresmay be disposed adjacent to the first contact plugand may surround the first contact plug. The first dummy vertical structuresmay include four dummy structures surrounding the first contact plug. In an example, the first dummy vertical structuresmay include a 1-1 dummy vertical structure, a 1-2 dummy vertical structure, a 1-3 dummy vertical structureand a 1-4 dummy vertical structure. In an example, when viewed on the plane, the 1-1 dummy vertical structuremay be disposed on the left side on the first contact plug, the 1-2 dummy vertical structuremay be disposed on the right side on the first contact plug, the 1-3 dummy vertical structuremay be disposed on the left side below the first contact plug, and the 1-4 dummy vertical structuremay be disposed on the right side below the first contact plug. In an example, the 1-1 dummy vertical structureand the 1-2 dummy vertical structuremay be in contact with a first isolation region disposed on the first contact plugamong the isolation regions MS when viewed on a plane, and the 1-3 dummy vertical structureand the 1-4 dummy vertical structuremay be in contact with a second isolation region disposed below the first contact plugamong the isolation regions MS when viewed on a plane.

175 170 175 170 175 175 130 a a a a a a Each of the first dummy vertical structuresmay include a first portion Sa adjacent to the first contact plug, second portions Sb extending from the first portion Sa and connected by the first portion Sa, and a third portion Sc connecting the second portions Sb to each other and in contact with the isolation region MS. The first portion Sa of the first dummy vertical structuresmay be more adjacent to the first contact plugthan the second portions Sb of the first dummy vertical structures. The third portion Sc of each of the first dummy vertical structuresmay be a side surface exposed by the gate electrodes.

170 175 170 1751 170 1752 170 1753 170 1754 170 175 a a a a a a a a a a a a When viewed on a plane, a spacing distance between the first contact plugand the first dummy vertical structuresmay be the same. For example, when viewed on a plane, the distance between the first contact plugand the 1-1 dummy vertical structure, a distance between the first contact plugand the 1-2 dummy vertical structure, a distance between the first contact plugand the 1-3 dummy vertical structure, and a distance between the first contact plugand the 1-4 dummy vertical structuremay be the same. However, an example implementation thereof is not limited thereto. For example, a spacing distance between the first contact plugand the first dummy vertical structuresmay be different.

175 150 150 1751 1752 1753 1754 150 120 1751 150 130 160 a a a a a a a. Each of the first dummy vertical structuresmay be surrounded by dummy insulating structures. In an example, the dummy insulating structuresmay surround the 1-1 dummy vertical structure, the 1-2 dummy vertical structure, the 1-3 dummy vertical structureand the 1-4 dummy vertical structure, respectively, and may be spaced apart from each other in the third direction (Z-direction). For example, the dummy insulating structuresmay be disposed alternately with the interlayer insulating layersand may surround the 1-1 dummy vertical structure. In an example, the dummy insulating structuresmay be disposed at the same level as the gate electrodesand the first contact insulating structures

150 1751 150 1752 150 160 130 150 160 a a a a The dummy insulating structuressurrounding the 1-1 dummy vertical structuremay be spaced apart from each other in the third direction (Z-direction) and may be spaced apart from the dummy insulating structuressurrounding the 1-2 dummy vertical structurein the horizontal direction. The dummy insulating structuresmay be spaced apart from the first contact insulating structuresin the horizontal direction. In an example, the gate electrodemay be disposed between the dummy insulating structuresand the first contact insulating structurewhen viewed on a plane

150 154 175 156 175 152 154 156 150 1751 154 1751 156 1751 152 154 156 154 156 156 154 154 170 156 156 1751 1752 154 1751 1752 170 156 1753 1754 154 1753 1754 170 a a a a a a a a a a a a a a a a The dummy insulating structuremay include a first dummy insulating patternsurrounding a first portion Sa of each of the first dummy vertical structures, a second dummy insulating patternssurrounding a second portions Sb of each of the first dummy vertical structures, and a dummy insulating linersurrounding the first dummy insulating patternand the second dummy insulating patterns. For example, a dummy insulating structuresurrounding a 1-1 dummy vertical structuremay include a first dummy insulating patternin contact with a first portion Sa of the 1-1 dummy vertical structure, second dummy insulating patternsin contact with the second portions Sb of the 1-1 dummy vertical structure, and a dummy insulating linersurrounding the first dummy insulating patternand the second dummy insulating patterns. The first dummy insulating patternmay correspond to a surface profile of the first portion Sa, and the second dummy insulating patternsmay correspond to a surface profile of the second portions Sb. The second dummy insulating patternsmay be disposed between the first dummy insulating patternand the isolation region MS when viewed on a plane. In an example, the first dummy insulating patternmay be disposed more adjacent to the first contact plugthan the second dummy insulating patterns. When viewed on a plane, the second dummy insulating patternsof each of the 1-1 dummy vertical structureand the 1-2 dummy vertical structuremay be disposed between the first dummy insulating patternof each of the 1-1 dummy vertical structureand the 1-2 dummy vertical structureand the first isolation region disposed on an upper side of the first contact plugamong the isolation regions MS. When viewed on a plane, the second dummy insulating patternsof each of the 1-3 dummy vertical structureand the 1-4 dummy vertical structuremay be disposed between the first dummy insulating patternof each of the 1-3 dummy vertical structureand the 1-4 dummy vertical structureand the second isolation region disposed on a lower side of the first contact plugamong the isolation regions MS.

154 1751 154 1752 156 1751 156 1752 154 1753 154 1754 156 1753 156 1754 a a a a a a a a The first dummy insulating patternof the 1-1 dummy vertical structuremay be disposed parallel to the first dummy insulating patternof the 1-2 dummy vertical structurein the first direction (X-direction). The second dummy insulating patternsof the 1-1 dummy vertical structuremay be disposed side by side with the second dummy insulating patternsof the 1-2 dummy vertical structurein the first direction (X-direction). The first dummy insulating patternof the 1-3 dummy vertical structuremay be disposed side by side with the first dummy insulating patternof the 1-4 dummy vertical structurein the first direction (X-direction). The second dummy insulating patternsof the 1-3 dummy vertical structuremay be disposed side by side with the second dummy insulating patternsof the 1-4 dummy vertical structurein the first direction (X-direction)

154 156 154 156 The first dummy insulating patternmay include a first insulating material, and the second dummy insulating patternmay include a second insulating material different from the first insulating material. For example, the first dummy insulating patternmay include silicon nitride, and the second dummy insulating patternmay include silicon oxide.

5 FIG. 1 FIG.A 6 FIG.A 5 FIG. 6 FIG.B 5 FIG. 5 FIG. 2 FIG. 170 175 175 150 160 130 b a b b b is an enlarged diagram illustrating region B of the semiconductor device in.is a cross-sectional diagram illustrating a semiconductor device taken along line B-B′ inaccording to an example implementation.is a cross-sectional diagram illustrating a semiconductor device taken along line B-B′ inaccording to another example implementation.is a plan diagram illustrating the second contact plug, the first and second dummy vertical structuresand, the dummy insulating structure, and the second contact insulating structuredisposed at the same level as the second gate electrode portionsin.

5 6 FIGS.andA 1 FIG.B 100 170 175 175 170 160 170 175 170 150 175 b a b b b b b b a Referring to, region B of the semiconductor devicemay include a second contact plugdisposed between the isolation regions MS, first and second dummy vertical structuresandadjacent to the second contact plug, second contact insulating structuressurrounding the second contact plugand the second dummy vertical structureand spaced apart from each other in the third direction (Z-direction) in a lower portion of the gate contact region GP of the second contact plug(e.g., the gate pad region GP of), and dummy insulating structuressurrounding each of the first dummy vertical structuresand spaced apart from each other in the third direction (Z-direction).

170 175 175 170 170 175 175 170 175 1752 1753 1754 170 175 170 1752 170 1753 170 1754 170 175 170 170 b a b b b b a b b a a a b b b a b a b a b b b b. The second contact plugmay be disposed between the isolation regions MS. The first dummy vertical structuresand the second dummy vertical structuresmay be disposed adjacent to the second contact plugand may surround the second contact plug. In an example, one second dummy vertical structureand three first dummy vertical structuresmay surround the second contact plug. For example, the second dummy vertical structure, the 1-2 dummy vertical structure, the 1-3 dummy vertical structure, and the 1-4 dummy vertical structuremay surround the second contact plug. The second dummy vertical structuremay be disposed on the left side on the second contact plug, the 1-2 dummy vertical structuremay be disposed on the right side on the second contact plug, the 1-3 dummy vertical structuremay be disposed on the left side below the second contact plug, and the 1-4 dummy vertical structuremay be disposed on the right side below the second contact plug. However, an example implementation thereof is not limited thereto, and the second dummy vertical structuremay be disposed on the right side on the second contact plug, or may be disposed on the left side or the right side below the second contact plug

175 1752 170 1753 1754 170 b a b a a b The second dummy vertical structureand the 1-2 dummy vertical structuremay be in contact with the first isolation region MS disposed on an upper side of the second contact plugamong the isolation regions MS when viewed on a plane, and the 1-3 dummy vertical structureand the 1-4 dummy vertical structuremay be in contact with the second isolation region disposed on a lower side of the second contact plugamong the isolation regions MS when viewed on a plane.

175 170 175 170 175 b b b b b. The second dummy vertical structuremay include a first portion Sa adjacent to the second contact plug, second portions Sb extending from the first portion Sa and connected by the first portion Sa, and a third portion Sc connecting the second portions Sb and in contact with the isolation region MS. In an example, the first portion Sa of the second dummy vertical structuremay be more adjacent to the second contact plugthan the second portions Sb of the second dummy vertical structure

170 175 160 160 170 170 175 160 120 160 170 175 b b b b b b b b b b 2 FIG. The second contact plugand the second dummy vertical structuremay share the second contact insulating structures. Each of the second contact insulating structuresmay be in contact with the vertical extension portion of the second contact plug(e.g., the vertical extension portionV of) and the second dummy vertical structure, and may be spaced apart from each other in the third direction (Z-direction). The second contact insulating structuresmay be disposed alternately with the interlayer insulating layersin the third direction (Z-direction). Each of the second contact insulating structuresmay be in contact with the second contact plugand the second dummy vertical structurebelow the gate pad region GP.

160 164 170 170 175 166 164 175 162 164 166 b b b b, b b b b b b. Each of the second contact insulating structuresmay include a 2-1 contact insulating patternin contact with the vertical extension portionV of the second contact plugand the first portion Sa of the second dummy vertical structure2-2 contact insulating patternsextending from the 2-1 contact insulating patternand in contact with the second portions Sb of the second dummy vertical structure, and a second contact insulating linersurrounding the 2-1 contact insulating patternand the 2-2 contact insulating patterns

164 170 175 166 175 166 164 b b b b b b b The 2-1 contact insulating patternmay be disposed along a surface profile of an external side surface of the second contact plugand an external side surface of the first portion Sa of the second dummy vertical structure. The 2-2 contact insulating patternsmay be disposed along a surface profile of an external side surface of the second portions Sb of the second dummy vertical structure. When viewed on a plane, the 2-2 contact insulating patternsmay be disposed between the 2-1 contact insulating patternand the isolation region MS.

164 166 162 164 166 162 b b b b b b The 2-1 contact insulating patternmay include a first insulating material, the 2-2 contact insulating patternmay include a second insulating material different from the first insulating material, and the second contact insulating linermay include a third insulating material. For example, the 2-1 contact insulating patternmay include silicon nitride, the 2-2 contact insulating patternmay include silicon oxide, and the second contact insulating linermay include at least one of silicon oxide, silicon carbide, or silicon oxynitride.

1752 1753 1754 150 150 100 150 100 a a a The 1-2 dummy vertical structure, the 1-3 dummy vertical structure, and the 1-4 dummy vertical structuremay be surrounded by dummy insulating structures. The dummy insulating structuredisposed in region B of the semiconductor devicemay correspond to the dummy insulating structuredisposed in region A of the semiconductor device.

160 150 130 130 160 150 b b b 2 FIG. The second contact insulating structuresmay be spaced apart from the dummy insulating structuresin the horizontal direction. When viewed on a plane, the gate electrode(e.g., the second gate electrode portionin) may be disposed between the second contact insulating structureand the dummy insulating structures.

170 175 170 175 170 175 170 1752 b b b a b b b a. In an example, when viewed on a plane, a spacing distance between the second contact plugand the second dummy vertical structuremay be less than a spacing distance between the second contact plugand each of the first dummy vertical structures. For example, the spacing distance between the second contact plugand the second dummy vertical structuremay be less than the spacing distance between the second contact plugand the 1-2 dummy vertical structure

6 FIG.A 130 1 130 160 b b b Referring to, each of the second gate electrode portionsmay have a first height Hin the third direction (Z-direction). To correspond to this, the second gate electrode portionsand the second contact insulating structuresdisposed at the same level may have the same thickness in the third direction (Z-direction).

6 FIG.B 130 130 1 1 130 2 2 1 b b b Referring to, the second gate electrode portions′ may include a 2-1 gate electrode portion_having a first height Hin the third direction (Z-direction) and a 2-2 gate electrode portion_having a second height Hgreater than the first height H.

160 130 1 160 130 2 b b b b Correspondingly, a thickness of the second contact insulating structuredisposed at the same level as the 2-1 gate electrode portion_may be less than a thickness of the second contact insulating structuredisposed at the same level as the 2-2 gate electrode portion_.

100 170 170 175 170 175 170 160 170 160 170 175 150 175 100 170 175 160 170 150 175 170 a b a a b b a a b b b a a a a a a b 1 5 FIGS.A and In example implementations, a semiconductor devicemay include first and second contact plugsand, first dummy vertical structuressurrounding the first contact plug, a second dummy vertical structureadjacent to the second contact plug, first contact insulating structuressurrounding the first contact plug, a second contact insulating structurein contact with the second contact plugand the second dummy vertical structure, and a dummy insulating structuresurrounding the first dummy vertical structures. However, an example implementation thereof is not limited thereto. For example, the semiconductor devicemay include first contact plugs, first dummy vertical structures, first contact insulating structuressurrounding the first contact plugs, and dummy insulating structuressurrounding the first dummy vertical structures, other than the second contact plugsillustrated in.

7 FIG. 1 is an enlarged diagram illustrating region B of the semiconductor device in FIG.A according to another example implementation.

175 160 175 170 b b b b 7 FIG. 5 FIG. Other than the second dummy vertical structures′ and the second contact insulating structures′ in contact with the second dummy vertical structures′ and the second contact plugillustrated in, overlapping descriptions of the components the same as or corresponding to the components illustrated inwill not be provided.

7 FIG. 1 FIG.B 100 170 175 175 170 160 170 175 170 150 175 a b a b b b b b b a Referring to, region B of the semiconductor devicemay include a second contact plugdisposed between the isolation regions MS, first and second dummy vertical structuresand′ adjacent to the second contact plug, second contact insulating structures′ surrounding the second contact plugand the second dummy vertical structures′ and spaced apart from each other in the third direction (Z-direction) in a lower portion of the gate contact region (e.g., the gate pad region GP in) of the second contact plug, and dummy insulating structuressurrounding the first dummy vertical structures, respectively, and spaced apart from each other in the third direction (Z-direction).

175 175 170 170 175 175 170 175 1751 1752 1751 1751 1752 a b b b b a b b b b b b b The first dummy vertical structuresand the second dummy vertical structures′ may be disposed adjacent to the second contact plugand may surround the second contact plug. In an example, two second dummy vertical structures′ and two first dummy vertical structuresmay surround the second contact plug. The second dummy vertical structures′ may include a 2-1 dummy vertical structureand a 2-2 dummy vertical structurespaced apart from the 2-1 dummy vertical structurein the horizontal direction. For example, the 2-1 dummy vertical structureand the 2-2 dummy vertical structuremay be spaced apart from each other in the first horizontal direction (X-direction).

1751 1752 1753 1754 170 1751 170 1752 170 1753 170 1754 170 1751 170 1752 170 1753 170 1754 170 b b a a b b b b b a b a b b b b b a b a b. The 2-1 dummy vertical structure, the 2-2 dummy vertical structure, the 1-3 dummy vertical structure, and the 1-4 dummy vertical structuremay surround the second contact plug. The 2-1 dummy vertical structuremay be disposed on the left side on the second contact plug, the 2-2 dummy vertical structuremay be disposed on the right side on the second contact plug, the 1-3 dummy vertical structuremay be disposed on the left side below the second contact plug, and the 1-4 dummy vertical structuremay be disposed on the right side below the second contact plug. However, an example implementation thereof is not limited thereto. For example, the 2-1 dummy vertical structuremay be disposed on the right side on the second contact plug, and the 2-2 dummy vertical structuremay be disposed on the right side below the second dummy plug. In this case, the 1-3 dummy vertical structuremay be disposed on the left side on the second contact plug, and the 1-4 dummy vertical structuremay be disposed on the left side below the second contact plug

1751 1752 170 1753 1754 170 b b b a a a The 2-1 dummy vertical structureand the 2-2 dummy vertical structuremay be in contact with the first isolation region disposed on an upper side of the second contact plugamong the isolation regions MS when viewed on a plane, and the 1-3 dummy vertical structureand the 1-4 dummy vertical structuremay be in contact with the second isolation region disposed on a lower side of the first contact plugamong the isolation regions MS when viewed on a plane.

1751 1752 170 175 170 175 b b b b b b′. The 2-1 dummy vertical structureand the 2-2 dummy vertical structuremay include a first portion Sa adjacent to the second contact plug, second portions Sb extending from the first portion Sa and connected by the first portion Sa, and a third portion Sc connecting the second portions Sb to each other and in contact with the isolation region MS. In an example, the first portions Sa of the second dummy vertical structures′ may be more adjacent to the second contact plugthan the second portions Sb of the second dummy vertical structures

160 120 170 170 175 160 170 1751 1752 170 1751 1752 160 b b b b b b b b b b b′. 1 FIG.B 2 FIG. The second contact insulating structures′ may be disposed alternately with the interlayer insulating layers (e.g., the interlayer insulating layersin) and in contact with the vertical extension portions (e.g., the vertical extension portionV in) of the second contact plugand the second dummy vertical structures′, and may be spaced apart from each other in the third direction (Z-direction). The second contact insulating structure′ may be in contact with the second contact plug, the 2-1 dummy vertical structure, and the 2-2 dummy vertical structure. The second contact plug, the 2-1 dummy vertical structure, and the 2-2 dummy vertical structuremay share the second contact insulating structures

160 164 170 170 1751 1752 166 1751 168 1752 162 164 166 168 b b b b b b b b b b b b b′. 2 FIG. Each of the second contact insulating structures′ may include a 2-1 contact insulating pattern′ in contact with a vertical extension portion (e.g., vertical extension portionV in) of the second contact plug, a first portion Sa of the 2-1 dummy vertical structure, and in contact with the first portion Sa of the 2-2 dummy vertical structure, a 2-2 contact insulating pattern′ in contact with the second portions Sb of the 2-1 dummy vertical structure, a 2-3 contact insulating pattern′ in contact with the second portions Sb of the 2-2 dummy vertical structure, and a second contact insulating liner′ surrounding the 2-1 contact insulating pattern′, the 2-2 contact insulating pattern′, and the 2-3 contact insulating pattern

164 170 1751 1752 166 164 1751 168 164 1752 166 168 164 166 168 b b b b b b b b b b b b b b b The 2-1 contact insulating pattern′ may be disposed along surface profiles of an external side surface of the second contact plug, an external side surface of the first portion Sa of the 2-1 dummy vertical structure, and an external side surface of the first portion Sa of the 2-2 dummy vertical structure. The 2-2 contact insulating patterns′ may extend from a side surface of the 2-1 contact insulating pattern′ and may be disposed along a surface profile of an external side surface of the second portions Sb of the 2-1 dummy vertical structure. The 2-3 contact insulating patterns′ may extend from a side surface of the 2-1 contact insulating pattern′ and may be disposed along a surface profile of an external side surface of the second portions Sb of the 2-2 dummy vertical structure. The 2-2 contact insulating patterns′ and the 2-3 contact insulating patterns′ may be disposed between the 2-1 contact insulating pattern′ and the isolation region MS. The 2-2 contact insulating patterns′ and the 2-3 contact insulating patterns′ may be spaced apart from each other in the first direction (X-direction).

164 166 168 162 164 166 168 162 b b b b b b b b The 2-1 contact insulating pattern′ may include the first insulating material, and the 2-2 contact insulating patterns′ and the 2-3 contact insulating patterns′ may include a second insulating material different from the first insulating material. The second contact insulating liner′ may include a third insulating material. For example, the 2-1 contact insulating pattern′ may include silicon nitride, the 2-2 contact insulating patterns′ and the 2-3 contact insulating patterns′ may include silicon oxide, and the second contact insulating liner′ may include at least one of silicon oxide, silicon carbide, or silicon oxynitride.

1753 1754 150 150 100 150 100 a a a 5 FIG. Each of the 1-3 dummy vertical structureand the 1-4 dummy vertical structuremay be surrounded by the dummy insulating structures. The dummy insulating structuredisposed in region B of the semiconductor devicemay correspond to the dummy insulating structuredisposed in region B of the semiconductor devicein.

160 150 130 130 160 150 b b b 2 FIG. The second contact insulating structures′ may be spaced apart from the dummy insulating structuresin the horizontal direction. When viewed on a plane, the gate electrode(e.g., the second gate electrode portionin) may be disposed between the second contact insulating structure′ and the dummy insulating structures.

170 1751 170 1753 1754 b b b a a In an example, when viewed on a plane, a spacing distance between the second contact plugand the 2-1 dummy vertical structuremay be less than a spacing distance between the second contact plugand the 1-3 dummy vertical structure(and the 1-4 dummy vertical structure).

175 1751 1752 175 175 170 170 170 160 170 175 b b b b b b b b b b b′. In another example implementation, the second dummy vertical structures′ may include the 2-1 dummy vertical structuresand the 2-2 dummy vertical structuresas illustrated, but the second dummy vertical structure′ may include three dummy vertical structures. In this case, the second dummy vertical structures′ may include the 2-1 dummy vertical structure, the 2-2 dummy vertical structure, and the 2-3 dummy vertical structure, and the 2-1 dummy vertical structure may be disposed on the upper left side of the second contact plug, the 2-2 dummy vertical structure may be disposed on the upper right side of the second contact plug, and the 2-3 dummy vertical structure may be disposed on the lower left side of the second contact plug. Each of the second contact insulating structures′ may be in contact with the second contact plugand three 2-1 dummy vertical structures, 2-2 dummy vertical structures, and 2-3 dummy vertical structures included in the second dummy vertical structures

100 170 170 175 170 175 170 160 170 160 170 175 150 175 a a b a a b b a a b b b a. In example implementations, a semiconductor devicemay include first and second contact plugsand, first dummy vertical structuressurrounding the first contact plug, a second dummy vertical structure′ adjacent to the second contact plug, first contact insulating structuressurrounding the first contact plug, second contact insulating structures′ in contact with the second contact plugand the second dummy vertical structure′, and a dummy insulating structuresurrounding the first dummy vertical structures

8 10 FIGS.to 8 10 FIGS.to 1 FIG.A are cross-sectional diagrams illustrating a method of manufacturing a semiconductor device according to an example implementation.each illustrate cross-sections along line IV-IV′ of the semiconductor device in.

8 FIG. 220 290 201 Referring to, circuit devices, a circuit interconnection structure, and a peripheral region insulating layerincluded in the peripheral circuit region PERI may be formed on the substrate.

210 201 222 225 201 210 222 225 222 225 224 222 225 205 201 222 225 224 205 The device isolation layersmay be formed in the substrate, and a circuit gate dielectric layerand a circuit gate electrodemay be formed in order on the substrate. The device isolation layersmay be formed, for example, by a shallow trench isolation (STI) process. The circuit gate dielectric layerand the circuit gate electrodemay be formed using atomic layer deposition (ALD) or chemical vapor deposition (CVD). The circuit gate dielectric layermay be formed of silicon oxide, and the circuit gate electrodemay be formed of at least one of polycrystalline silicon or a metal silicide layer, but an example implementation thereof is not limited thereto. Thereafter, a spacer layermay be formed on both sidewalls of the circuit gate dielectric layerand the circuit gate electrode, and impurity regionsmay be formed in the substrateon both sides of the circuit gate dielectric layerand the circuit gate electrode. In example implementations, the spacer layermay be formed in a plurality of layers. The impurity regionsmay be formed by performing an ion implantation process.

270 290 280 Among the circuit interconnection structures, the circuit contact plugsmay be formed by partially forming a peripheral region insulating layer, removing a portion thereof by etching, and filling the conductive material. The circuit interconnection linesmay be formed, for example, by depositing a conductive material and patterning the conductive material.

290 290 The peripheral region insulating layermay be formed in a plurality of insulating layers. A respective portion of the peripheral region insulating layermay be formed in each of processes for forming the circuit interconnection structure. Accordingly, a peripheral circuit region PERI may be formed.

101 110 104 121 119 119 119 a b c On the peripheral circuit region PERI, a plate layer, a horizontal insulating layer, a second horizontal conductive layer, and a substrate insulating layer, in which a memory cell region CELL is provided, may be formed, and mold structure MSS and first to third vertical sacrificial layers,, andmay be formed.

101 290 101 101 The plate layermay be formed on the peripheral region insulating layer. The plate layermay be formed of, for example, polycrystalline silicon and may be formed by a CVD process. The polycrystalline silicon included in the plate layermay include impurities.

101 291 280 291 170 101 290 280 101 101 291 101 1 FIG.B When the plate layeris formed, landing padsmay be formed together on the circuit interconnection linesin an uppermost portion. The landing padsmay be formed in the region in which a lower end of the contact plugs(see) is disposed. First, before forming the plate layer, a portion of the peripheral region insulating layermay be removed from the circuit interconnection linesof the uppermost portion to form openings. When forming the plate layer, the openings may be filled with a material included in the plate layer, thereby forming the landing pads. The openings may be formed, for example, with a ground via for connecting the plate layerto the circuit interconnection structure.

111 112 110 101 110 102 111 112 111 120 112 118 110 2 1 FIG.B The first and second horizontal insulating layersandincluded in the horizontal insulating layermay be alternately stacked on the plate layer. The horizontal insulating layermay be layers in which a portion thereof is replaced with the first horizontal conductive layerinthrough a subsequent process. The first horizontal insulating layersmay include a material different from a material of the second horizontal insulating layer. For example, the first horizontal insulating layersmay be formed of the same material as the interlayer insulating layers, and the second horizontal insulating layermay be formed of the same material as the subsequent sacrificial insulating layersP. Partial regions of the horizontal insulating layer, for example, a portion of the second region R, may be removed by a pattern process.

104 110 101 110 The second horizontal conductive layermay be formed on the horizontal insulating layer, and may be in contact with the plate layerin the region from which the horizontal insulating layeris removed.

121 101 170 121 101 110 104 121 104 The substrate insulating layermay be formed to penetrate the plate layerin partial regions including the region in which the contact plugsare disposed. The substrate insulating layermay be formed by removing a portion of the plate layer, the horizontal insulating layerand the second horizontal conductive layer, and filling an insulating material. After filling the insulating material, a planarization process may be further performed using a chemical mechanical polishing (CMP) process. Accordingly, an upper surface of the substrate insulating layermay be substantially coplanar with an upper surface of the second horizontal conductive layer.

118 120 104 121 1 1 FIG.B Thereafter, the first mold structure MSa may be formed by alternately stacking sacrificial insulating layersP and interlayer insulating layerson the second horizontal conductive layerand the substrate insulating layerat a height at which the first stack structure GS(see) is disposed.

118 130 118 120 120 120 118 120 120 118 1 FIG.B The sacrificial insulating layersP may be layers in which at least a portion is replaced by gate electrodes(see) through a subsequent process. The sacrificial insulating layersP may be formed of a material different from that of the interlayer insulating layers, and may be formed of a material etched with etch selectivity with respect to the interlayer insulating layersunder specific etch conditions. For example, the interlayer insulating layermay be formed of at least one of silicon oxide and silicon nitride, and the sacrificial insulating layersP may be formed of a material different from a material of the interlayer insulating layer, selected from among silicon, silicon oxide, silicon carbide, and silicon nitride. In example implementations, the number of the interlayer insulating layersand the sacrificial insulating layersP and thicknesses thereof may be varied from the illustrated example.

118 120 2 118 118 118 118 118 The gate pad regions GP may be formed by repeating a photolithography process and an etching process for the sacrificial insulating layersP and the interlayer insulating layers. The gate pad regions GP may be formed in the second region R, and may be formed such that the sacrificial insulating layersP of the upper portion may include a region extending shorter than the sacrificial insulating layersP of the lower portion. In the gate pad regions GP, asymmetric step structures may be formed such that upper surfaces and ends of the plurality of sacrificial insulating layersP may be exposed upwardly. Sacrificial insulating layersP may be further formed on the step structure of the gate pad regions GP such that the sacrificial insulating layersP positioned in an uppermost portion in each region may have a relatively great thickness.

192 118 120 119 170 175 119 119 a a a 1 FIG.B 1 FIG.C Thereafter, the first cell region insulating layercovering the sacrificial insulating layersP and the interlayer insulating layersin the first mold structure MSa may be formed. The first vertical sacrificial layersmay be formed in positions corresponding to the first channel structures CH, the contact plugsin, and the dummy vertical structuresin. The first vertical sacrificial layersmay be formed by forming holes to penetrate the first mold structure MSa, depositing sacrificial layer material in the holes, and performing a planarization process. The first vertical sacrificial layersmay include, for example, carbon or a carbon-based material, but an example implementation thereof is not limited thereto.

119 119 119 119 119 119 119 119 119 119 2 1 170 175 b c a b a c b a b c The second mold structure MSb, the second vertical sacrificial layers, the third mold structure MSc, and the third vertical sacrificial layersmay be formed on the first mold structure MSa in the same manner as the first mold structure MSa and the first vertical sacrificial layers, respectively. The second vertical sacrificial layersmay be formed to be connected to the first vertical sacrificial layers, and the third vertical sacrificial layersmay be formed to be connected to the second vertical sacrificial layers. In this process, the first to third vertical sacrificial layers,, andformed in the second region Rmay be formed with a width similar to a width in the first region R, and may be formed with a width less than widths of the contact plugsand the dummy vertical structures.

9 FIG. Referring to, channel structures CH penetrating the mold structure MSS may be formed, and first holes OH may be formed.

1 119 119 119 1 145 140 147 149 a b c A mask layer exposing only the first region Rmay be formed. The channel structures CH may be formed by forming lower channel holes by removing the first to third vertical sacrificial layers,, andfrom the first region R, and sequentially depositing at least a portion of the gate dielectric layer, the channel layer, the channel filling insulating layer, and the channel padin the lower channel holes.

145 145 101 140 145 147 149 The gate dielectric layermay be formed to have a uniform thickness using an ALD or CVD process. In this process, the gate dielectric layermay be formed entirely or partially, and a portion extending vertically along the channel structures CH to the plate layermay be formed in this process. The channel layermay be formed on the gate dielectric layerin the lower channel holes. The channel filling insulating layermay be formed to fill the lower channel holes and may be an insulating material. The channel padmay be formed of a conductive material, for example, polycrystalline silicon.

119 119 119 2 291 a b c The first holes OH may be formed by selectively removing the first to third vertical sacrificial layers,, andfrom the second region R, and further removing the exposed landing pads.

119 119 119 2 119 119 119 119 280 291 a b c a b c c 9 FIG. First, a mask layer exposing the first to third vertical sacrificial layers,, andin the second region Rmay be formed, and the first to third vertical sacrificial layers,, andexposed through the mask layer may be selectively removed. When the mask layer is formed to have openings larger than upper surfaces of the third vertical sacrificial layers, the first holes OH may have an enlarged width at upper ends thereof as illustrated in. Circuit interconnection linesmay be exposed through bottom surfaces of the first holes OH. In some example implementations, the landing padsmay not be removed in this process and may be removed in a subsequent process.

10 FIG. 192 194 190 Referring to, after the first holes OH are enlarged in the horizontal direction, the first preliminary insulating linerP, the first preliminary insulating patternP, and the vertical sacrificial layerP may be formed in the first holes OH.

118 120 118 120 118 The first holes OH may be enlarged in the horizontal direction by removing a portion of the sacrificial insulating layersP and the interlayer insulating layersexposed through the first holes OH. During the process, the sacrificial insulating layersP may be removed relatively longer in the horizontal direction than the interlayer insulating layers. Thereafter, the sacrificial insulating layersP may be further removed around the first holes OH, thereby forming tunnel portions.

192 192 194 192 190 190 194 A first preliminary insulating linerP may be formed by depositing an insulating material in the first holes OH and tunnel portions. The first preliminary insulating linerP may be conformally deposited on internal sidewalls of the tunnel portions, and the first preliminary insulating patternP may fill the tunnel portions on the first preliminary insulating linerP in the contact tunnel portions and may be formed on sidewalls of the first holes OH. A vertical sacrificial layerP may fill the first holes OH between the sidewalls of the first holes OH. The vertical sacrificial layerP may include a different material from that of the first preliminary insulating patternP, and may include, for example, carbon (C).

10 FIG. 118 120 Referring to region D in, in a process of enlarging the first holes OH in the horizontal direction by removing a portion of the sacrificial insulating layersP and the interlayer insulating layersexposed through the first holes OH, the first holes OH spaced apart from each other in the horizontal direction may be connected to each other through the tunnel portions. A distance between central axes of the first holes OH connected through the tunnel portions extending in the third direction (Z-direction) may be less than a distance between central axes of the first holes OH spaced apart from each other in the horizontal direction extending in the third direction (Z-direction).

192 194 190 The first holes OH connected through the tunnel portions may share the first preliminary insulating linerP and the first preliminary insulating patternP, and the vertical sacrificial layersP extending in the third direction (Z-direction) may be spaced apart from each other in the horizontal direction.

11 18 FIGS.A toB are diagrams illustrating a method of manufacturing a semiconductor device according to an example implementation.

11 FIG.A 12 FIG.A 13 FIG.A 14 FIG. 15 FIG.A 16 FIG.A 17 FIG.A 18 FIG.A 10 FIG. 5 FIG. 192 194 ,,,,,,, andare plan diagrams illustrating processes after the process of forming first holes sharing the first preliminary insulating linerP and the first preliminary insulating patternP inand first holes spaced apart from each other in the horizontal direction, respectively, and are plan diagrams corresponding to.

11 FIG.B 12 FIG.B 13 FIG.B 15 FIG.B 16 FIG.B 17 FIG.B 18 FIG.B 11 FIG.A 12 FIG.A 13 FIG.A 15 FIG.A 16 FIG.A 17 FIG.A 18 FIG.A 6 FIG.A ,,,,,, andare cross-sectional diagrams taken along line B-B′ of the semiconductor device in,,,,,, and, and are cross-sectional diagrams corresponding to.

11 11 FIGS.A andB 10 FIG. 10 FIG. 192 194 1 192 1 162 194 164 190 195 190 1 190 2 3 4 192 194 152 154 2 3 4 190 2 190 3 190 4 190 1 a b c d Referring to, the first holes OH sharing the first preliminary insulating linerP and the first preliminary insulating patternP inmay be referred to as a first contact hole CPH and a first dummy hole DH, and the first preliminary insulating linerP in the first contact hole CPH and the first dummy hole DHmay be referred to as a second preliminary contact insulating linerP, and the first preliminary insulating patternP may be referred to as a second preliminary contact insulating patternP. The vertical sacrificial layerP in the first contact hole CPH may be referred to as a first contact vertical sacrificial layerP. The vertical sacrificial layerP in the first dummy hole DHmay be referred to as a first dummy sacrificial layer. The first holes OH spaced apart from each other inmay be referred to as second, third, and fourth dummy holes DH, DH, and DH, and the first preliminary insulating linerP and the first preliminary insulating patternP formed in the first holes OH spaced apart from each other may be referred to as preliminary dummy insulating linerP and first preliminary dummy insulating patternP in the second, third, and fourth dummy holes DH, DH, and DH, respectively. The second dummy sacrificial layerin the second dummy hole DH, the third dummy sacrificial layerin the third dummy hole DH, and the fourth dummy sacrificial layerin the fourth dummy hole DHmay correspond to the vertical sacrificial layerP in the first holes OHspaced apart from each other.

170 1 175 2 3 4 1752 1753 1754 b b a a a 5 FIG. 5 FIG. 5 FIG. The first contact hole CPH may correspond to the second contact plugin, the first dummy hole DHmay correspond to the second dummy vertical structurein, and the second, third, and fourth dummy holes DH, DH, and DHmay correspond to the 1-2 dummy vertical structure, the 1-3 dummy vertical structure, and the 1-4 dummy vertical structurein.

1 2 3 4 162 164 1 10 FIG. Since the first contact hole CPH is disposed such that a spacing distance with the first dummy hole DHis less than a spacing distance with the second, third, and fourth dummy holes DH, DH, and DH, the first holes OH inmay be connected in the process of being enlarged in the horizontal direction and may share the second preliminary contact insulating linerP and the second preliminary contact insulating patternP. Accordingly, the first contact hole CPH and the first dummy hole DHmay be physically connected to each other.

2 3 4 152 154 2 3 4 162 152 118 152 162 The second, third, and fourth dummy holes DH, DH, and DHmay be spaced apart from each other in the horizontal direction, and the preliminary dummy insulating linerP and the first preliminary dummy insulating patternP disposed in the tunnel portions of the second, third, and fourth dummy holes DH, DH, and DH, respectively, may also be spaced apart from each other in the horizontal direction. The second preliminary contact insulating linerP and the preliminary dummy insulating linersP may be spaced apart from each other in the horizontal direction, and sacrificial insulating layersP may be formed between the preliminary dummy insulating linersP and the second preliminary contact insulating linerP.

12 12 FIGS.A andB 1 190 1 190 2 190 3 190 4 190 190 a b c d a d Referring to, the first openings OPNmay be formed by removing the first dummy sacrificial layerin the first dummy hole DH, the second dummy sacrificial layerin the second dummy hole DH, the third dummy sacrificial layerin the third dummy hole DH, and the fourth dummy sacrificial layerin the fourth dummy hole DH. The first to fourth dummy sacrificial layerstomay be removed by a wet etching process.

13 13 FIGS.A andB 175 175 1 175 152 154 2 3 4 175 1752 2 1753 3 1754 4 a b a a a a a Referring to, preliminary dummy vertical structures_P and_P may be formed by filling the first openings OPNwith an insulating material. The first preliminary dummy vertical structures_P may be formed as dummy vertical structures surrounded by a preliminary dummy insulating linerP and a first preliminary dummy insulating patternP by filling the second dummy hole DH, the third dummy hole DH, and the fourth dummy hole DHwith the insulating material. The first preliminary dummy vertical structures_P may include 1-2 preliminary dummy vertical structures_P formed in the second dummy hole DH, 1-3 preliminary dummy vertical structures_P formed in the third dummy hole DH, and 1-4 preliminary dummy vertical structures_P formed in the fourth dummy hole DH.

175 162 164 1 b The second preliminary dummy vertical structure_P may be formed as a dummy vertical structure surrounded by the second preliminary contact insulating linerP and the second preliminary contact insulating patternP by filling the insulating material in the first dummy hole DH.

13 FIG.A 14 FIG. 118 1752 154 1752 152 154 175 164 175 162 164 195 a a b b Referring toand, by removing, in the vertical direction, a portion extending in the first direction (X-direction), and overlapping a portion of the sacrificial insulating layersP, a portion of the 1-2 preliminary dummy vertical structure_P, a portion of the first preliminary dummy insulating patternP surrounding the 1-2 preliminary dummy vertical structure_P, a portion of the preliminary dummy insulating linerP surrounding the first preliminary dummy insulating patternP, a portion of the second preliminary dummy vertical structure_P, a portion of the second preliminary contact insulating patternP surrounding the second preliminary dummy vertical structure_P, and a portion of the second preliminary contact insulating linerP surrounding the second preliminary contact insulating patternP, when viewed on a plane, an isolation region MS (e.g., the first isolation region) may be formed on an upper side of the first contact vertical sacrificial layerP.

118 1753 1754 154 1753 1754 152 154 195 a a a a By removing, in the vertical direction, a portion extending in the first direction (X-direction), and overlapping a portion of the sacrificial insulating layersP, a portion of the 1-3 and 1-4 preliminary dummy vertical structures_P and_P, a portion of the first preliminary dummy insulating patternP surrounding the 1-3 and 1-4 preliminary dummy vertical structures_P and_P, and a portion of the preliminary dummy insulating linerP surrounding the first preliminary dummy insulating patternP, when viewed on a plane, an isolation region MS (e.g., second isolation region) may be formed on a lower side of the first contact vertical sacrificial layerP.

175 175 175 175 a a b b As the isolation regions MS are formed, a portion of the first preliminary dummy vertical structure_P may be removed such that a first dummy vertical structuremay be formed, and a portion of the second preliminary dummy vertical structure_P may be removed such that a second dummy vertical structuremay be formed.

175 175 1752 1752 1753 1753 1754 1754 b b a a a a a a. As the isolation regions MS are formed, the second preliminary dummy vertical structure_P may be formed as the second dummy vertical structure, and the 1-2 preliminary dummy vertical structure_P may be formed as the 1-2 dummy vertical structure. The 1-3 preliminary dummy vertical structure_P may be formed as the 1-3 dummy vertical structure, and the 1-4 preliminary dummy vertical structure_P may be formed as the 1-4 dummy vertical structure

13 FIG.A 14 FIG. 175 175 a b Referring toand, when viewed on a plane, a maximum width of each of the first preliminary dummy vertical structures_P and the second preliminary dummy vertical structure_P may have a first size Ra.

175 175 a b When viewed on a plane, a maximum width of each of the first dummy vertical structuresand the second dummy vertical structuremay have a second size Rb less than the first size Ra. The second size Rb may be larger than half the first size Ra.

154 152 154 152 175 a a The first preliminary dummy insulating patternP and the preliminary dummy insulating linerP may be partially cut out and may be formed as a first dummy insulating pattern″ and a dummy insulating linersurrounding the first dummy vertical structures, respectively.

164 162 164 162 175 b b b The second preliminary contact insulating patternP and the second preliminary contact insulating linerP may be partially cut out and may be formed as a second contact insulating pattern″ and a second contact insulating linersurrounding the second dummy vertical structures, respectively.

15 FIG.A 15 FIG.B 154 175 152 1 164 175 162 1 2 154 164 2 a a b b b b Referring toand, a first dummy insulating pattern″ disposed between the first dummy vertical structuresand the dummy insulating linermay be removed by a first width W, and the second contact insulating pattern″ formed between the second dummy vertical structuresand the second contact insulating linermay be removed by the first width W, such that second openings OPNmay be formed. The first dummy insulating patternand the 2-1 contact insulating patternmay be exposed through the second openings OPN.

118 152 162 1 3 118 3 b The sacrificial insulating layers″ between the dummy insulating linerand the second contact insulating linermay be removed by the first width W, such that third openings OPNmay be formed, and the sacrificial insulating layersmay be exposed through the third openings OPN.

1 154 164 118 2 3 154 164 118 1 a b a b 14 FIG. 13 FIG.A By etching the first width Win the horizontal direction through a pull-back process or etching process with respect to a side surface of the first dummy insulating pattern″, a side surface of the second contact insulating pattern″, and a side surface of the sacrificial insulating layersP exposed through the isolation regions MS in, second openings OPNand third openings OPNmay be formed. The etching degree of a side surface of the first dummy insulating pattern″, a side surface of the second contact insulating pattern″, and a side surface of the sacrificial insulating layers″ may be controlled by controlling the pull-back process time. The first width Wmay be less than half the first size Ra in.

175 152 2 3 154 118 a a A portion of the first dummy vertical structuresand a portion of the dummy insulating linermay be exposed through the second openings OPNand the third openings OPNby a pull-back process for a side surface of the first dummy insulating pattern″ and a side surface of the sacrificial insulating layers″ exposed through the isolation regions MS.

175 162 2 3 164 118 b b b A portion of the second dummy vertical structureand a portion of the second contact insulating linermay be exposed through the second openings OPNand the third openings OPNby a pull-back process for a side surface of the second contact insulating pattern″ and a side surface of the sacrificial insulating layers″ exposed through the isolation regions MS.

16 16 FIGS.A andB 166 2 3 Referring to, an insulating patternP may be formed in the second openings OPNand the third openings OPN.

2 3 166 2 3 166 Since a width of each of the second openings OPNis relatively less than a width of each of the third openings OPN, the insulating patternP may fill the second openings OPNand may be formed be conformally along an internal sidewall of the third openings OPN. The insulating patternP may be silicon oxide.

17 17 FIGS.A andB 175 175 4 166 152 162 166 164 164 164 160 164 166 162 a b b b b b b b b b Referring to, a planarization process may be performed such that a side surface of the first dummy vertical structuresand a side surface of the second dummy vertical structuresmay be exposed, and the fourth openings OPNmay be formed by removing the insulating patternP formed between the dummy insulating linerand the second contact insulating liner. The insulating patternP may be disposed on a side surface of the 2-1 contact insulating pattern, and may be formed as 2-1 contact insulating patterns, thereby preventing the 2-1 contact insulating patternfrom being exposed. Accordingly, the second contact insulating structuresincluding the 2-1 contact insulating pattern, the 2-2 contact insulating patterns, and the second contact insulating linermay be formed.

166 154 156 154 150 154 156 152 The insulating patternP may be disposed on a side surface of the first dummy insulating patternand may be formed as second dummy insulating patterns, thereby preventing the side surface of the first dummy insulating patternfrom being exposed. Accordingly, a dummy insulating structureincluding the first dummy insulating pattern, the second dummy insulating patterns, and the dummy insulating linermay be formed.

18 18 FIGS.A andB 5 118 6 195 118 164 166 154 156 118 164 170 175 170 175 b b b b b b b Referring to, a fifth opening OPNmay be formed by removing the sacrificial insulating layers, and a sixth opening OPNmay be formed by removing the first contact vertical sacrificial layerP. In the process of removing the sacrificial insulating layers, the 2-1 contact insulating patternmay not be removed by the 2-2 contact insulating patterns, and the first dummy insulating patternmay not be removed by the second dummy insulating pattern. Accordingly, in the process of removing the sacrificial insulating layersand replacing the layers with a conductive material, the 2-1 contact insulating patternsmay surround the side surface of the second contact plugand the side surface of the second dummy vertical structure, such that the second contact plugand the second dummy vertical structuremay be prevented from being conductive through the conductive material.

1 FIG.B 5 FIG. 5 130 6 170 180 170 100 b Thereafter, referring toand, a conductive material may be formed in the fifth opening OPN, thereby forming a gate electrode, and a conductive material may be formed in the sixth opening OPN, thereby forming a second contact plug. By forming studsconnected to upper ends of the contact plugsand the channel structures CH, a semiconductor devicemay be manufactured.

19 FIG. 1 FIG.A is a cross-sectional diagram illustrating a semiconductor device taken along line I-I′ inaccording to an example implementation.

19 FIG. 100 1 2 Referring to, a semiconductor device′ may include a memory cell structure Sand a peripheral circuit structure Sbonded to each other by a wafer bonding method.

1 FIG.B 2 2 295 298 299 295 280 298 295 298 198 1 298 1 2 198 298 280 The description of the peripheral circuit region PERI described above with reference tomay be applied to the peripheral circuit structure S. The peripheral circuit structure Smay further include second bonding viasand second bonding metal layers, and a second bonding insulating layer, which are bonding structures. The second bonding viasmay be connected to circuit interconnection linesin an uppermost portion. At least a portion of the second bonding metal layermay be connected to the second bonding vias. The second bonding metal layermay be connected to the first bonding metal layersof the memory cell structure S. The second bonding metal layersmay provide an electrical connection path for bonding the memory cell structure Sand the peripheral circuit structure Stogether with the first bonding metal layers. In another example, a portion of the second bonding metal layersmay not be connected to circuit interconnection linesof the lower portion and may be disposed only for bonding.

295 298 299 298 299 298 The second bonding viasand the second bonding metal layersmay include a conductive material, for example, copper (Cu). The second bonding insulating layermay be disposed around the second bonding metal layers. The second bonding insulating layermay also function as a diffusion barrier for the second bonding metal layersand may include, for example, at least one of SiN, SiON, SiCN, SiOC, SiOCN, and SiO.

1 1 122 185 195 198 199 1 106 101 122 1 FIG.B In case there is no other description for the memory cell structure S, the description of the memory cell region CELL described above with reference tomay be applied. The memory cell structure Smay further include a substrate insulating layer, cell interconnection lines, a bonding structure of the first bonding vias, first bonding metal layersand a first bonding insulating layer. In an example, the memory cell structure Smay further include a passivation layercovering an upper surface of the plate layerand an upper surface of the substrate insulating layers.

122 101 1 101 2 122 1 101 The substrate insulating layermay be disposed above the gate structure GS, disposed between the plate layerand the gate structure GS on the first region R, and disposed at the same level as the plate layeron the second region R. The channel structure CH may penetrate the gate structure GS and the substrate insulating layerin the first region Rand may be positioned in the plate layer.

122 101 1 1 2 101 2 The substrate insulating layermay be disposed under the plate layeron the first region R, extends from the first region Rto the second region R, and may be disposed on the same level as the plate layeron the second region R.

185 180 185 The cell interconnection linesmay be connected to the studs. However, in example implementations, the number of layers and arrangement of the plugs and the interconnection lines included in the cell interconnection structure may be varied. The cell interconnection linesmay be formed of a conductive material, and may include at least one of tungsten (W), aluminum (Al), and copper (Cu), for example.

195 198 185 195 185 198 198 298 2 199 299 2 195 198 199 The first bonding viasand the first bonding metal layersmay be disposed below the cell interconnection linesin the lowermost portion. The first bonding viasmay connect the cell interconnection linesto the first bonding metal layers, and the first bonding metal layersmay be bonded to the second bonding metal layersof the peripheral circuit structure S. The first bonding insulating layermay be bonded to the second bonding insulating layerof the peripheral circuit structure S. The first bonding viasand the first bonding metal layersmay include a conductive material, for example, copper (Cu). The first bonding insulating layermay include at least one of, for example, SiO, SiN, SiCN, SiOC, SiON, and SiOCN.

1 2 198 298 199 299 198 298 199 299 1 2 The first and second semiconductor structures Sand Smay be bonded to each other by bonding between the first bonding metal layersand the second bonding metal layersand by bonding between the first bonding insulating layerand the second bonding insulating layer. The bonding between the first bonding metal layersand the second bonding metal layersmay be, for example, copper (Cu)-copper (Cu) bonding, and the bonding between the first bonding insulating layerand the second bonding insulating layermay be, for example, dielectric-dielectric bonding, such as SiCN—SiCN bonding. The first and second semiconductor structures Sand Smay be bonded to each other by hybrid bonding including copper (Cu)-copper (Cu) bonding and dielectric-dielectric bonding.

106 101 100 106 122 1 2 170 122 170 101 The passivation layermay be disposed on an upper surface of the plate layerand may protect the semiconductor device′. The passivation layermay include at least one of an insulating material, for example, silicon oxide, silicon nitride, and silicon carbide. The substrate insulating layermay be widely disposed in the first region Rand the second region Rto cover upper ends of the contact plugs. However, in example implementations, the arrangement of the substrate insulating layermay be varied in a range in which the contact plugsare electrically isolated from the plate layer.

20 FIG. is a diagram illustrating a data storage system including a semiconductor device according to an example implementation.

20 FIG. 1000 1100 1200 1100 1000 1100 1000 1100 Referring to, a data storage systemmay include a semiconductor deviceand a controllerelectrically connected to the semiconductor device. The data storage systemmay be implemented as a storage device including one or a plurality of semiconductor devicesor an electronic device including a storage device. For example, the data storage systemmay be implemented as a solid state drive device (SSD) including one or a plurality of semiconductor devices, a universal serial bus (USB), a computing system, a medical device, or a communication device.

1100 1100 1100 1100 1100 1100 1100 1100 1110 1120 1130 1100 1 2 1 2 1 1 FIGS.A toD The semiconductor devicemay be implemented as a non-volatile memory device, such as, for example, the NAND flash memory device described in the aforementioned example implementation with reference to. The semiconductor devicemay include a first structureF and a second structureS on the first structureF. In the example implementations, the first structureF may be disposed on the side of the second structureS. The first structureF may be implemented as a peripheral circuit structure including a decoder circuit, a page buffer, and a logic circuit. The second structureS may be implemented as a memory cell structure including a bitline BL, a common source line CSL, wordlines WL, first and second gate upper lines ULand UL, first and second gate lower lines LLand LLand memory cell strings CSTR disposed between the bitline BL and the common source line CSL.

1100 1 2 1 2 1 2 1 2 1 2 1 2 In the second structureS, each of the memory cell strings CSTR may include lower transistors LTand LTadjacent to the common source line CSL, upper transistors UTand UTadjacent to the bitline BL, and a plurality of memory cell transistors MCT disposed between the lower transistors LTand LTand the upper transistors UTand UT. The number of lower transistors LTand LTand the number of upper transistors UTand UTmay be varied in the example implementations.

1 2 1 2 1 2 1 2 1 2 1 2 In the example implementations, the upper transistors UTand UTmay include a string select transistor, and the lower transistors LTand LTmay include a ground select transistor. The gate lower lines LLand LLmay be configured as gate electrodes of the lower transistors LTand LT, respectively. The wordlines WL may be configured as gate electrodes of the memory cell transistors MCT, and the gate upper lines ULand ULmay be configured as gate electrodes of the upper transistors UTand UT, respectively.

1 2 1 2 1 2 1 2 1 2 In the example implementations, the lower transistors LTand LTmay include a lower erase control transistor LTand a ground select transistor LTconnected to each other in series. The upper transistors UTand UTmay include a string select transistor UTand an upper erase control transistor UTconnected to each other in series. At least one of the lower erase control transistor LTor the upper erase control transistor UTmay be used in an erase operation for erasing data stored in the memory cell transistors MCT using a GIDL phenomenon.

1 2 1 2 1110 1115 1100 1100 1120 1125 110 1100 The common source line CSL, the first and second gate lower lines LLand LL, the wordlines WL, and the first and second gate upper lines ULand ULmay be electrically connected to the decoder circuitthrough first connection interconnectionsextending from the first structureF to the second structureS. The bitlines BL may be electrically connected to the page bufferthrough second connection interconnectionsextending from the first structureF to the second structureS.

1100 1110 1120 1110 1120 1130 1100 1200 1101 1130 1101 1130 1135 1100 1100 In the first structureF, the decoder circuitand the page buffermay perform a control operation on at least one selected memory cell transistor among the plurality of memory cell transistors MCT. The decoder circuitand the page buffermay be controlled by the logic circuit. The semiconductor devicemay communicate with the controllerthrough the input/output padelectrically connected to the logic circuit. The input/output padsmay be electrically connected to the logic circuitthrough an input/output connection lineextending from the first structureF to the second structureS.

1200 1210 1220 1230 1000 1100 1200 1100 The controllermay include a processor, a NAND controller, and a host interface. In the example implementations, the data storage systemmay include a plurality of semiconductor devices, and in this case, the controllermay control the plurality of semiconductor devices.

1210 1000 1200 1210 1100 1220 1220 1221 1100 1221 1100 1100 1100 1230 1000 1230 1210 1100 The processormay control overall operation of the data storage systemincluding the controller. The processormay operate according to a predetermined firmware, and may access the semiconductor deviceby controlling the NAND controller. The NAND controllermay include a controller interfaceprocessing communication with the semiconductor device. Through the controller interface, a control command for controlling the semiconductor device, data to be written to the memory cell transistors MCT of the semiconductor device, and data to be read from the memory cell transistors MCT of the semiconductor devicemay be transmitted. The host interfacemay provide a communication function between the data storage systemand an external host. When a control command from an external host is received through the host interface, the processormay control the semiconductor devicein response to the control command.

According to the aforementioned example implementations, a semiconductor device and data storage system including the same may include a contact plug, a dummy vertical structure adjacent to the contact plug, and a contact insulating structure shared by the contact plug and the dummy vertical structure, and the contact insulating structure may include a first contact insulating pattern in contact with the contact plug and a portion of the dummy vertical structure and second contact insulating patterns in contact with the other portion of the dummy vertical structure. Accordingly, by preventing the first contact insulating pattern from being removed during the manufacturing process by the second contact insulating patterns of the contact insulating structure shared by the contact plug and the dummy vertical structure, a semiconductor device having improved reliability and a data storage system including the same may be provided.

While this disclosure contains many specific implementation details, these should not be construed as limitations on the scope of what may be claimed. Certain features that are described in this disclosure in the context of separate implementations can also be implemented in combination in a single implementation. Conversely, various features that are described in the context of a single implementation can also be implemented in multiple implementations separately or in any suitable subcombination. Moreover, although features may be described above as acting in certain combinations, one or more features from a combination can in some cases be excised from the combination, and the combination may be directed to a subcombination or variation of a subcombination.