Transmitter and Receiver Adopting Correlated Signaling for Compensating for Inter-Channel Mismatch and Integrated Circuit Including the Same

This application claims priority under 35 U.S.C. § 119(a) to Korean Patent Application No. 10-2024-0179872, filed in the Korean Intellectual Property Office on Dec. 5, 2024, the disclosure of each of which is hereby incorporated by reference in its entirety.

The present disclosure relates to a transmitter, and more particularly, to a transmitter and a receiver adopting correlated signaling for compensating for inter-channel mismatch.

Conventional parallel transmitters and receivers have reduced and solved skew caused by mismatch between signal transmission lines by printing the signal transmission lines on a printed circuit board or in an integration process sufficiently to reduce the skew. This method has used an area of unnecessary signal transmission lines.

Correlated signaling refers to a technique used in communication systems to generate or use correlated signals.

In communication systems, correlated signaling is designed so that a plurality of signals have a certain correlation with each other. Correlated signaling can facilitate detection of desired signals or improve performance of communication systems.

Correlated signals are easier to detect, a correlation between signals is utilized to improve an energy efficiency of transmitted power, and correlated signaling can utilize correlated signals to suppress specific interference or enhance signal differentiation.

An object of the present disclosure is to provide a transmitter and a receiver adopting correlated signaling, which include a phase interpolator that selects a reference phase of a clock as any one of 0°, 90°, 180°, and 270°, fine-tunes the selected reference phase to any one of 0° to 90°, and generates differential clocks using the fine-tuned reference phase, and a device that can use the differential clocks as synchronous differential clocks, and an integrated circuit having the same to compensate for inter-channel mismatch that may occur in a process of printing channels on a printed circuit board or an integration process.

An exemplary embodiment of the present disclosure is directed to a transmitter, including serializers, and a phase interpolator configured to select a reference phase of a clock as one of 0°, 90°, 180°, and 270° using a first code, fine-tune the selected reference phase by adding a phase selected using a second code thereto, and generate differential clocks using the fine-tuned reference phase, in which the phase selected using the second code is any one of 0° to 90°, and the differential clocks are used as synchronization clocks of each of the serializers.

Another exemplary embodiment of the present disclosure is directed to a receiver, including a continuous time linear equalizer configured to receive a first channel signal input through a first channel and a second channel signal input through a second channel, a current mode amplifier configured to buffer output signals of the continuous time linear equalizer, a phase interpolator configured to select a reference phase of a clock as one of 0°, 90°, 180°, and 270° using a first code, fine-tune the selected reference phase by adding a selected phase using a second code thereto, and generate differential clocks using the fine-tuned reference phase, a first comparator configured to compare an output signal of the current mode amplifier with a first reference voltage using the differential clocks and output first bits, and a second comparator configured to compare the output signal of the current mode amplifier with a second reference voltage using the differential clocks and output second bits.

Still another exemplary embodiment of the present disclosure is directed to an integrated circuit, including a first transmitter, a second transmitter having the same structure as the first transmitter, a receiver, a first communication channel connected between a first output terminal of the first transmitter and a first input terminal of the receiver, and a second communication channel connected between a second output terminal of the second transmitter and a second input terminal of the receiver, in which the first transmitter includes serializers, and a phase interpolator configured to select a reference phase of a clock as any one of 0°, 90°, 180°, and 270° using a first code, fine-tune the selected reference phase by adding a phase selected using a second code thereto, and generate differential clocks using the fine-tuned reference phase, the phase selected using the second code is any one of 0° to 90°, and the differential clocks are used as synchronization clocks of each of the serializers.

The phase interpolator may include a first differential amplifier configured to select the reference phase as 0° using the first code having a first value, generate a first phase finely tuned between 0° and 90° by amplifying first differential input clocks in response to the second code, and generate the differential clocks using the first phase, a second differential amplifier configured to select the reference phase as 90° using the first code having a second value, generate a second phase finely tuned between 90° and 180° by amplifying second differential input clocks in response to the second code, and generate the differential clocks using the second phase, a third differential amplifier configured to select the reference phase as 180° using the first code having a third value, generate a third phase finely tuned between 180° and 270° by amplifying the first differential input clocks in response to the second code, and generate the differential clocks using the third phase, and a fourth differential amplifier configured to select the reference phase as 270° using the first code having a fourth value, generate a fourth phase finely tuned between 270° and 360° by amplifying the second differential input clocks in response to the second code, and generate the differential clocks using the third phase.

1 FIG. is a block diagram of a system including a transmitter and a receiver adopting correlated signaling according to an embodiment of the present disclosure.

1 FIG. 100 100 Referring to, a systemis a transmitter system configured to transmit and receive wired signals over a short distance. The systemmay be a central processing unit (CPU), a graphics processing unit (GPU), a tensor processing unit (TPU), a neural processing unit (NPU), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a System on Chip (SoC), or a system integrated within memory device, but the present disclosure is not limited thereto.

100 200 1 200 300 1 300 300 1 300 2 1 m, m− The systemincludes a plurality of transmitters_to_a plurality of receivers_to_(1), a plurality of dummy receivers_DMand_DM, and a plurality of signal transmission lines CHto CHm, also referred to as “communication channels” or “channels.” Where m is a natural number greater than or equal to 2, and for convenience of description in the present specification, m is assumed to be 8.

100 The systemincludes parallel transmitters adopting correlated signaling and has a structure which can compensate for inter-channel mismatch. For example, the correlated signaling is a technique used to analyze a correlation between two signals to extract specific characteristics, measure similarity, or analyze frequency components of a signal.

300 300 i i+ For example, increased jitter noise due to inter-channel mismatch is compensated for or eliminated by two corresponding receivers_and_(1), where i is any one of 1 to 7, and 1≤i≤(m−1).

300 1 1 0 200 1 1 A first dummy receiver_DMreceives and processes a first channel signal CH_of a first transmitter_through a first channel CH.

300 2 2 0 200 2 2 3 0 200 3 3 300 7 7 8 0 200 8 8 A second receiver_receives and processes a second channel signal CH_of a second transmitter_received through a second channel CHand a third channel signal CH_of a third transmitter_received through a third channel CH. A seventh receiver_receives and processes a seventh channel signal of a seventh transmitter received through a seventh channel CHand an eighth channel signal CH_of an eighth transmitter_received through an eighth channel CH.

300 2 8 0 200 8 8 A second dummy receiver_DMreceives and processes the eighth channel signal CH_of the eighth transmitter_received through the eighth channel CH.

2 FIG. 1 FIG. 1 2 FIGS.and 2 FIG. 200 1 200 8 200 1 is a block diagram of the first transmitter shown in. Referring to, since the eight transmitters_to_are identical in structure and operation, a structure and an operation of the first transmitter_will be described in detail with reference to.

200 1 210 215 220 230 240 250 260 270 The first transmitter_includes a clock buffer, a frequency divider (or clock divider), a first serializer circuit, a poly-phase filter (PPF) circuit, a phase interpolator, a latch-based retimer, a second serializer circuit, and a feed-forward equalizer (FFE).

0 0 215 Input differential clocks CLK(f) and CLKB(f) Are Input to the Frequency Divider.

210 0 0 230 0 0 0 The clock bufferbuffers each of the input differential clocks CLK(f) and CLKB(f) and outputs the buffered differential clocks to the poly-phase filter (PPF) circuit. Each of the input differential clocks CLK(f) and CLKB(f) has a clock frequency f.

215 0 0 0 1 2 3 The frequency dividerdivides each of the input differential clocks CLK(f) and CLKB(f) having the clock frequency fby different division ratios to generate divided differential clocks having different frequencies f, f, and f.

220 221 223 The first serializer circuitincludes a first input serializer circuitand a second input serializer circuit.

221 2 2 221 k k The first input serializer circuitserializes a first parallel data D() using divided differential clocks to generate a first input data ED. For example, the first parallel data D() is an 8-bit parallel data, and the first input data ED is a 1-bit data. According to the embodiment, the first input serializer circuitmay be an 8:1 serializer.

223 2 2 223 k− k− The second input serializer circuitserializes a second parallel data D(1) using the divided differential clocks to generate a second input data EO. For example, the second parallel data D(1) is an 8-bit parallel data, and the second input data EO is a 1-bit data. According to the embodiment, the second input serializer circuitmay be an 8:1 serializer.

3 FIG. 2 FIG. 4 FIG. 3 FIG. 5 FIG. 3 FIG. 6 FIG. 3 FIG. 7 FIG. 2 FIG. is a block diagram of the first serializer circuit shown in,is a timing diagram of signals for describing an operation of an 8:4 serializer shown in,is a timing diagram of signals for describing an operation of a 4:2 serializer shown in,is a timing diagram of signals for describing an operation of a 2:1 serializer shown in, andis a timing diagram of output signals of the first serializer circuit shown in.

2 7 FIGS.to 215 3 3 3 3 0 2 2 2 2 0 1 1 1 1 0 f f f f f f Referring to, the divided differential clocks divided by the frequency dividerinclude first divided differential clocks CLK() and CLKB() generated by dividing the clock frequency fby a first division ratio (e.g., 8), second divided differential clocks CLK() and CLKB() generated by dividing the clock frequency fby a second division ratio (e.g., 4), and third divided differential clocks CLK() and CLKB() generated by dividing the clock frequency fby a third division ratio (e.g., 2).

3 3 3 3 0 2 2 2 2 0 1 1 1 1 0 f f f f f f For example, a frequency of each of the first divided differential clocks CLK() and CLKB() is f/8, a frequency of each of the second divided differential clocks CLK() and CLKB() is f/4, and a frequency of each of the third divided differential clocks CLK() and CLKB() is f/2.

221 221 1 221 2 221 3 The first input serializer circuitincludes a first serializer_, a second serializer_, and a Third Serializer_.

221 1 2 3 3 3 3 1 k f f The first serializer_serializes N-bit (e.g., N is a natural number greater than or equal to 2, and N is 8) first parallel data D() using the first divided differential clocks CLK() and CLKB() to generate a first input N/2-bit parallel data DE.

221 2 1 2 2 2 2 2 f f The second serializer_serializes the first input N/2-bit parallel data DEusing the second divided differential clocks CLK() and CLKB() to generate a first input N/4-bit parallel data DE.

221 3 2 1 1 1 1 f f The third serializer_serializes the first input N/4-bit parallel data DEusing the third divided differential clocks CLK() and CLKB() to generate a first input N/8-bit parallel data, i.e., the first input data ED.

223 223 1 223 2 223 3 The second input serializer circuitincludes a fourth serializer_, a fifth serializer_, and a sixth serializer_.

223 1 2 3 3 3 3 1 k− f f The fourth serializer_serializes an N-bit (here, N is 8) second parallel data D(1) using the first divided differential clocks CLK() and CLKB() to generate a second input N/2-bit parallel data DO.

223 2 1 2 2 2 2 2 f f The fifth serializer_serializes the second input N/2-bit parallel data DOusing the second divided differential clocks CLK() and CLKB() to generate a second input N/4-bit parallel data DO.

223 3 2 1 1 1 1 f f The sixth serializer_serializes the second input N/4-bit parallel data DOusing the third divided differential clocks CLK() and CLKB() to generate a second input N/8-bit parallel data, i.e., the second input data EO.

221 1 223 1 221 1 223 1 2 2 1 1 k k− 4 FIG. The first serializer_and the fourth serializer_can each be an 8:4 serializer. The serializers_and_serialize 8-bit parallel data D() and D(1) according to the timing diagram shown into generate 4-bit parallel data DEand DO, respectively.

221 2 223 2 221 2 223 2 1 1 2 2 5 FIG. The second serializer_and the fifth serializer_can each be a 4:2 serializer. The serializer_and_serialize the 4-bit parallel data DEand DOaccording to the timing diagram shown into generate 2-bit parallel data DEand DO, respectively.

221 3 223 3 221 3 223 3 2 2 6 FIG. The third serializer_and the sixth serializer_can each be a 2:1 serializer. The serializer_and_serialize the 2-bit parallel data DEand DOaccording to the timing diagram shown into generate 1-bit data DE and DO, respectively.

7 FIG. 4 7 FIGS.through 220 2 2 1 48 k k− Referring to the timing diagram shown in, the first serializer circuitcan serialize the 8-bit parallel data D() and D(1) and finally output each of the 1-bit input data DE and DO. Dto Dshown inrepresent 1-bit data and can indicate an order of data.

8 FIG. 1 FIG. 1 8 FIGS.and 230 230 1 230 4 is a block diagram of the poly-phase filter circuit shown in. Referring to, the poly-phase filter circuitincludes a plurality of poly-phase filters_to_.

9 FIG. 8 FIG. 8 9 FIGS.and 9 FIG. 230 1 230 1 0 90 180 270 230 2 is a circuit diagram of a first poly-phase filter shown in. Referring to, a first poly-phase filter_includes a plurality of inverters. When some of the plurality of inverters are designed to have a delay, the first poly-phase filter_generates four clocks CLK, CLK, CLK, and CLKeach having a phase difference of 90°, as shown in, and outputs them to a second poly-phase filter_.

10 FIG. 8 FIG. 8 10 FIGS.and 230 2 230 4 230 2 is a circuit diagram of the second poly-phase filter shown in. Referring to, the poly-phase filters_to_are identical in structure and operation. Therefore, a structure and an operation of the second poly-phase filter_will be described in detail.

230 2 230 2 0 90 180 270 230 3 10 FIG. The second poly-phase filter_includes a plurality of inverters. When some of the plurality of inverters are designed to have a delay, the second poly-phase filter_generates four clocks CLK, CLK, CLK, and CLKeach having a phase difference of 90°, as shown in, and transmits them to a third poly-phase filter_.

230 3 0 90 180 270 230 4 The third poly-phase filter_generates four clocks CLK, CLK, CLK, and CLKeach having a phase difference of 90°, and transmits them to a fourth poly-phase filter_.

230 4 0 90 180 270 0 90 180 270 The fourth poly-phase filter_generates four clocks CLK, CLK, CLK, and CLKeach having a phase difference of 90°. At this time, CLKis identical to CLKI, CLKis identical to CLKQ, CLKis identical to CLKIB, and CLKis identical to CLKQB. CLKI and CLKIB are differential clocks, and CLKQ and CLKQB are differential clocks.

11 FIG. 1 FIG. 12 FIG. 11 FIG. 11 12 FIGS.and 240 240 1 240 4 is a circuit diagram of the phase interpolator shown in, andis a conceptual diagram for describing an operation of the phase interpolator shown in. Referring to, the phase interpolatorincludes a plurality of differential amplifiers (also referred to as “mixers”)_to_.

240 1 2 3 4 1 The phase interpolatorselects a reference phase of a clock as any one of 0°, 90°, 180°, and 270° using a corresponding first code PSctrl<>, PSctrl<>, PSctrl<>, or PSctrl<>, fine-tunes the selected reference phase by adding a phase selected using a W-bit second code ICctrl(<W:>) thereto, and generates differential clocks OUTP and OUTN using the fine-tuned reference phase.

1 2 3 4 1 1 2 2 3 3 4 4 For example, a first code generator may generate respective first codes PSctrl<>, PSctrl<>, PSctrl<>, and PSctrl<>in response to a 2-bit data. In this case, when the 2-bit data is 2′b00, the first code generator generates a first code PSctrl<> or a first phase control signal PSctrl<> having a high level. When the 2-bit data is 2′b01, the first code generator generates a first code PSctrl<> or a second phase control signal PSctrl<> having a high level. When the 2-bit data is 2′b10, the first code generator generates a first code PSctrl<> or a third phase control signal PSctrl<> having a high level. When the 2-bit data is 2′b11, the first code generator can generate a first code PSctrl<> or a fourth phase control signal PSctrl<> having a high level.

1 250 261 263 265 In this case, the phase selected using the W-bit second code Icctrl(<W:>) is any one of 0° to 90°. Here, W is a natural number greater than or equal to 2, and for the convenience of description, W is assumed to be 32. The differential clocks OUTP and OUTN can be used as synchronization clocks (or operating clocks) of the latch-based retimerand each of serializers,, and.

240 1 240 2 240 3 240 4 240 1 240 2 240 3 240 4 Types of differential amplifiers_and_may be different from types of differential amplifiers_and_. For example, the differential amplifiers_and_may be inverting differential amplifiers, and the differential amplifiers_and_may be non-inverting differential amplifiers, but the present disclosure is not limited thereto.

240 1 240 4 The differential amplifier may refer to a clock generator. Each of the differential amplifiers_to_has an identical structure.

240 1 1 32 1 A first differential amplifier_may select the reference phase as 0° using the first code PSctrl<> having a first value (e.g., ‘high level’ or ‘logic 1’), generate a first phase finely tuned between 0° and 90° by amplifying a difference between first differential input clocks CLKI and CLKIB in response to a 32-bit second code ICctrl(<:>), and generate the differential clocks OUTP and OUTN using the first phase.

240 1 1 1 2 1 1 1 2 1 3 1 242 1 The first differential amplifier_includes resistors R_and R_for supplying an operating voltage VDD to amplifying NMOS transistors T_and T_, a bias (or selecting) NMOS transistor T_, and a phase fine-tuning current cell_.

242 1 242 2 242 3 242 4 32 1 For example, each of phase fine-tuning current cells_,_,_, and_may include 32 parallel switches that are turned on or off in response to each of 32-bit parallel control signals included in the second code Icctrl(<:>).

1 3 1 240 When the first code PSctrl<> having the first value is supplied to a bias NMOS transistor T_, the phase interpolatorselects the reference phase as 0°.

32 1 240 1 242 1 240 When the 32-bit second code ICctrl(<:>) is adjusted, a current flowing through the first differential amplifier_is adjusted by the phase fine-tuning current cell_. Therefore, the phase interpolatormay generate a first phase (e.g., 0°<first phase<90°) finely tuned between 0° and 90° and generate the differential clocks OUTP and OUTN using the first phase.

32 1 32 1 For example, when the 32-bit second code ICctrl(<:>) is all 1, the first phase can be a phase very close to 90°, and when a least significant bit (LSB) of the 32-bit second code ICctrl(<:>) is 1 and the remaining 31 bits are all 0, the first phase may be a phase slightly greater than 0°.

240 2 2 32 1 A second differential amplifier_may select the reference phase as 90° using the first code PSctrl<> having a second value (e.g., ‘high level(or data 1)’ or ‘logic 1(or data 0)’), generate a second phase (e.g., 90°<second phase<180°) finely tuned between 90° and 180° by amplifying a difference between the second differential input clocks CLKQ and CLKQB in response to the 32-bit second code ICctrl(<:>), and generate the differential clocks OUTP and OUTN using the second phase.

240 2 1 2 2 2 1 2 2 2 3 2 242 2 The second differential amplifier_includes resistors R_and R_for supplying the operating voltage VDD to amplifying NMOS transistors T_and T_, a bias (or selection) NMOS transistor T_, and a phase fine-tuning current cell_.

2 3 2 240 When the first code PSctrl<> having the second value is supplied to the bias NMOS transistor T_, the phase interpolatorselects the reference phase as 90°.

32 1 240 2 242 2 240 When the 32-bit second code ICctrl(<:>) is adjusted, a current flowing through the second differential amplifier_is adjusted by the phase fine-tuning current cell_. Therefore, the phase interpolatormay generate a second phase finely tuned between 90° and 180° and generate the differential clocks OUTP and OUTN using the second phase.

32 1 32 1 For example, when the 32-bit second code ICctrl(<:>) is all 1, the second phase may be a phase very close to 180°, and when the LSB of the 32-bit second code ICctrl(<:>) is 1 and the remaining 31 bits are all 0, the second phase may be a phase slightly greater than 90°.

240 3 3 32 1 A third differential amplifier_may select the reference phase as 180° using the first code PSctrl<> having a third value (e.g., ‘high level’ or ‘logic 1’), generate a third phase (e.g., 180°<third phase<270°) finely tuned between 180° and 270° by amplifying a difference between the first differential input clocks CLKI and CLKIB in response to the 32-bit second code ICctrl(<:>), and generate the differential clocks OUTP and OUTN using the third phase.

240 3 1 3 2 3 1 3 2 3 3 3 242 3 The third differential amplifier_includes resistors R_and R_for supplying the operating voltage VDD to amplifying NMOS transistors T_and T_, a bias (or selection) NMOS transistor T_, and a phase fine-tuning current cell_.

3 3 3 240 When the first code PSctrl<> having the third value is supplied to the bias NMOS transistor T_, the phase interpolatorselects the reference phase as 180°.

32 1 240 3 242 3 240 When the 32-bit second code ICctrl(<:>) is adjusted, a current flowing through the third differential amplifier_is adjusted by the phase fine-tuning current cell_. Therefore, the phase interpolatormay generate a third phase finely tuned between 180° and 270° and generate the differential clocks OUTP and OUTN using the third phase.

32 1 32 1 For example, when the 32-bit second code ICctrl(<:>) is all 1, the third phase may be a phase very close to 270°, and when the LSB of the 32-bit second code ICctrl(<:>) is 1 and the remaining 31 bits are all 0, the third phase may be a phase slightly greater than 180°.

240 4 4 32 1 A fourth differential amplifier_may select the reference phase as 270° using the first code PSctrl<> having a fourth value (e.g., ‘high level’ or ‘logic 1’), generate a fourth phase (e.g., 270°<fourth phase<360°) finely tuned between 270° and 360° by amplifying the difference between the second differential input clocks CLKQ and CLKQB in response to the 32-bit second code ICctrl(<:>), and generate the differential clocks OUTP and OUTN using the fourth phase.

240 4 1 4 2 4 1 4 2 4 3 4 242 4 The fourth differential amplifier_includes resistors R_and R_for supplying the operating voltage VDD to amplifying NMOS transistors T_and T_, a bias (or selection) NMOS transistor T_, and a phase fine-tuning current cell_.

4 3 4 240 When the first code PSctrl<> having the fourth value is supplied to the bias NMOS transistor T_, the phase interpolatorselects the reference phase as 270°.

32 1 240 4 242 4 240 When the 32-bit second code ICctrl(<:>) is adjusted, a current flowing through the fourth differential amplifier_is adjusted by the phase fine-tuning current cell_. Therefore, the phase interpolatormay generate a fourth phase finely tuned between 270° and 360° and generate the differential clocks OUTP and OUTN using the fourth phase.

32 1 32 1 For example, when the 32-bit second code ICctrl(<:>) is all 1, the fourth phase may be very close to 360°. When the LSB of the 32-bit second code ICctrl(<:>) is 1 and the remaining 31 bits are all 0, the fourth phase may be slightly greater than 270°.

13 FIG. 1 FIG. 14 FIG. 13 FIG. is a block diagram of the latch-based retimer shown in, andis a timing diagram of output signals of the latch-based retimer shown in.

250 The latch-based retimeris an electronic system for correcting signal timing and maintaining data integrity. It synchronizes input signals DE and DO to the differential clocks OUTP and OUTN and outputs output signals E and H, C and F, and A and A at accurate timings, thereby reducing signal jitter.

250 251 1 251 4 240 252 1 252 4 The latch-based retimerincludes a first shift register including a plurality of flip-flops_to_that operate based on the differential clocks OUTP and OUTN whose phases are controlled by the phase interpolator, and a second shift register including a plurality of flip-flops_to_that operate based on the differential clocks OUTP and OUTN.

251 1 251 3 251 1 251 4 251 2 251 4 251 1 251 4 Odd-numbered flip-flops_and_among the plurality of flip-flops_to_that sequentially process a 1-bit first input data DE perform a latch operation using a clock OUTP among the differential clocks OUTP and OUTN, and even-numbered flip-flops_and_among the plurality of flip-flops_to_perform a latch operation using an inverted clock OUTN among the differential clocks OUTP and OUTN. The first shift register outputs first parallel bits (ACE).

252 1 252 3 252 1 252 4 252 2 252 4 252 1 252 4 Odd-numbered flip-flops_and_among the plurality of flip-flops_to_that sequentially process a 1-bit second input data DO perform a latch operation using the clock OUTP among the differential clocks OUTP and OUTN, and even-numbered flip-flops_and_among the plurality of flip-flops_to_perform a latch operation using the inverted clock OUTN among the differential clocks OUTP and OUTN.

The second shift register outputs second parallel bits (DFH).

260 261 263 265 240 The second serializer circuitincludes seventh to ninth serializers,, andwhich perform a serialization operation on the basis of the differential clocks OUTP and OUTN whose phases are controlled by the phase interpolator.

261 263 265 261 263 265 221 3 223 3 261 263 265 3 6 FIGS.and Each of the serializers,, andmay be a 2:1 serializer, and an operation of each of the serializer,, andis identical or similar to that of each of the 2:1 serializers_and_described with reference to. Therefore, a detailed description of the operation of each of the 2:1 serializers,, andwill be omitted.

261 271 A seventh serializermay serialize a first bit (H) of the second parallel bits (DFH), which is paired with a first bit (E) of the first parallel bits (ACE) on the basis of the differential clocks OUTP and OUTN, generate first differential signals, and transmit them to a first voltage driver.

263 273 An eighth serializermay serialize a second bit (F) of the second parallel bits (DFH), which is paired with a second bit (C) of the first parallel bits (ACE) on the basis of the differential clocks OUTP and OUTN, generate second differential signals, and transmit them to a second voltage driver.

265 275 250 14 FIG. A ninth serializermay serialize a third bit (D) of the second parallel bits (DFH), which is paired with a third bit (A) of the first parallel bits (ACE) on the basis of the differential clocks OUTP and OUTN, generate third differential signals, and transmit them to a third voltage driver. Referring to, the latch-based retimermay generate signals E and H, C and F, and A and D delayed by a unit interval (UI).

15 FIG. 1 FIG. 1 15 FIGS.and 270 271 273 275 is a circuit diagram of the first voltage driver included in the feed-forward equalizer shown in. Referring to, the feed-forward equalizerincludes the first voltage driver, the second voltage driver, and the third voltage driver.

15 FIG. 271 Referring to, the first voltage driverincludes a single unit voltage driver.

271 1 1 2 2 1 2 3 3 1 2 1 2 A unit voltage driver corresponding to the first voltage driverincludes a plurality of PMOS transistors MPconnected in parallel between a power line for supplying the operating voltage VDD and a first node NDand receiving first bias bits (PBIAS), transistors MPand MNconnected in series between nodes NDand ND, transistors MNand MPconnected in series between the nodes NDand ND, and a plurality of NMOS transistors MNconnected in parallel between a second node NDand a ground Vss and receiving second bias bits (NBIAS), respectively.

273 271 275 271 The second voltage driverincludes a plurality of parallel-connected unit voltage drivers, and the third voltage driverincludes a plurality of parallel-connected unit voltage drivers.

271 273 271 275 271 275 271 271 The number of unit voltage driversincluded in the second voltage driveris greater than the number of unit voltage driversincluded in the third voltage driver, and the number of unit voltage driversincluded in the third voltage driveris greater than the number of unit voltage driversincluded in the first voltage driver.

273 275 275 271 For example, a voltage driving capability of the second voltage driveris greater than that of the third voltage driver, and the voltage driving capability of the third voltage driveris greater than that of the first voltage driver.

271 271 261 1 The unit voltage driverincluded in the first voltage drivergenerates a first output signal DOUT=PRE by amplifying a difference between first differential signals DIN and DINB generated by the seventh serializerand inverting an amplified signal, and outputs this signal DOUT=PRE to an output terminal TXP.

271 273 263 1 Each of the plurality of unit voltage driversincluded in the second voltage drivergenerates a second output signal DOUT=MAIN by amplifying a difference between second differential signals DIN and DINB generated by the eighth serializer, and outputs this signal DOUT=MAIN to the output terminal TXP.

271 275 265 1 Each of the plurality of unit voltage driversincluded in the third voltage drivergenerates a third output signal DOUT=POST by amplifying a difference between differential signals DIN and DINB generated by the ninth serializerand inverting an amplified signal, and outputs this signal DOUT=POST to the output terminal TXP.

16 FIG. 1 FIG. 1 15 16 FIGS.,, and 271 273 275 1 1 1 300 1 300 1 is a timing diagram of output signals of the feed-forward equalizer shown in. Referring to, respective output signals PRE, MAIN, and POST of each of the voltage drivers,, andincluding different numbers of unit voltage drivers are combined at the output terminal TXPto be generated as the first channel signal CH_O. The first channel signal CH_O is transmitted to a first receiving terminal of a first receiver_and a receiving terminal of a first dummy receiver_D.

200 2 200 8 2 0 8 200 1 1 A process in which each of the transmitters_to_generates respective channel signals CH_to CH_O is identical to or similar to a process in which the first transmitter_generates the first channel signal CH_O.

17 FIG. 1 FIG. 1 17 FIGS.and 300 1 300 300 1 m− is a block diagram of the first receiver shown in. Referring to, receivers_to_(1) are identical in structure and operation, so that a structure and an operation of the receiver_will be described in detail.

300 1 302 1 1 1 200 1 302 2 2 2 200 2 302 3 302 4 0 0 310 320 332 334 340 350 360 370 380 390 The first receiver_includes a first receiving terminal_for receiving the first channel signal CH_O transmitted through the first channel CHconnected to the first transmitter_, a second receiving terminal_for receiving a second channel signal CH_O transmitted through the second channel CHconnected to the second transmitter_, clock receiving terminals_and_for receiving the differential clocks CLK(f) and CLKB(f), a first amplifier, a second amplifier, a first comparator, a second comparator, a clock buffer, a PPF circuit, a phase interpolator, an XOR circuit, a retimer, and a deserializer.

300 1 1 302 1 302 2 The first receiver_may further include a resistor Ra connected between a power line for transmitting a receiver operating voltage VDDand the first receiving terminal_, and a resistor Rb connected between the power line and the second receiving terminal_.

310 1 302 1 2 302 2 320 The first amplifiergenerates differential signals by amplifying a difference between the first channel signal CH_O received through the first receiving terminal_and the second channel signal CH_O received through the second receiving terminal_and transmit them to the second amplifier.

310 According to embodiments, the first amplifiermay be a continuous time linear equalizer (CTLE) or a buffer.

320 310 1 332 334 The second amplifieramplifies a difference between the differential signals output from the first amplifierand transmits an amplified signal OTto the first comparatorand the second comparator.

320 According to embodiments, the second amplifiermay be a current mode logic (Current Mode Logic (CML) circuit, a current mode amplifier.

332 1 320 360 2 334 1 320 3 2 3 332 334 The first comparatorcompares the output signal OTof the second amplifierwith a first reference voltage VH using the differential clocks OUTP and OUTN output from the phase interpolatorand outputs first bits OTcorresponding to a result of the comparison. The second comparatorcompares the output signal OTof the second amplifierwith a second reference voltage VL using the differential clocks OUTP and OUTN and outputs second bits OTcorresponding to a result of the comparison. According to embodiments, the first bits OTare 2 bits, and the second bits OTare 2 bits. Each of the comparatorsandmay be a sampler or a Schmitt trigger.

340 0 0 302 3 302 4 350 The clock bufferbuffers the input differential clocks CLK(f) and CLKB(f) output from the clock receiving terminals_and_and outputs the buffered differential clocks to the PPF circuit.

350 300 1 230 200 1 350 360 300 1 240 200 1 360 A structure and an operation of the PPF circuitincluded in the first receiver_are identical to those of the PPF circuitincluded in the first transmitter_, and therefore, a description of the PPF circuitwill be omitted. A structure and an operation of the phase interpolatorincluded in the first receiver_are identical to those of the phase interpolatorincluded in the first transmitter_, and therefore, a description of the phase interpolatorwill be omitted.

370 4 2 332 3 334 380 4 A logic circuit, for example, the XOR circuit, generates third bits OTby performing an XOR operation on the first bits OToutput from the first comparatorand the second bits OToutput from the second comparatorbit by bit and outputs them to the retimer. According to the embodiment, the third bits OTmay be 2 bits.

380 4 5 390 360 The retimerreorders the third bits OTand outputs the reordered fourth bits OT, e.g., 2 bits, to the deserializerusing the differential clocks OUTP and OUTN output from the phase interpolator.

380 4 5 The retimermay synchronize the input signals OTto the differential clocks OUTP and OUTN and output the output signals OTat accurate timings.

390 5 380 6 360 390 390 5 6 The deserializerdeserializes the fourth bits OToutput from the retimerand generates parallel data OTusing the differential clocks OUTP and OUTN output from the phase interpolator. The deserializermay be a 2:16 deserializer, and the deserializermay deserialize the 2-bit parallel data OTto generate a 16-bit parallel data OT.

18 FIG. 1 FIG. 1 18 FIGS.and 300 1 300 2 300 1 is a block diagram of the dummy transmitter shown in. Referring to, the first dummy receiver_DMand the second dummy receiver_DMare identical in structure, so that a structure and an operation of the first dummy receiver_DMwill be described.

300 1 300 7 300 1 300 2 1 0 8 1 8 Unlike the receivers_to_, each dummy receiver_DMor_DMreceives a single channel signal CH_or CH_O transmitted through a single channel CHor CH.

300 1 302 1 1 1 200 1 302 3 302 4 0 0 310 320 330 340 350 360 380 390 The first dummy receiver_DMincludes a first receiving terminal_A for receiving the first channel signal CH_O transmitted through the first channel CHconnected to the first transmitter_, clock receiving terminals_A and_A for receiving the input differential clocks CLK(f) and CLKB(f), a first amplifierA, the second amplifier, a third amplifier, the clock buffer, the PPF circuit, the phase interpolator, the retimer, and the deserializer.

300 1 1 302 1 The first dummy receiver_DMmay further include a resistor Rc connected between the power line for transmitting the receiver operating voltage VDDand the first receiving terminal_.

310 1 302 1 320 310 The first amplifierA amplifies the difference between the first channel signal CH_O received through the first receiving terminal_A and a reference voltage VREF and outputs differential signals to the second amplifier. According to the embodiments, the first amplifierA may be a continuous time linear equalizer (CTLE) or a buffer.

320 310 330 320 The second amplifieramplifies a difference between the differential signals transmitted from the first amplifierA and transmits amplified differential signals OTP and OTN to the third amplifier. According to the embodiments, the second amplifiermay be a current mode logic (CML) circuit, or a current mode amplifier.

330 360 320 380 330 The third amplifier, using the differential clocks OUTP and OUTN output from the phase interpolator, generates an amplified signal OT by amplifying a difference between the differential signals OTP and OTN output from the second amplifierand outputs it to the retimer. The output signal OT may be 2 bits, and the third amplifiermay be a sampler or a Schmitt trigger.

340 0 0 302 3 302 4 350 The clock bufferbuffers the differential clocks CLK(f) and CLKB(f) output from the clock receiving terminals_A and_and outputs the buffered differential clocks to the PPF circuit.

350 300 1 230 200 1 350 A structure and an operation of the PPF circuitincluded in the first dummy receiver_DMare identical to those of the PPF circuitincluded in the first transmitter_, and therefore, a description of the PPF circuitwill be omitted.

360 300 1 240 200 1 360 A structure and an operation of the phase interpolatorincluded in the first dummy receiver_DMare identical to those of the phase interpolatorincluded in the first transmitter_, and therefore, a description of the phase interpolatorwill be omitted.

380 330 5 390 360 The retimerrearranges the bits OT output from the third amplifierand outputs the rearranged bits OT(e.g., 2 bits) to the deserializerusing the differential clocks OUTP and OUTN output from the phase interpolator.

390 5 380 6 360 390 5 6 The deserializerdeserializes the bits OTrearranged by the retimerand generates parallel data OTusing the differential clocks OUTP and OUTN output from the phase interpolator. The deserializermay be a 2:16 deserializer, and may deserialize the 2-bit parallel data OTand generates 16-bit parallel data OT.

According to the embodiment of the present disclosure, a receiver and a transmitter adopting correlated signaling provide a phase interpolator that selects a reference phase of a clock as any one of 0°, 90°, 180°, and 270°, fine-tunes the selected reference phase to any one of 0° to 90°, and generates differential clocks using the fine-tuned reference phase, and a device that can use the differential clocks as synchronous differential clocks, thereby compensating for inter-channel mismatch that may occur in a process of printing channels on a printed circuit board or an integration process.

Moreover, the transmitter and receiver adopting correlated signaling can compensate for inter-channel mismatch, thereby reducing jitter noise caused by the inter-channel mismatch, and achieving the integrity of transmitted and received signals.

Although a few embodiments of the present general inventive concept have been shown and described, it will be appreciated by those skilled in the art that changes may be made in these embodiments without departing from the principles and spirit of the general inventive concept, the scope of which is defined in the appended claims and their equivalents.