Display Substrate and Manufacturing Method Therefor, and Display Apparatus

This application is a continuation application of the U.S. application Ser. No. 18/938,307, which is a continuation application of the U.S. application Ser. No. 17/763,198, which is a national stage of PCT Application No. PCT/CN2021/097380, which is filed on May 31, 2021 and claims priority to Chinese Patent Application No. 202011041915.9 entitled “Pixel Circuit, Pixel Driving Method, Display Panel and Display Apparatus” and filed on Sep. 28, 2020. The above-identified applications are incorporated into this application by reference in their entireties.

The present disclosure relates to the field of display technology, and particularly, to a display substrate and a manufacturing method therefor, and a display apparatus.

An Organic Light Emitting Diode (OLED) is an active light emitting display device, which has the advantages of auto-luminescence, wide angle of view, high contrast, low power consumption, extremely high response speed, lightness and thinness, bendability, low cost, etc. With the continuous development of display technology, Flexible Displays that use OLEDs as light emitting devices and use Thin Film Transistors (TFTs) for signal control have become mainstream products in the field of display at present.

The following is a summary about the subject matter described herein in detail. The summary is not intended to limit the protection scope of the claims.

The present disclosure provides a display substrate, including a base substrate, a second power line, a data signal line and a plurality of sub-pixels, wherein at least one sub-pixel includes a pixel driving circuit and a light emitting device connected to the pixel driving circuit, the pixel driving circuit is connected to the data signal line and the light emitting device is connected to the second power line; a semiconductor layer and a plurality of conducting layers, which are arranged at one side of the semiconductor layer away from the base substrate, are arranged on the base substrate, a first electrode is arranged in at least one conducting layer, the first electrode is connected to the second power line, and there is an overlapping area between an orthographic projection of the first electrode on the base substrate and an orthographic projection of the data signal line on the base substrate.

In an exemplary implementation, the first electrode includes a first electrode segment extending along a first direction and a second electrode segment extending along a second direction, there is an overlapping area between an orthographic projection of the second electrode segment on the base substrate and the orthographic projection of the data signal line on the base substrate, one end of the first electrode segment is connected to the second electrode segment, and the other end of the first electrode segment is connected to the second power line; and the second direction is an extension direction of the data signal line, and the first direction intersects the second direction.

In an exemplary implementation, the plurality of conducting layers includes a first conducting layer, a second conducting layer, a third conducting layer and a fourth conducting layer arranged sequentially at one side of the semiconductor layer away from the base substrate, the data signal line is arranged in the fourth conducing layer, and the first electrode is arranged in the first conducting layer, the second conducting layer or the third conducting layer.

In an exemplary implementation, the second power line is arranged in the fourth conducting layer, and the second power line is connected to the first electrode through a via hole.

In an exemplary implementation, the fourth conducting layer further includes a second power connecting line having one end connected to the second power line and the other end connected to the first electrode through a via hole.

In an exemplary implementation, the first electrode is arranged in the first conducting layer or the second conducting layer, an interlayer connecting electrode is further arranged in the third conducting layer, the interlayer connecting electrode is connected to the first electrode through a via hole, and the second power line is connected to the interlayer connecting electrode through a via hole.

In an exemplary implementation, the pixel driving circuit at least includes a first transistor, a second transistor, a third transistor, a fourth transistor and a fifth transistor; a first pole of the first transistor is connected to the data signal line, and a second pole of the first transistor is connected to a second node; a first pole of the second transistor is connected to a first node, and a second pole of the second transistor is connected to a third node; a gate electrode of the third transistor is connected to the first node, a first pole of the third transistor is connected to the first power line, and a second pole of the third transistor is connected to the third node; a first pole of the fourth transistor is connected to an initial signal line; and a first pole of the fifth transistor is connected to a reference signal line, and a second pole of the fifth transistor is connected to the second node.

In an exemplary implementation, the pixel driving circuit further includes a storage capacitor and a threshold capacitor, the storage capacitor includes a storage capacitor first polar plate and a storage capacitor second polar plate, and the threshold capacitor includes a threshold capacitor first polar plate and a threshold capacitor second polar plate; the storage capacitor second polar plate is connected to the first power line, and the storage capacitor first polar plate is connected to the first node; and the threshold capacitor second polar plate is connected to the second node, and the threshold capacitor first polar plate is connected to the first node.

In an exemplary implementation, the storage capacitor first polar plate and the threshold capacitor first polar plate are arranged in the first conducting layer, the storage capacitor first polar plate and the threshold capacitor first polar plate are connected to each other to form an integrated structure, and the threshold capacitor first polar plate does not overlap with the semiconductor layer.

In an exemplary implementation, the storage capacitor second polar plate and the threshold capacitor second polar plate are arranged in the second conducting layer, the storage capacitor second polar plate and the threshold capacitor second polar plate are spaced apart from each other, a storage capacitor second polar plate of a sub-pixel and a storage capacitor second polar plate of an adjacent sub-pixel are connected to each other to form an integrated structure, there is an overlapping area between an orthographic projection of the storage capacitor second polar plate on the base substrate and an orthographic projection of the storage capacitor first polar plate on the base substrate, and there is an overlapping area between an orthographic projection of the threshold capacitor second polar plate on the base substrate and an orthographic projection of the threshold capacitor first polar plate on the base substrate.

In an exemplary implementation, the fourth transistor is a double-gate transistor, and at least includes a fourth active layer arranged in the semiconductor layer and two fourth gate electrodes; and the display substrate further includes a first sub-polar plate, and there is an overlapping area between an orthographic projection of the first sub-polar plate on the base substrate and an orthographic projection of the fourth active layer, located between the two fourth gate electrodes, on the base substrate.

In an exemplary implementation, the two fourth gate electrodes are arranged in the first conducting layer, the first sub-polar plate is arranged in the second conducting layer, and the first sub-polar plate is connected to the initial signal line.

In an exemplary implementation, the fifth transistor is a double-gate transistor, and at least includes a fifth active layer arranged in the semiconductor layer and two fifth gate electrodes; and the display substrate further includes a second sub-polar plate, and there is an overlapping area between an orthographic projection of the second sub-polar plate on the base substrate and an orthographic projection of the fifth active layer, located between the two fifth gate electrodes, on the base substrate.

In an exemplary implementation, the two fifth gate electrodes are arranged in the first conducting layer, the second sub-polar plate is arranged in the second conducting layer, and the second sub-polar plate is connected to the first power line through a via hole.

In an exemplary implementation, the first transistor is a double-gate transistor, and at least includes a first active layer arranged in the semiconductor layer and two first gate electrodes; and the display substrate further includes a third sub-polar plate, and there is an overlapping area between an orthographic projection of the third sub-polar plate on the base substrate and an orthographic projection of the first active layer, located between the two first gate electrodes, on the base substrate.

In an exemplary implementation, the two first gate electrodes are arranged in the first conducting layer, the third sub-polar plate is arranged in the second conducting layer, and the third sub-polar plate is connected to the first power line through a via hole.

In an exemplary implementation, the second transistor is a double-gate transistor, and at least includes a second active layer arranged in the semiconductor layer and two second gate electrodes; and the display substrate further includes a fourth sub-polar plate, and there is an overlapping area between an orthographic projection of the fourth sub-polar plate on the base substrate and an orthographic projection of the second active layer, located between the two second gate electrodes, on the base substrate.

In an exemplary implementation, the two second gate electrodes are arranged in the first conducting layer, the third sub-polar plate is arranged in the second conducting layer, and the fourth sub-polar plate is connected to the first power line through a via hole.

The present disclosure further provides a display apparatus, including the aforementioned display substrate.

forming a semiconductor layer and a plurality of conducting layers, which are arranged at one side of the semiconductor layer away from the base substrate, on the base substrate, wherein a first electrode is arranged in at least one conducting layer, the first electrode is connected to the second power line, and there is an overlapping area between an orthographic projection of the first electrode on the base substrate and an orthographic projection of the data signal line on the base substrate. The present disclosure further provides a method for manufacturing a display substrate, the display substrate including a base substrate, a second power line, a data signal line and a plurality of sub-pixels, wherein at least one sub-pixel includes a pixel driving circuit and a light emitting device connected to the pixel driving circuit, the pixel driving circuit is connected to the data signal line and the light emitting device is connected to the second power line; the method including:

forming a semiconductor layer on the base substrate; and forming sequentially a first conducting layer, a second conducting layer, a third conducting layer and a fourth conducting layer on the semiconductor layer, wherein the first electrode is arranged in the first conducting layer, the second conducting layer or the third conducting layer, the second power line and the data signal line are arranged in the fourth conducting layer, and the second power line is connected to the first electrode through a via hole. In an exemplary implementation, the forming a semiconductor layer and a plurality of conducting layers, which are arranged at one side of the semiconductor layer away from the base substrate, on the base substrate includes:

Other aspects will become apparent upon reading and understanding accompanying drawings and the detailed description.

11 12 13 14 15 16 17 18 21 22 23 24 25 26 27 28 31 32 33 34 35 36 37 38 41 42 43 44 45 46 47 48 49 51 71 72 73 74 75 101 102 103 104 301 302 303 304 401 402 403 —first active layer;—second active layer;—third active layer;—fourth active layer;—fifth active layer;—sixth active layer;—seventh active layer;—eighth active layer;—first scan signal line;—second scan signal line;—third scan signal line;—first light emitting control line;—second light emitting control line;—storage capacitor first polar plate;—threshold capacitor first polar plate;—first electrode;—initial signal line;—first connecting line;—storage capacitor second polar plate;—threshold capacitor second polar plate;—first sub-polar plate;—second sub-polar plate;—third sub-polar plate;—fourth sub-polar plate;—first connecting electrode;—second connecting electrode;—third connecting electrode;—fourth connecting electrode;—fifth connecting electrode;—sixth connecting electrode;—seventh connecting electrode;—eighth connecting electrode;—interlayer connecting electrode;—anode connecting electrode;—first power line;—reference signal line;—second power line;—data signal line;—second power connecting line;—base substrate;—driving circuit layer;—light emitting device;—encapsulation layer;—anode;—pixel definition layer;—organic light emitting layer;—cathode;—first encapsulation layer;—second encapsulation layer; and—third encapsulation layer.

In order to make the objects, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be described in detail below in combination with the drawings. It is to be noted that their implementations may be carried out in many different forms. Those of ordinary skill in the art may easily understand such a fact that manners and contents may be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be explained as being limited to the contents recorded in the following implementations only. The embodiments in the present disclosure and features in the embodiments may be arbitrarily combined with each other without conflicts.

Scales of the drawings in the present disclosure may be used as references in the actual processes, which, however, are not limited thereto. For example, a width to length ratio of a channel, a thickness of each film layer and a spacing between two film layers, and a width of each signal line and a spacing between two signal lines may be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the number shown in the drawings. The drawings described in the present disclosure are schematic structure diagrams only, and one implementation of the present disclosure is not limited to the shapes, numerical values or the like shown in the drawings.

Ordinal numerals such as “first”, “second”, “third” and the like in the specification are set to avoid confusion of the constituent elements, but not to set a limit in quantity.

In the specification, for convenience, words and sentences indicating orientations or positional relationships, such as “center”, “upper”, “lower”, “front”, “back”, “vertical”, “horizontal”, “top”, “bottom”, “inside” and “outside”, are used for describing positional relationships of constituent elements with reference to the accompanying drawings, and are merely for facilitating describing the specification and simplifying the description, rather than indicating or implying that referred apparatuses or elements must have particular orientations, and be constructed and operated in particular orientations. Thus, they should not be construed as a limitation to the present disclosure. The positional relationships of the constituent elements appropriately change according to directions of describing the constituent elements. Therefore, the words and sentences are not limited to those described in the specification, but may be replaced appropriately according to a situation.

In the specification, unless otherwise specified and defined explicitly, the terms “install”, “connect” and “link” should be broadly understood. For example, it may be a fixed connection, a detachable connection, or an integral connection; may be a mechanical connection or an electrical connection; and may be a direct connection, or an indirect connection through an intermediary, or an internal connection between two elements. Those of ordinary skill in the art may understand the meanings of the above terms in the present disclosure according to specific situations.

In the specification, a transistor refers to an element which at least includes three terminals, i.e., a gate electrode, a drain electrode and a source electrode. The transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and a current may flow through the drain electrode, the channel region and the source electrode. It is to be noted that in the specification, the channel region refers to a region which the current mainly flows through.

In the specification, a first pole may be a drain electrode and a second pole may be a source electrode; or, a first pole may be a source electrode and a second pole may be a drain electrode. In the case that transistors with opposite polarities are used, or that a direction of a current changes during operation of a circuit, or the like, functions of the “source electrode” and the “drain electrode” are sometimes exchanged. Therefore, the “source electrode” and the “drain electrode” may be exchanged in the specification.

In the specification, an “electrical connection” includes a case in which constituent elements are connected together through an element with a certain electric action. There is no specific restriction on the “element with a certain electric action” as long as it allows transmission and receiving of electric signals between connected constituent elements. Examples of the “element with a certain electric action” include not only an electrode and a wiring, but also a switching element such as a transistor, a resistor, an inductor, a capacitor, other elements with various functions, etc.

In the specification, “parallel” refers to a state in which an angle formed by two straight lines is −10° or more and 10° or less, and thus also includes a state in which the angle is −5° or more and 5° or less. In addition, “perpendicular” refers to a state in which an angle formed by two straight lines is 80° or more and 100° or less, and thus also includes a state in which the angle is 85° or more and 95° or less.

In the specification, “film” and “layer” are interchangeable. For example, sometimes a “conducting layer” may be replaced with a “conducting film”. Similarly, sometimes an “insulating film” may be replaced with an “insulating layer”.

“About” in the present disclosure means that a boundary is not defined so strictly and numerical values within process and measurement error ranges are allowed.

1 FIG. 1 FIG. 1 1 1 1 2 3 1 1 2 3 1 1 2 3 1 is a schematic diagram of a structure of a display apparatus. As shown in, the display apparatus may include a timing controller, a data driver, a scan driver, a light emitting driver and a pixel array. The timing controller is connected to the data driver, the scan driver and the light emitting driver respectively, the data driver is connected to a plurality of data signal lines (Dto Dn) respectively, the scan driver is connected to a plurality of scan signal lines (Sto Sm) respectively, and the light emitting driver is connected to a plurality of light emitting signal lines (Eto Eo) respectively. The pixel array may include a plurality of sub-pixels Pxij, i and j may be natural numbers, at least one sub-pixel Pxij may include a circuit unit and a light emitting device connected to the circuit unit, and the circuit unit may include at least one scan signal line, at least one data signal line, at least one light emitting signal line and a pixel driving circuit. In an exemplary implementation, the timing controller may provide a gray value and a control signal, which are suitable for the specification of the data driver, to the data driver; provide a clock signal, a scan start signal, etc., which are suitable for the specification of the scan driver, to the scan driver; and provide a clock signal, a transmit stop signal, etc., which are suitable for the specification of the light emitting driver, to the light emitting driver. The data driver may generate a data voltage to be provided to the data lines D, D, D, . . . , and Dn, by using the gray value and the control signal received from the timing controller. For example, the data driver may sample the gray value using the clock signal and apply a data voltage corresponding to the gray value to the data signal lines Dto Dn by taking a pixel row as a unit, wherein n may be a natural number. The scan driver may generate a scan signal to be provided to the scan signal lines S, S, S, . . . , and Sm, by receiving the clock signal, the scan start signal, etc. from the timing controller. For example, the scan driver may provide sequentially a scan signal with a turn-on level pulse to the scan signal lines Sto Sm. For example, the scan driver may be constructed in a form of a shift register and may generate a scan signal in such a manner as to transmit sequentially the scan start signal provided in a form of a turn-on level pulse to a next-stage circuit under the control of the clock signal, wherein m may be a natural number. The light emitting driver may generate a transmit signal to be provided to the light emitting signal lines E, E, E, . . . , and Eo, by receiving the clock signal, the transmit stop signal, etc. from the timing controller. For example, the light emitting driver may provide sequentially a transmit signal with a turn-off level pulse to the light emitting signal lines Eto Eo. For example, the light emitting driver may be constructed in a form of a shift register and may generate a transmit signal in such a manner as to transmit sequentially the transmit stop signal provided in a form of a turn-off level pulse to a next-stage circuit under the control of the clock signal, wherein o may be a natural number.

2 FIG. 2 FIG. 1 2 3 1 2 3 1 2 3 1 2 3 is a schematic diagram of a planar structure of a display substrate. As shown in, the display substrate may include a plurality of pixel units P arranged in a matrix, at least one of the plurality of pixel units P includes a first sub-pixel Pemitting light of a first color, a second sub-pixel Pemitting light of a second color and a third sub-pixel Pemitting light of a third color, and the first sub-pixel P, the second sub-pixel P, and the third sub-pixel Peach include a pixel driving circuit and a light emitting device. The pixel driving circuit in the first sub-pixel P, the second sub-pixel Pand the third sub-pixel Pis connected to a scan signal line, a data signal line and a light emitting signal line respectively. The pixel driving circuit is configured to receive a data voltage transmitted by the data signal line under the control of the scan signal line and the light emitting signal line, and output a corresponding current to the light emitting device. The light emitting device in the first sub-pixel P, the second sub-pixel Pand the third sub-pixel Pis connected to the pixel driving circuit of the sub-pixel where the light emitting device is located, and is configured to emit light with a corresponding luminance in response to a current output by the pixel driving circuit of the sub-pixel where the light emitting device is located.

In an exemplary implementation, the pixel unit P may include a red (R) sub-pixel, a green (G) sub-pixel and a blue (B) sub-pixel, or may include a red sub-pixel, a green sub-pixel, a blue sub-pixel and a white (W) sub-pixel, which is not limited in the present disclosure. In an exemplary implementation, the shape of the sub-pixel in the pixel unit may be a rectangle, a rhombus, a pentagon or a hexagon. When the pixel unit includes three sub-pixels, the three sub-pixels may be arranged side by side horizontally, side by side vertically, or in the form of “”; and when the pixel unit includes four sub-pixels, the four sub-pixels may be arranged side by side horizontally, side by side vertically, or in the shape of a square, which is not limited in the present disclosure.

3 FIG. 3 FIG. 102 101 103 102 101 104 103 101 is a schematic diagram of a sectional structure of a display substrate, which illustrates a structure of three sub-pixels of an OLED display substrate. As shown in, in a plane perpendicular to the display substrate, the display substrate may include a driving circuit layerarranged on a base substrate, a light emitting devicearranged at one side of the driving circuit layeraway from the base substrate, and an encapsulation layerarranged at one side of the light emitting deviceaway from the base substrate. In some possible implementations, the display substrate may include other film layers, such as a photo spacer, which is not limited in the present disclosure herein.

102 102 210 211 3 FIG. In an exemplary implementation, the driving circuit layerof each sub-pixel may include a plurality of transistors and a storage capacitor constituting a pixel driving circuit.illustrates an example in which each sub-pixel includes one driving transistor and one storage capacitor. In some possible implementations, the driving circuit layerof each sub-pixel may include: a first insulating layer arranged on the base substrate; an active layer arranged on the first insulating layer; a second insulating layer overlying the active layer; a gate electrode and a first polar plate arranged on the second insulating layer; a third insulating layer overlying the gate electrode and the first polar plate; a second polar plate arranged on the third insulating layer; a fourth insulating layer overlying the second polar plate, the second, third and fourth insulating layers being provided with a via hole exposing the active layer; a source electrode and a drain electrode arranged on the fourth insulating layer, the source electrode and the drain electrode being connected respectively to the active layer through the via hole; and a planarization layer overlying the aforementioned structures, the planarization layer being provided with a via hole exposing the drain electrode. The active layer, the gate electrode, the source electrode and the drain electrode form a driving transistor, and the first polar plate and the second polar plate form a storage capacitor.

103 301 302 303 304 301 210 302 301 301 303 301 304 303 303 303 301 304 In an exemplary implementation, the light emitting devicemay include an anode, a pixel definition layer, an organic light emitting layerand a cathode. The anodeis arranged on the planarization layer, and is connected to the drain electrode of the driving transistorthrough the via hole provided in the planarization layer; the pixel definition layeris arranged on the anodeand the planarization layer, and is provided with a pixel opening exposing the anode; the organic light emitting layeris at least partially arranged in the pixel opening, and is connected to the anode; the cathodeis arranged on the organic light emitting layer, and is connected to the organic light emitting layer; and the organic light emitting layeremits light of a corresponding color under the driving of the anodeand the cathode.

104 401 402 403 401 403 402 402 401 403 103 In an exemplary implementation, the encapsulation layermay include a first encapsulation layer, a second encapsulation layerand a third encapsulation layerthat are stacked. The first encapsulation layerand the third encapsulation layermay be made of an inorganic material, and the second encapsulation layermay be made of an organic material, and the second encapsulation layeris arranged between the first encapsulation layerand the third encapsulation layer, which may ensure that external water vapor cannot enter the light emitting device.

303 In an exemplary implementation, the organic light emitting layermay include a hole injection layer (HIL), a hole transport layer (HTL), an electron block layer (EBL), a light emitting layer (EML), a hole block layer (HBL), an electron transport layer (ETL) and an electron injection layer (EIL) that are stacked. In an exemplary implementation, the hole injection layers and the electron injection layers of all the sub-pixels may be connected together as a common layer, the hole transport layers and the electron transport layers of all the sub-pixels may be connected together as a common layer, the hole block layers of all the sub-pixels may be connected together as a common layer, and the light emitting layers and the electron block layers of adjacent sub-pixels may be slightly overlapped with each other, or may be isolated from each other.

4 FIG. 4 FIG. 1 8 10 1 2 3 1 2 In an exemplary implementation, the pixel driving circuit may be of a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C or 8T2C structure.is a schematic diagram of an equivalent circuit of a pixel driving circuit, which illustrates an 8T2C structure. As shown in, the pixel driving circuit may include eight transistors (a first transistor Tto an eighth transistor T) and two capacitors (a storage capacitor Cst and a threshold capacitor CVth), and the pixel driving circuit is connected tosignal lines including a first scan signal line S, a second scan signal line S, a third scan signal line S, a first light emitting signal line EM, a second light emitting signal line EM, a reference signal line REF, an initial signal line INIT, a data signal line DATA, a first power line VDD and a second power line VSS.

1 1 1 1 2 2 2 2 1 2 3 3 1 3 3 3 4 3 4 4 8 5 3 5 5 2 6 2 6 6 7 1 7 3 7 8 2 8 4 8 1 1 2 1 In an exemplary implementation, a gate electrode of the first transistor Tis connected to the first scan signal line S, a first pole of the first transistor Tis connected to the data signal line DATA, and a second pole of the first transistor Tis connected to a second node N. A gate electrode of the second transistor Tis connected to the second scan signal line S, a first pole of the second transistor Tis connected to a first node N, and a second pole of the second transistor Tis connected to a third node N. A gate electrode of the third transistor Tis connected to the first node N, a first pole of the third transistor Tis connected to the first power line VDD, and a second pole of the third transistor Tis connected to the third node N. A gate electrode of the fourth transistor Tis connected to the third scan signal line S, a first pole of the fourth transistor Tis connected to the initial signal line INIT, and a second pole of the fourth transistor Tis connected to a first pole of the eighth transistor T. A gate electrode of the fifth transistor Tis connected to the third scan signal line S, a first pole of the fifth transistor Tis connected to the reference signal line REF, and a second pole of the fifth transistor Tis connected to the second node N. A gate electrode of the sixth transistor Tis connected to the second scan signal line S, a first pole of the sixth transistor Tis connected to the initial signal line INIT, and a second pole of the sixth transistor Tis connected to a first pole of the light emitting device. A gate electrode of the seventh transistor Tis connected to the first light emitting signal line EM, a first pole of the seventh transistor Tis connected to the third node N, and a second pole of the seventh transistor Tis connected to the first pole of the light emitting device. A gate electrode of the eighth transistor Tis connected to the second light emitting signal line EM, the first pole of the eighth transistor Tis connected to the second pole of the fourth transistor T, and a second pole of the eighth transistor Tis connected to the first node N. A first end of the storage capacitor Cst is connected to the first power line VDD, and a second end of the storage capacitor Cst is connected to the first node N. A first end of the threshold capacitor CVth is connected to the second node N, and a second end of the threshold capacitor CVth is connected to the first node N.

1 8 1 8 In an exemplary implementation, the first transistor Tto the eighth transistor Tmay be P-type transistors or N-type transistors. Using the same type of transistors in the pixel driving circuit may simplify the process flow, reduce the process difficulty of a display panel, and improve the product yield. In some possible implementations, the first transistor Tto the eighth transistor Tmay include P-type transistors and N-type transistors.

In an exemplary implementation, the second pole of the light emitting device is connected to the second power line VSS, a signal of the second power line VSS is a low-level signal and a signal of the first power line VDD is a continuously provided high-level signal.

2 3 2 3 3 2 2 3 In an exemplary implementation, the second scan signal line Sis a scan signal line in the pixel driving circuit of the present display row, and the third scan signal line Sis a scan signal line in the pixel driving circuit of the previous display row, that is, for the nth display row, the second scan signal line Sis S(n) and the third scan signal line Sis S(n−1), the third scan signal line Sof the present display row may be the same signal line as the second scan signal line Sin the pixel driving circuit of the previous display row, or the second scan signal line Sof the present display row may be the same signal line as the third scan signal line Sin the pixel driving circuit of the next display row, so as to reduce the signal lines of the display panel and realize the narrow bezel of the display panel.

1 2 1 2 1 1 In an exemplary implementation, the first light emitting signal line EMis a light emitting signal line in the pixel driving circuit of the present display row, and the second light emitting signal line EMis a light emitting signal line in the pixel driving circuit of the next display row, that is, for the nth display row, the first light emitting signal line EMis EM(n) and the second light emitting signal line EMis EM(n+1), and the first light emitting signal line EMof the present display row may be the same signal line as the first light emitting signal line EMin the pixel driving circuit of the next display row, so as to reduce the signal lines of the display panel and realize the narrow bezel of the display panel.

1 2 3 1 2 In an exemplary implementation, the first scan signal line S, the second scan signal line S, the third scan signal line S, the first light emitting signal line EM, the second light emitting signal line EMand the initial signal line INIT may extend along a horizontal direction, and the data signal line DATA, the first power line VDD, the second power line VSS and the reference signal line REF may extend along a vertical direction.

In an exemplary implementation, the light emitting device may be an organic light emitting device (OLED), and includes a first pole (anode), an organic light emitting layer, and a second pole (cathode) that are stacked.

5 FIG. 4 FIG. 4 FIG. 1 8 1 2 3 1 2 is a working timing diagram of a pixel driving circuit. An exemplary embodiment of the present disclosure will be described below through a working process of the pixel driving circuit shown in. The pixel driving circuit inincludes eight transistors (the first transistor Tto the eighth transistor T), two capacitors (the storage capacitor Cst and the threshold capacitor CVth) and 10 signal lines (the first scan signal line S, the second scan signal line S, the third scan signal line S, the first light emitting signal line EM, the second light emitting signal line EM, the reference signal line REF, the initial signal line INIT, the data signal line DATA, the first power line VDD and the second power line VSS). All the eight transistors are P-type transistors.

In an exemplary implementation, the working process of the pixel driving circuit may include the following stages.

1 2 3 1 2 1 3 4 5 2 2 8 4 8 1 1 2 3 6 7 In a first stage A, which is referred to as a reset stage, the signals of the second light emitting signal line EMand the third scan signal line Sare low-level signals, and the signals of the first scan signal line S, the second scan signal line Sand the first light emitting signal line EMare high-level signals. The signal of the third scan signal line Sis a low-level signal, which causes the fourth transistor Tand the fifth transistor Tto be turned on, and a reference signal of the reference signal line REF is provided to the second node Nwhich is reset to a reference voltage Vref of the reference signal. The signal of the second light emitting signal line EMis a low-level signal, which causes the eighth transistor Tto be turned on, and as the fourth transistor Tand the eighth transistor Tare turned on, an initial signal of the initial signal line INIT is provided to the first node Nwhich is reset to an initial voltage Vinit of the initial signal. In this stage, the first transistor T, the second transistor T, the third transistor T, the sixth transistor Tand the seventh transistor Tare turned off, and the OLED does not emit light in this stage.

2 2 3 1 1 2 2 2 6 2 1 3 3 1 1 3 3 6 3 5 2 1 3 7 8 In a second stage A, which is referred to as a threshold acquisition stage, the signals of the second scan signal line Sand the third scan signal line Sare low-level signals, and the signals of the first scan signal line S, the first light emitting signal line EMand the second light emitting signal line EMare high-level signals. The signal of the second scan signal line Sis a low-level signals, which causes the second transistor Tand the sixth transistor Tto be turned on. The second transistor Tis turned on, such that potentials of the first node Nand the third node Nare the same, and the third transistor Tforms a “diode connected” structure. The first power line VDD charges the first node N, and the first node Nis charged until it reaches a potential of Vdd−|Vth|. Information carrying a threshold voltage of the third transistor Tis stored in the storage capacitor Cst. Vdd is a supply voltage of the first power line VDD, and Vth is a threshold voltage of the third transistor T. The sixth transistor Tis turned on, such that an initial voltage of the initial signal line INIT is provided to a first pole of the OLED to initialize (reset) the first pole of the OLED and clear its internal pre-stored voltage. The signal of the third scan signal line Sis a low-level signal, and the fifth transistor Tkeeps being turned on, so that the second node Nmaintains the reference voltage Vref of the reference signal. In this stage, the first transistor T, the third transistor T, the seventh transistor Tand the eighth transistor Tare turned off, and the OLED does not emit light in this stage.

3 1 2 3 1 2 1 1 2 2 1 2 1 In a third stage A, which is referred to as a data writing stage, the signal of the first scan signal line Sis a low-level signal, and the signals of the second scan signal line S, the third scan signal line S, the first light emitting signal line EMand the second light emitting signal line EMare high-level signals. The signal of the first scan signal line Sis a low-level signal, which causes the first transistor Tto be turned on. The data signal line DATA outputs a data voltage to the second node N, and the second node Nwrites the data voltage Vdt. After the signals of the first node Nand the second node Nare superimposed, the potential of the first node Nbecomes:

4 1 1 2 3 2 1 7 1 3 3 7 1 2 3 1 3 In a fourth stage A, which is referred to as a light emitting stage, the signal of the first light emitting signal line EMis a low-level signal, and the signals of the first scan signal line S, the second scan signal line S, the third scan signal line Sand the second light emitting signal line EMare high-level signals. The signal of the first light emitting signal line EMis a low-level signal, which causes the seventh transistor Tto be turned on. The potential of the first node Ncauses the third transistor Tto be turned on. The supply voltage output by the first power line VDD provides a driving voltage to the first pole of the OLED through the third transistor Tand the seventh transistor Twhich are turned on, to drive the OLED to emit light. In this stage, the first node Nand the second node Nare suspended, and their original potentials are maintained by means of the storage capacitor Cst. In a driving process of the pixel driving circuit, a driving current flowing through the third transistor T(driving transistor) is determined by a voltage difference between its gate electrode and first pole. Therefore, according to the potential of the first node N, the driving current flowing through the third transistor Tis:

3 3 3 wherein I is the driving current flowing through the third transistor T, that is, a driving current which drives the OLED, β is a constant, Vdt is the data voltage output by the data signal line DATA, and Vref is the reference voltage output by the reference signal line REF. There is no information of the threshold voltage of the third transistor Tin the formula of the driving current, so the pixel driving circuit has a self-compensation effect on the threshold voltage of the third transistor T.

1 2 1 2 1 2 1 1 2 N1 In the working process of the pixel driving circuit, in the reset stage, the potential of the first node Nis the initial voltage Vinit, and the potential of the second node Nis the reference voltage Vref. In the threshold acquisition stage, the potential of the first node Nis Vdd−|Vth|, and the potential of the second node Nis the reference voltage Vref. In the data writing stage, the potential of the first node Nis V=Vdd−|Vth|+(Vdt−Vref)*Cvth/(Cvth+Cst), and the potential of the second node Nis the data voltage Vdt. In the light emitting stage, the potential of the first node Nis VN, and the potential of the second node Nis the data voltage Vdt. A feature of the pixel driving circuit of an exemplary embodiment of the present disclosure is that the threshold acquisition stage and the data writing stage are separated in time, and the acquisition time of the threshold voltage Vth may be increased through timing control, so as to improve the compensation ability of the threshold voltage Vth of the pixel driving circuit.

6 FIG. 6 FIG. 21 22 23 24 25 31 71 72 73 74 26 33 27 34 71 74 71 74 73 28 28 73 28 74 is a schematic diagram of a structure of a display substrate in accordance with an exemplary embodiment of the present disclosure, which illustrates a planar structure of three sub-pixels. As shown in, in a plane parallel to the display substrate, a first scan signal line, a second scan signal line, a third scan signal line, a first light emitting control line, a second light emitting control line, an initial signal line, a first power line, a reference signal line, a second power line, a data signal line, a pixel driving circuit and a light emitting device are provided in at least one sub-pixel. The pixel driving circuit may include a storage capacitor, a threshold capacitor and a plurality of transistors. Each of the transistors may include an active layer, a gate electrode, a first pole and a second pole; the storage capacitor includes a storage capacitor first polar plateand a storage capacitor second polar plate; and the threshold capacitor includes a threshold capacitor first polar plateand a threshold capacitor second polar plate. In an exemplary implementation, the pixel driving circuit is connected to the first power lineand the data signal line, respectively. The first power lineprovides a high-level signal to the pixel driving circuit, the data signal lineprovides a data signal to the pixel driving circuit, and the light emitting device is connected to the second power linewhich provides a low-level signal to the light emitting device. In an exemplary implementation, the display substrate further includes a first electrode. The first electrodeis connected to the second power line, and there is an overlapping area between an orthographic projection of the first electrodeon the plane of the display substrate and an orthographic projection of the data signal lineon the plane of the display substrate.

28 74 28 In a plane perpendicular to the display substrate, the display substrate may include a semiconductor layer and a plurality of conducting layers arranged sequentially on a base substrate, and the first electrodeis arranged in at least one conducting layer. In an exemplary embodiment, the plurality of conducting layers may include a first conducting layer, a second conducting layer, a third conducting layer and a fourth conducting layer arranged sequentially on the semiconductor layer, the data signal linemay be arranged in the fourth conducting layer, and the first electrodemay be arranged in the first conducting layer or on the second conducting layer or on the third conducting layer.

21 22 23 24 25 26 27 31 33 34 71 72 72 74 In an exemplary embodiment, the semiconductor layer may include the active layers of the plurality of transistors, the first conducting layer may include the first scan signal line, the second scan signal line, the third scan signal line, the first light emitting control line, the second light emitting control line, the storage capacitor first polar plateand the threshold capacitor first polar plate, the second conducting layer may include the initial signal line, the storage capacitor second polar plateand the threshold capacitor second polar plate, the third conducting layer may include the first power lineand the reference signal line, and the fourth conducting layer may include the second power lineand the data signal line.

21 22 23 24 25 26 27 31 33 34 71 72 73 74 In an exemplary embodiment, the first scan signal line, the second scan signal line, the third scan signal line, the first light emitting control lineand the second light emitting control lineextend along a first direction X, and the storage capacitor first polar plateand the threshold capacitor first polar plateare connected to each other to form an integrated structure. The initial signal lineextends along the first direction X, and the storage capacitor second polar plateand the threshold capacitor second polar plateare spaced apart from each other. The first power line, the reference signal line, the second power lineand the data signal lineextend along a second direction Y. The first direction X may be an extending direction of the scan signal line, and the second direction Y may be an extending direction of the data signal line.

33 33 In an exemplary embodiment, the storage capacitor second polar platesof adjacent sub-pixels in one sub-pixel row are connected to each other by a connecting line, and the storage capacitor second polar platesconnected to each other in one sub-pixel row also serve as first power connecting lines, so that all sub-pixels in one sub-pixel row have the same supply voltage, thereby improving display uniformity.

32 72 In an exemplary embodiment, the second conducting layer may include a first connecting line, which extends along the first direction X and is connected to the reference signal line, so that all sub-pixels in one sub-pixel row have the same reference voltage, thereby improving display uniformity.

1 2 3 4 5 1 74 1 34 2 26 27 2 3 3 26 27 3 71 4 31 4 26 27 5 72 5 34 In an exemplary embodiment, the pixel driving circuit may include the first transistor T, the second transistor T, the third transistor T, the fourth transistor Tand the fifth transistor T. The first pole of the first transistor Tis connected to the data signal line, and the second pole of the first transistor Tis connected to the threshold capacitor second polar plate; the first pole of the second transistor Tis connected to the storage capacitor first polar plateand the threshold capacitor first polar plate, and the second pole of the second transistor Tis connected to the second pole of the third transistor T; the gate electrode of the third transistor Tis connected to the storage capacitor first polar plateand the threshold capacitor first polar plate, and the first pole of the third transistor Tis connected to the first power line; the first pole of the fourth transistor Tis connected to the initial signal line, and the second pole of the fourth transistor Tis connected to the storage capacitor first polar plateand the threshold capacitor first polar plate; and the first pole of the fifth transistor Tis connected to the reference signal line, and the second pole of the fifth transistor Tis connected to the threshold capacitor second polar plate.

1 2 4 5 35 36 37 38 35 4 36 5 37 1 38 2 In an exemplary embodiment, the first transistor T, the second transistor T, the fourth transistor Tand the fifth transistor Tare double-gate transistors. The second conducting layer may include a first sub-polar plate, a second sub-polar plate, a third sub-polar plateand a fourth sub-polar plate. The first sub-polar plateis configured to introduce parasitic capacitance at a double-gate intermediate node of the fourth transistor T, the second sub-polar plateis configured to introduce parasitic capacitance at a double-gate intermediate node of the fifth transistor T, the third sub-polar plateis configured to introduce parasitic capacitance at a double-gate intermediate node of the first transistor T, and the fourth sub-polar plateis configured to introduce parasitic capacitance at a double-gate intermediate node of the second transistor T.

4 35 35 35 31 In an exemplary embodiment, the fourth transistor Tat least includes a fourth active layer and two fourth gate electrodes, and there is an overlapping area between an orthographic projection of the first sub-polar plateon the base substrate and an orthographic projection of the fourth active layer, located between the two fourth gate electrodes, on the base substrate. The two fourth gate electrodes are arranged in the first conducting layer, the first sub-polar plateis arranged in the second conducting layer, and the first sub-polar plateis connected to the initial signal line.

5 36 36 36 71 In an exemplary embodiment, the fifth transistor Tat least includes a fifth active layer and two fifth gate electrodes, and there is an overlapping area between an orthographic projection of the second sub-polar plateon the base substrate and an orthographic projection of the fifth active layer, located between the two fifth gate electrodes, on the base substrate. The two fifth gate electrodes are arranged in the first conducting layer, the second sub-polar plateis arranged in the second conducting layer, and the second sub-polar plateis connected to the first power linethrough a via hole.

1 37 37 37 71 In an exemplary embodiment, the first transistor Tat least includes a first active layer and two first gate electrodes, and there is an overlapping area between an orthographic projection of the third sub-polar plateon the base substrate and an orthographic projection of the first active layer, located between the two first gate electrodes, on the base substrate. The two first gate electrodes are arranged in the first conducting layer, the third sub-polar plateis arranged in the second conducting layer, and the third sub-polar plateis connected to the first power linethrough a via hole.

3 38 38 38 71 In an exemplary embodiment, the second transistor Tat least includes a second active layer and two second gate electrodes, and there is an overlapping area between an orthographic projection of the fourth sub-polar plateon the base substrate and an orthographic projection of the second active layer, located between the two second gate electrodes, on the base substrate. The two second gate electrodes are arranged in the first conducting layer, the fourth sub-polar plateis arranged in the second conducting layer, and the fourth sub-polar plateis connected to the first power linethrough a via hole.

41 42 44 45 46 47 49 41 2 42 8 1 44 1 5 45 4 6 46 4 8 47 2 3 7 6 7 49 28 In an exemplary embodiment, the third conducting layer may include a first connecting electrode, a second connecting electrode, a third connecting electrode, a fourth connecting electrode, a fifth connecting electrode, a sixth connecting electrode, a seventh connecting electrode, an eighth connecting electrode and an interlayer connecting electrode. The first connecting electrodeserves as the first pole of the second transistor T, the second connecting electrodeserves as the second pole of the eighth transistor T, the third connecting electrode serves as the first pole of the first transistor T, the fourth connecting electrodealso serves as the second pole of the first transistor Tand the second pole of the fifth transistor T, the fifth connecting electrodealso serves as the first pole of the fourth transistor Tand the first pole of the sixth transistor T, the sixth connecting electrodealso serves as the second pole of the fourth transistor Tand the first pole of the eighth transistor T, the seventh connecting electrodealso serves as the second pole of the second transistor T, the second pole of the third transistor Tand the first pole of the seventh transistor T, the eighth connecting electrode also serves as the second pole of the sixth transistor Tand the second pole of the seventh transistor T, and the interlayer connecting electrodeis configured to connect the first electrodewith the second power line.

51 In an exemplary embodiment, the fourth conducting layer may include an anode connecting electrodeconfigured to connect the eighth connecting electrode with the anode of the light emitting device.

28 74 In an exemplary embodiment, the first electrodemay include a first electrode segment extending along the first direction X and a second electrode segment extending along the second direction Y, there is an overlapping area between an orthographic projection of the second electrode segment on the base substrate and an orthographic projection of the data signal lineon the base substrate, one end of the first electrode segment is connected to the second electrode segment, and the other end of the first electrode segment is connected to the second power line through a via hole.

75 73 49 49 28 In an exemplary embodiment, the third conducting layer may include a second power connecting linehaving one end connected to the second power lineand the other end connected to the interlayer connecting electrodethrough a via hole, and the interlayer connecting electrodeis connected to the first electrodethrough a via hole.

In an exemplary implementation, the display substrate may include a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer and a fifth insulating layer. The first insulating layer is arranged between the base substrate and the semiconductor layer, the second insulating layer is arranged between the semiconductor layer and the first conducting layer, the third insulating layer is arranged between the first conducting layer and the second conducting layer, the fourth insulating layer is arranged between the second conducting layer and the third conducting layer, and the fifth insulating layer is arranged between the third conducting layer and the fourth conducting layer.

In the display substrate in accordance with an exemplary embodiment of the present disclosure, a first electrode is arranged, there is an overlapping area between an orthographic projection of the first electrode on the base substrate and an orthographic projection of the data signal line on the base substrate, and the first electrode is connected to the second power line, thus effectively avoiding the influence of jumps of the data voltage on the critical node, thereby preventing the jumps of the data voltage from affecting the potential of the critical node of the pixel driving circuit, and improving the display effect.

Exemplary description is made below through a process of manufacturing a display substrate. “Patterning process” mentioned in the present disclosure includes photoresist coating, mask exposure, development, etching, photoresist stripping, etc., for metal materials, inorganic materials or transparent conducting materials, and includes organic material coating, mask exposure, development, etc., for organic materials. Any one or more of sputtering, evaporation and chemical vapor deposition may be used for deposition, any one or more of spray coating, spin coating and inkjet printing may be used for coating, and any one or more of dry etching and wet etching may be used for etching, which are not limited in the present disclosure. A “thin film” refers to a layer of thin film manufactured with a certain material on a base substrate using deposition, coating or other processes. If the “thin film” does not need the patterning process in the entire manufacturing process, the “thin film” may also be called a “layer”. If the “thin film” needs the patterning process in the entire manufacturing process, the “thin film” is called a “thin film” before the patterning process and is called a “layer” after the patterning process. The “layer” which has experienced the patterning process includes at least one “pattern”. “A and B being arranged in the same layer” in the present disclosure means that A and B are formed simultaneously through a single patterning process, and the “thickness” of a film layer is the dimension of the film layer in a direction perpendicular to the display substrate. In an exemplary embodiment of the present disclosure, “an orthographic projection of B being located within the range of an orthographic projection of A” means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B. “An orthographic projection of A containing an orthographic projection of B” means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

In an exemplary implementation, taking the case of three sub-pixels in one sub-pixel row in the display substrate as an example, the process of manufacturing the display substrate may include the following operations.

7 FIG. (1) A pattern of a semiconductor layer is formed. In an exemplary embodiment, forming a pattern of a semiconductor layer may include: depositing sequentially a first insulating thin film and a semiconductor thin film on a base substrate, and patterning the semiconductor thin film through a patterning process to form a first insulating layer overlying the base substrate and a semiconductor layer arranged on the first insulating layer, as shown in.

1 8 11 1 13 3 15 5 12 2 16 6 17 7 14 4 18 8 14 16 16 14 In an exemplary embodiment, the semiconductor layer of at least one sub-pixel may include the first active layer of the first transistor Tto the eighth active layer of the eighth transistor T, the first active layerof the first transistor T, the third active layerof the third transistor Tand the fifth active layerof the fifth transistor Tare arranged separately, the second active layerof the second transistor T, the sixth active layerof the sixth transistor Tand the seventh active layerof the seventh transistor Tare connected to each other to form an integrated structure, the fourth active layerof the fourth transistor Tand the eighth active layerof the eighth transistor Tare connected to each other to form an integrated structure, the fourth active layerof the present sub-pixel is connected to the sixth active layerof the sub-pixel in the previous sub-pixel row, and the sixth active layerof the present sub-pixel is connected to the fourth active layerof the sub-pixel in the next sub-pixel row.

In an exemplary embodiment, the active layer of each transistor may include a first region, a second region, and a channel region located between the first region and the second region.

11 11 1 11 11 2 11 11 1 11 11 2 11 In an exemplary embodiment, the first active layeris in the shape of “”, the two ends of “” are a first region-of the first active layerand a second region-of the first active layer, respectively. The first region-of the first active layerand the second region-of the first active layerare arranged separately.

12 12 1 12 12 2 12 12 1 12 12 2 12 17 1 17 12 2 12 17 1 17 In an exemplary embodiment, the second active layeris in the shape of “lying L”, and the two ends of the “lying L” are a first region-of the second active layerand a second region-of the second active layer, respectively. The first region-of the second active layeris arranged separately, and the second region-of the second active layeralso serves as a first region-of the seventh active layer, i.e., the second region-of the second active layerand the first region-of the seventh active layerare connected to each other.

13 13 1 13 13 2 13 13 1 13 11 13 2 13 12 In an exemplary embodiment, the third active layeris in the shape of a wavy line extending along the second direction Y, and the two ends of the wavy line are a first region-of the third active layerand a second region-of the third active layer, respectively. The first region-of the third active layeris close to the first active layerand the second region-of the third active layeris close to the second active layer.

14 14 1 14 14 2 14 14 1 14 16 1 16 14 1 14 16 1 16 14 2 14 18 1 18 14 2 14 18 1 18 In an exemplary embodiment, the fourth active layeris in the shape of a bifold line extending along the second direction Y, and the two ends of the bifold line are a first region-of the fourth active layerand a second region-of the fourth active layer, respectively. The first region-of the fourth active layeralso serves as a first region-of the sixth active layerof the sub-pixel in the previous sub-pixel row, that is, the first region-of the fourth active layerof the present sub-pixel and the first region-of the sixth active layerof the sub-pixel in the previous sub-pixel row are connected to each other. The second region-of the fourth active layeralso serves as a first region-of the eighth active layer, that is, the second region-of the fourth active layerand the first region-of the eighth active layerare connected to each other.

15 15 1 15 15 2 15 15 1 15 15 2 15 In an exemplary embodiment, the fifth active layeris in the shape of “”, and the two ends of “” are a first region-of the fifth active layerand a second region-of the fifth active layer, respectively. The first region-of the fifth active layerand the second region-of the fifth active layerare arranged separately.

16 16 1 16 16 2 16 16 1 16 14 1 14 16 1 16 14 1 14 16 2 16 17 2 17 16 2 16 17 2 17 In an exemplary embodiment, the sixth active layeris in the shape of “-”, and the two ends of “-” are the first region-of the sixth active layerand a second region-of the sixth active layer, respectively. The first region-of the sixth active layeralso serves as the first region-of the fourth active layerof the sub-pixel in the next sub-pixel row, that is, the first region-of the sixth active layerof the present sub-pixel and the first region-of the fourth active layerof the sub-pixel in the next sub-pixel row are connected to each other. The second region-of the sixth active layeralso serves as a second region-of the seventh active layer, i.e., the second region-of the sixth active layerand the second region-of the seventh active layerare connected to each other.

17 17 1 17 17 2 17 17 1 17 12 2 12 17 2 17 16 2 16 In an exemplary embodiment, the seventh active layeris in the shape of “1”, and the two ends of “1” are the first region-of the seventh active layerand the second region-of the seventh active layer, respectively. The first region-of the seventh active layeralso serves as the second region-of the second active layer, and the second region-of the seventh active layeralso serves as the second region-of the sixth active layer.

18 18 1 18 18 2 18 18 1 18 14 2 14 18 2 18 In an exemplary embodiment, the eighth active layeris in the shape of “1”, and the two ends of “1” are the first region-of the eighth active layerand a second region-of the eighth active layer, respectively. The first region-of the eighth active layeralso serves as the second region-of the fourth active layer, and the second region-of the eighth active layeris arranged separately.

21 22 23 24 25 26 27 28 8 FIG. (2) A pattern of a first conducting layer is formed. In an exemplary embodiment, forming a pattern of a first conducting layer may include: depositing sequentially a second insulating thin film and a first metal thin film on the base substrate, on which the aforementioned pattern is formed, and patterning the first metal thin film through a patterning process to form a second insulating layer overlying the pattern of the semiconductor layer and a pattern of a first conducting layer arranged on the second insulating layer. The pattern of the first conducting layer at least includes: the first scan signal line, the second scan signal line, the third scan signal line, the first light emitting control line, the second light emitting control line, the storage capacitor first polar plate, the threshold capacitor first polar plateand the first electrode, as shown in.

21 22 23 24 25 26 27 28 21 22 26 22 27 21 24 22 26 23 25 21 27 25 21 23 In an exemplary embodiment, the first scan signal line, the second scan signal line, the third scan signal line, the first light emitting control lineand the second light emitting control lineextend along the first direction X. The storage capacitor first polar plate, the threshold capacitor first polar plateand the first electrodeare arranged between the first scan signal lineand the second scan signal line, and are located in the middle of the sub-pixel in the second direction Y. The storage capacitor first polar plateis close to the second scan signal line, and the threshold capacitor first polar plateis close to the first scan signal line. The first light emitting control lineis arranged at one side of the second scan signal lineaway from the storage capacitor first polar plate, the third scan signal lineand the second light emitting control lineare arranged at one side of the first scan signal lineaway from the threshold capacitor first polar plate, and the second light emitting control lineis arranged between the first scan signal lineand the third scan signal line.

28 28 1 28 2 28 1 28 2 28 1 28 2 In an exemplary embodiment, the first electrodeis in the shape of a fold line, and includes a first electrode segment-extending along the first direction X and a second electrode segment-extending along the second direction Y. An end of the first electrode segment-and an end of the second electrode segment-which are adjacent to each other are connected to each other, the first electrode segment-is configured to be connected to a second power line formed subsequently, and the second electrode segment-overlaps with a data signal line formed subsequently, and is configured to avoid the influence of jumps of the data voltage on the data signal line on the critical node, preventing the jumps of the data voltage from affecting the potential of the critical node of the pixel driving circuit, thereby improving the display effect.

26 27 28 2 28 13 In an exemplary embodiment, the outline of the storage capacitor first polar platemay be in the shape of a rectangle, corners of which may be provided with a chamfer. The outline of the threshold capacitor first polar platemay be in the shape of a rectangle, a corner of the rectangle close to the second electrode segment-of the first electrodeis provided with a groove, a corner of the rectangle close to the third active layeris provided with a groove, and the corners may be provided with a chamfer.

26 27 26 27 In an exemplary embodiment, the storage capacitor first polar plateand the threshold capacitor first polar plateare connected to each other through a connecting line. In a possible exemplary embodiment, the storage capacitor first polar plateand the threshold capacitor first polar plateare connected to each other to form an integrated structure.

21 22 23 24 25 In an exemplary embodiment, the first scan signal line, the second scan signal line, the third scan signal line, the first light emitting control lineand the second light emitting control linemay be arranged at equal intervals or at unequal intervals, the interval being a dimension in the second direction Y.

22 22 23 23 In an exemplary embodiment, a plurality of second gate blocks may be arranged on the second scan signal line, each second gate block is arranged in one sub-pixel, one end of the second gate block is connected to the second scan signal line, and the other end of the second gate block extends along the second direction Y to form a double-gate second transistor. A plurality of third gate blocks may be arranged on the third scan signal line, each third gate block is arranged in one sub-pixel, one end of the third gate block is connected to the third scan signal line, and the other end of the third gate block extends along the opposite direction of the second direction Y to form a double-gate fourth transistor.

21 11 1 22 12 2 26 13 26 3 23 14 4 23 15 5 22 16 6 24 17 7 25 18 8 In an exemplary embodiment, an area where the first scan signal lineoverlaps with the first active layerserves as the gate electrode of the first transistor T(double-gate structure), an area where the second scan signal lineoverlaps with the second active layerserves as the gate electrode of the second transistor T(double-gate structure), there is an overlapping area between an orthographic projection of the storage capacitor first polar plateon the base substrate and an orthographic projection of the third active layeron the base substrate, the storage capacitor first polar platealso serves as the gate electrode of the third transistor T, an area where the third scan signal lineoverlaps with the fourth active layerserves as the gate electrode of the fourth transistor T(double gate structure), an area where the third scan signal lineoverlaps with the fifth active layerserves as the gate electrode of the fifth transistor T(double gate structure), an area where the second scan signal lineoverlaps with the sixth active layerserves as the gate electrode of the sixth transistor T, an area where the first light emitting control lineoverlaps with the seventh active layerserves as the gate electrode of the seventh transistor T, and an area where the second light emitting control lineoverlaps with the eighth active layerserves as the gate electrode of the eighth transistor T.

1 2 4 5 6 7 8 3 In an exemplary embodiment, the first transistor T, the second transistor T, the fourth transistor T, the fifth transistor T, the sixth transistor T, the seventh transistor T, and the eighth transistor Tare all switching transistors, and the third transistor Tis a driving transistor.

27 13 In an exemplary embodiment, there is no overlapping area between an orthographic projection of the threshold capacitor first polar plateon the base substrate and the orthographic projection of the third active layeron the base substrate.

1 8 In an exemplary embodiment, after the pattern of the first conducting layer is formed, the semiconductor layer may be metalized by using the first conducting layer as a shield. A region of the semiconductor layer, which is shielded by the first conducting layer, forms the channel regions of the first transistor Tto the eighth transistor T, and a region of the semiconductor layer, which is not shielded by the first conducting layer, is metalized, that is, the first regions and the second regions of the first active layer to the eighth active layer are all metalized.

31 32 33 34 9 FIG. (3) A pattern of a second conducting layer is formed. In an exemplary embodiment, forming a pattern of a second conducting layer may include: depositing sequentially a third insulating thin film and a second metal thin film on the base substrate, on which the aforementioned patterns are formed, and patterning the second metal thin film through a patterning process to form a third insulating layer overlying the first conducting layer and a pattern of a second conducting layer arranged on the third insulating layer. The pattern of the second conducting layer at least includes: the initial signal line, the first connecting line, the storage capacitor second polar plateand the threshold capacitor second polar plate, as shown in.

31 32 31 23 25 32 22 24 32 31 32 In an exemplary embodiment, the initial signal lineand the first connecting lineextend along the first direction X, the initial signal lineis arranged at one side of the third scan signal lineaway from the second light emitting control line, the first connecting lineis arranged between the second scan signal lineand the first light emitting control line, and the first connecting lineis configured to be connected to a reference signal line formed subsequently, so that each sub-pixel in a sub-pixel row has the same reference voltage, thereby improving display uniformity. The initial signal lineand the first connecting linemay be arranged at equal intervals or at unequal intervals.

33 34 21 22 33 34 In an exemplary embodiment, the storage capacitor second polar plateand the threshold capacitor second polar plateare arranged between the first scan signal lineand the second scan signal line, and the storage capacitor second polar plateand the threshold capacitor second polar plateare spaced apart from each other.

33 33 26 33 33 1 33 1 33 33 1 33 33 1 26 26 33 1 33 1 33 1 26 26 In an exemplary embodiment, the outline of the storage capacitor second polar platemay be in the shape of a rectangle, corners of which may be provided with a chamfer. There is an overlapping area between an orthographic projection of the storage capacitor second polar plateon the base substrate and the orthographic projection of the storage capacitor first polar plateon the base substrate. The storage capacitor second polar plateis provided with a first opening-, the first opening-may be in the shape of a rectangle and is located in the middle of the storage capacitor second polar plate. The first opening-causes the storage capacitor second polar plateto form a ring structure. The first opening-exposes the third insulating layer overlying the storage capacitor first polar plate, and the orthographic projection of the storage capacitor first polar plateon the base substrate contains an orthographic projection of the first opening-on the base substrate. In an exemplary embodiment, the first opening-is configured to accommodate a first via hole formed subsequently. The first via hole is located in the first opening-and exposes the storage capacitor first polar plate, so that a first connecting electrode subsequently formed is connected to the storage capacitor first polar platethrough the first via hole.

34 27 34 27 34 34 1 34 1 34 34 1 34 34 1 27 27 34 1 34 1 34 1 27 27 In an exemplary embodiment, the shape of the threshold capacitor second polar plateis similar to that of the threshold capacitor first polar plate, which is the shape of a rectangle with two corners being provided with a groove. There is an overlapping area between an orthographic projection of the threshold capacitor second polar plateon the base substrate and an orthographic projection of the threshold capacitor first polar plateon the base substrate. The threshold capacitor second polar plateis provided with a second opening-, and the second opening-may be in the shape of a rectangle and is located in the middle of the threshold capacitor second polar plate. The second opening-causes the threshold capacitor second polar plateto form a ring structure. The second opening-exposes the third insulating layer overlying the threshold capacitor first polar plate, and the orthographic projection of the threshold capacitor first polar plateon the base substrate contains an orthographic projection of the second opening-on the base substrate. In an exemplary embodiment, the second opening-is configured to accommodate a second via hole formed subsequently. The second via hole is located in the second opening-and exposes the threshold capacitor first polar plate, so that a second connecting electrode subsequently formed is connected to the threshold capacitor first polar platethrough the second via hole.

26 33 26 3 33 In an exemplary embodiment, the storage capacitor first polar plateand the storage capacitor second polar plateconstitute the storage capacitor Cst of the pixel driving circuit, the storage capacitor first polar plateserves as the second end of the storage capacitor Cst and also serves as the gate electrode of the third transistor T, and the storage capacitor second polar plateserves as the first end of the storage capacitor Cst and is connected to a first power line VDD formed subsequently.

27 34 27 1 34 In an exemplary embodiment, the threshold capacitor first polar plateand the threshold capacitor second polar plateconstitute the threshold capacitor CVth of the pixel driving circuit, the threshold capacitor first polar plateserves as the first end of the threshold capacitor CVth and is connected to the second pole of the first transistor Tformed subsequently, and the threshold capacitor second polar plateserves as the second end of the threshold capacitor CVth and is connected to the second end of the storage capacitor Cst.

33 33 33 In an exemplary embodiment, the storage capacitor second polar platesof adjacent sub-pixels in one sub-pixel row are connected to each other by connecting lines. Since the storage capacitor second polar plateis connected to the first power line formed subsequently, the storage capacitor second polar platesconnected to each other in one sub-pixel row also serve as the first power connecting lines, so that all sub-pixels in one sub-pixel row have the same supply voltage, thereby improving display uniformity.

34 In an exemplary embodiment, the threshold capacitor second polar platesof adjacent sub-pixels in one sub-pixel row are spaced apart from each other, so that the threshold capacitor CVth of each sub-pixel only reflects the threshold voltage of the driving transistor of that sub-pixel.

35 36 37 38 In an exemplary embodiment, the first sub-polar plate, the second sub-polar plate, the third sub-polar plateand the fourth sub-polar platemay be provided in each sub-pixel.

35 35 31 35 14 4 35 4 4 The first sub-polar platemay be in the shape of “L”. One end of the first sub-polar plateis connected to the initial signal line, and there is an overlapping area between an orthographic projection of the other end of the first sub-polar plateon the base substrate and the orthographic projection of the fourth active layer, located between the gate electrodes of two fourth transistors T, on the base substrate. The first sub-polar plateis configured to introduce parasitic capacitance at the double-gate intermediate node of the fourth transistor Tto stabilize the potential of the critical node in the pixel driving circuit, and further improve flicker of the display substrate to adjust an off-state leakage current of the fourth transistor T.

36 36 15 5 36 5 5 The second sub-polar platemay be in the shape of “1”. There is an overlapping area between the orthographic projection of the second sub-polar plateon the base substrate and the orthographic projection of the fifth active layer, located between the gate electrodes of two fifth transistors T, on the base substrate. The second sub-polar plateis configured to introduce parasitic capacitance at the double-gate intermediate node of the fifth transistor Tto adjust an off-state leakage current of the fifth transistor T, stabilize the potential of the critical node in the pixel driving circuit, and further improve flicker of the display substrate.

37 37 11 1 37 1 1 The third sub-polar platemay be in the shape of “-”. There is an overlapping area between the orthographic projection of the third sub-polar plateon the base substrate and the orthographic projection of the first active layer, located between the gate electrodes of two first transistors T, on the base substrate. The third sub-polar plateis configured to introduce parasitic capacitance at the double-gate intermediate node of the first transistor Tto adjust an off-state leakage current of the first transistor T, stabilize the potential of the critical node in the pixel driving circuit, and further improve flicker of the display substrate.

38 38 12 2 38 2 2 The fourth sub-polar platemay be in the shape of “-”. There is an overlapping area between the orthographic projection of the fourth sub-polar plateon the base substrate and the orthographic projection of the second active layer, located between the gate electrodes of two second transistors T, on the base substrate. The fourth sub-polar plateis configured to introduce parasitic capacitance at the double-gate intermediate node of the second transistor Tto adjust an off-state leakage current of the second transistor T, stabilize the potential of the critical node in the pixel driving circuit, and further improve flicker of the display substrate.

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 10 FIG. (4) A pattern of a fourth insulating layer is formed. In an exemplary embodiment, forming a pattern of a fourth insulation layer may include: depositing a fourth insulating thin film on the base substrate, on which the aforementioned patterns are formed, and patterning the fourth insulating thin film through a patterning process to form a fourth insulating layer overlying the second conducting layer. The fourth insulating layer is provided with a plurality of via holes which at least include: a first via hole V, a second via hole V, a third via hole V, a fourth via hole V, a fifth via hole V, a sixth via hole V, a seventh via hole V, an eighth via hole V, a ninth via hole V, a tenth via hole V, an eleventh via hole V, a twelfth via hole V, a thirteenth via hole V, a fourteenth via hole V, a fifteenth via hole V, a sixteenth via hole V, a seventeenth via hole V, an eighteenth via hole V, a nineteenth via hole V, a twentieth via hole Vand a twenty-first via hole V, as shown in.

1 33 1 33 1 33 1 1 26 1 26 In an exemplary embodiment, the first via hole Vis located in an area where the first opening-provided in the storage capacitor second polar plateis located, an orthographic projection of the first via hole Von the base substrate is located within the range of the orthographic projection of the first opening-on the base substrate, the fourth insulating layer and the third insulating layer in the first via hole Vare etched away to expose a surface of the storage capacitor first polar plate, and the first via hole Vis configured in such a way that the subsequently formed first connecting electrode is connected to the storage capacitor first polar platethrough this via hole.

2 34 1 34 2 27 2 27 In an exemplary embodiment, the second via hole Vis located in an area where the second opening-provided in the threshold capacitor second polar plateis located, the fourth insulating layer and the third insulating layer in the second via hole Vare etched away to expose a surface of the threshold capacitor first polar plate, and the second via hole Vis configured in such a way that the subsequently formed second connecting electrode is connected to the threshold capacitor first polar platethrough this via hole.

3 37 3 37 3 37 37 In an exemplary embodiment, the third via hole Vis located in an area where the third sub-polar plateis located, the fourth insulating layer in the third via hole Vis etched away to expose a surface of the third sub-polar plate, and the third via hole Vis configured in such a way that the subsequently formed first power line is connected to the third sub-polar platethrough this via hole, to provide a constant supply voltage for the third sub-polar plate.

4 3 4 In an exemplary embodiment, the fourth via hole Vis located in an area where the first region of the first active layer is located, the fourth insulating layer, the third insulating layer and the second insulating layer in the fourth via hole Vare etched away to expose a surface of the first region of the first active layer, and the fourth via hole Vis configured in such a way that the subsequently formed third connecting electrode is connected to the first active layer through this via hole.

5 5 5 In an exemplary embodiment, the fifth via hole Vis located in an area where the second region of the first active layer is located, the fourth insulating layer, the third insulating layer and the second insulating layer in the fifth via hole Vare etched away to expose a surface of the second region of the first active layer, and the fifth via hole Vis configured in such a way that the subsequently formed fourth connecting electrode is connected to the first active layer through this via hole.

6 36 6 36 6 36 36 In an exemplary embodiment, the sixth via hole Vis located in an area where the second sub-polar plateis located, the fourth insulating layer in the sixth via hole Vis etched away to expose a surface of the second sub-polar plate, and the sixth via hole Vis configured in such a way that the subsequently formed first power line is connected to the second sub-polar platethrough this via hole, to provide a constant supply voltage for the second sub-polar plate.

7 7 7 In an exemplary embodiment, the seventh via hole Vis located in an area where the first region of the fifth active layer is located, the fourth insulating layer, the third insulating layer and the second insulating layer in the seventh via hole Vare etched away to expose a surface of the first region of the fifth active layer, and the seventh via hole Vis configured in such a way that the subsequently formed reference signal line is connected to the fifth active layer through this via hole.

8 8 8 In an exemplary embodiment, the eighth via hole Vis located in an area where the second region of the fifth active layer is located, the fourth insulating layer, the third insulating layer and the second insulating layer in the eighth via hole Vare etched away to expose a surface of the second region of the fifth active layer, and the eighth via hole Vis configured in such a way that the subsequently formed fourth connecting electrode is connected to the fifth active layer through this via hole.

9 9 9 In an exemplary embodiment, the ninth via hole Vis located in an area where the first region of the fourth active layer (which is also the first region of the sixth active layer) is located, the fourth insulating layer, the third insulating layer and the second insulating layer in the ninth via hole Vare etched away to expose a surface of the first region of the fourth active layer, and the ninth via hole Vis configured in such a way that the subsequently formed fifth connecting electrode is connected to the fourth active layer through this via hole.

10 10 10 In an exemplary embodiment, the tenth via hole Vis located in an area where the second region of the fourth active layer (which is also the first region of the eighth active layer) is located, the fourth insulating layer, the third insulating layer and the second insulating layer in the tenth via hole Vare etched away to expose a surface of the second region of the fourth active layer, and the tenth via hole Vis configured in such a way that the subsequently formed sixth connecting electrode is connected to the fourth active layer through this via hole.

11 11 11 In an exemplary embodiment, the eleventh via hole Vis located in an area where the second region of the eighth active layer is located, the fourth insulating layer, the third insulating layer and the second insulating layer in the eleventh via hole Vare etched away to expose a surface of the second region of the eighth active layer, and the eleventh via hole Vis configured in such a way that the subsequently formed second connecting electrode is connected to the eighth active layer through this via hole.

12 12 12 In an exemplary embodiment, the twelfth via hole Vis located in an area where the first region of the third active layer is located, the fourth insulating layer, the third insulating layer and the second insulating layer in the twelfth via hole Vare etched away to expose a surface of the first region of the third active layer, and the twelfth via hole Vis configured in such a way that the subsequently formed first power line is connected to the third active layer through this via hole.

13 13 13 In an exemplary embodiment, the thirteenth via hole Vis located in an area where the second region of the third active layer is located, the fourth insulating layer, the third insulating layer and the second insulating layer in the thirteenth via hole Vare etched away to expose a surface of the second region of the third active layer, and the thirteenth via hole Vis configured in such a way that the subsequently formed seventh connecting electrode is connected to the third active layer through this via hole.

14 14 14 In an exemplary embodiment, the fourteenth via hole Vis located in an area where the first region of the second active layer is located, the fourth insulating layer, the third insulating layer and the second insulating layer in the fourteenth via hole Vare etched away to expose a surface of the first region of the second active layer, and the fourteenth via hole Vis configured in such a way that the subsequently formed first connecting electrode is connected to the second active layer through this via hole.

15 15 15 In an exemplary embodiment, the fifteenth via hole Vis located in an area where the second region of the second active layer (which is also the first region of the seventh active layer) is located, the fourth insulating layer, the third insulating layer and the second insulating layer in the fifteenth via hole Vare etched away to expose a surface of the second region of the second active layer, and the fifteenth via hole Vis configured in such a way that the subsequently formed seventh connecting electrode is connected to the second active layer through this via hole.

16 38 16 38 16 38 38 In an exemplary embodiment, the sixteenth via hole Vis located in an area where the fourth sub-polar plateis located, the fourth insulating layer in the sixteenth via hole Vis etched away to expose a surface of the fourth sub-polar plate, and the sixteenth via hole Vis configured in such a way that the subsequently formed first power line is connected to the fourth sub-polar platethrough this via hole, to provide a constant supply voltage for the fourth sub-polar plate.

17 32 17 17 32 In an exemplary embodiment, the seventeenth via hole Vis located in an area where the first connecting lineis located, the fourth insulating layer in the seventeenth via hole Vis etched away to expose a surface of the first connecting line, and the seventeenth via hole Vis configured in such a way that the subsequently formed reference signal line is connected to the first connecting linethrough this via hole.

18 31 18 31 18 45 31 In an exemplary embodiment, the eighteenth via hole Vis located in an area where the initial signal lineis located, the fourth insulating layer in the eighteenth via hole Vis etched away to expose a surface of the initial signal line, and the eighteenth via hole Vis configured in such a way that the subsequently formed fifth connecting electrodeis connected to the initial signal linethrough this via hole.

19 33 19 33 19 33 19 19 19 33 In an exemplary embodiment, the nineteenth via hole Vis located in an area where the storage capacitor second polar plateis located, the fourth insulating layer in the nineteenth via hole Vis etched away to expose a surface of the storage capacitor second polar plate, and the nineteenth via hole Vis configured in such a way that the subsequently formed first power line is connected to the storage capacitor second polar platethrough this via hole. In an exemplary embodiment, there may be one or more nineteenth via holes V, and a plurality of nineteenth via holes Vare arranged sequentially along the second direction Y. The plurality of nineteenth via holes Vmay improve the reliability of the connection of the first power line with the storage capacitor second polar plate.

20 28 2 28 20 28 2 28 20 28 2 28 In an exemplary embodiment, the twentieth via hole Vis located in an area where the second electrode segment-of the first electrodeis located, the fourth insulating layer and the third insulating layer in the twentieth via hole Vare etched away to expose a surface of the second electrode segment-of the first electrode, and the twentieth via hole Vis configured in such a way that the subsequently formed interlayer connecting electrode is connected to the second electrode segment-of the first electrodethrough this via hole.

21 21 21 In an exemplary embodiment, the twenty-first via hole Vis located in an area where the second region of the sixth active layer (which is also the second region of the seventh active layer) is located, the fourth insulating layer, the third insulating layer and the second insulating layer in the twenty-first via hole Vare etched away to expose a surface of the second region of the sixth active layer, and the twenty-first via hole Vis configured in such a way that the subsequently formed ninth connecting electrode is connected to the second active layer through this via hole.

41 42 43 44 45 46 47 48 49 71 72 11 FIG. (5) A pattern of a third conducting layer is formed. In an exemplary embodiment, forming a pattern of a third conducting layer may include: depositing a third metal thin film on the base substrate, on which the aforementioned patterns are formed, and patterning the third metal thin film through a patterning process to form a third conducting layer arranged on the fourth insulating layer. The third conducting layer at least includes: a first connecting electrode, a second connecting electrode, a third connecting electrode, a fourth connecting electrode, a fifth connecting electrode, a sixth connecting electrode, a seventh connecting electrode, an eighth connecting electrode, an interlayer connecting electrode, the first power lineand the reference signal line, as shown in.

71 72 71 72 In an exemplary embodiment, the first power lineand the reference signal lineextend along the second direction Y. The first power lineand the reference signal linemay be arranged at equal intervals or at unequal intervals, and may be straight lines or fold lines.

71 37 3 36 6 12 38 16 33 19 In an exemplary embodiment, the first power lineis connected to the third sub-polar platethrough the third via hole V, is connected to the second sub-polar platethrough the sixth via hole V, is connected to the first region of the third active layer through the twelfth via hole V, is connected to the fourth sub-polar platethrough the sixteenth via hole V, and is connected to the storage capacitor second polar platethrough the nineteenth via hole V.

72 7 32 17 In an exemplary embodiment, the reference signal lineis connected to the first region of the fifth active layer through the seventh via hole Vand is connected to the first connecting linethrough the seventeenth via hole V.

41 26 1 14 2 26 26 3 41 2 2 3 In the exemplary embodiment, the first connecting electrodeis in the shape of a strip extending along the second direction Y, with one end connected to the storage capacitor first polar platethrough the first via hole Vand the other end connected to the first region of the second active layer through the fourteenth via hole V, so that the first pole of the second transistor Tis connected to the storage capacitor first polar plate. Since the storage capacitor first polar platealso serves as the gate electrode of the third transistor T, the first connecting electrodeserves as the first pole of the second transistor T, so that the first pole of the second transistor T, the gate electrode of the third transistor Tand the second end of the storage capacitor Cst have the same potential.

42 27 2 11 8 27 27 26 42 8 2 3 8 1 In the exemplary embodiment, the second connecting electrodeis in the shape of a strip extending along the second direction Y, with one end connected to the threshold capacitor first polar platethrough the second via hole Vand the other end connected to the second region of the eighth active layer through the eleventh via hole V, so that the second pole of the eighth transistor Tis connected to the threshold capacitor first polar plate. Since the threshold capacitor first polar plateand the storage capacitor first polar plateare connected to each other to form an integrated structure, the second connecting electrodeserves as the second pole of the eighth transistor T, so that the first pole of the second transistor T, the gate electrode of the third transistor T, the second pole of the eighth transistor T, the second end of the storage capacitor Cst and the second end of the threshold capacitor CVth have the same potential (i.e. the first node N).

43 71 72 4 43 1 In an exemplary embodiment, the third connecting electrodeis arranged between the first power lineand the reference signal line, and is connected to the first region of the first active layer through the fourth via hole V. The third connecting electrodeserves as the first pole of the first transistor T, and is configured to be connected to the subsequently formed data signal line.

44 5 8 44 1 5 1 5 2 In an exemplary embodiment, the fourth connecting electrodeis in the shape of a strip extending along the second direction Y, with one end connected to the second region of the first active layer through the fifth via hole Vand the other end connected to the second region of the fifth active layer through the eighth via hole V. The fourth connecting electrodealso serves as the second pole of the first transistor Tand the second pole of the fifth transistor T, so that the second pole of the first transistor Tand the second pole of the fifth transistor Thave the same potential (i.e., the second node N).

45 9 31 18 45 4 6 4 6 31 In an exemplary embodiment, the fifth connecting electrodeis in the shape of a strip extending along the second direction Y, with one end connected to the first region of the fourth active layer (which is also the first region of the sixth active layer) through the ninth via hole Vand the other end connected to the initial signal linethrough the eighteenth via hole V. The fifth connecting electrodealso serves as the first pole of the fourth transistor Tand the first pole of the sixth transistor T, so that both the first pole of the fourth transistor Tand the sixth transistor Tare connected to the initial signal line.

46 10 46 4 8 4 8 In an exemplary embodiment, the sixth connecting electrodeis in the shape of a rectangle and is connected to the second region of the fourth active layer (which is also the first region of the eighth active layer) through the tenth via hole V. The sixth connecting electrodealso serves as the second pole of the fourth transistor Tand the first pole of the eighth transistor T, so that the connection of the second pole of the fourth transistor Twith the first pole of the eighth transistor Tis implemented.

47 13 15 47 2 3 7 2 3 7 3 In an exemplary embodiment, the seventh connecting electrodeis in the shape of a strip extending along the second direction Y, with one end connected to the second region of the third active layer through the thirteenth via hole Vand the other end connected to the second region of the second active layer (which is also the first region of the seventh active layer) through the fifteenth via hole V. The seventh connecting electrodealso serves as the second pole of the second transistor T, the second pole of the third transistor Tand the first pole of the seventh transistor T, so that the second pole of the second transistor T, the second pole of the third transistor Tand the first pole of the seventh transistor Thave the same potential (i.e., the third node N).

48 21 48 6 7 6 7 In an exemplary embodiment, the eighth connecting electrodeis in the shape of a rectangle, and is connected to the second region of the sixth active layer (which is also the second region of the seventh active layer) through the twenty-first via hole V. The eighth connecting electrodealso serves as the second pole of the sixth transistor Tand the second pole of the seventh transistor T, so that the connection of the second pole of the sixth transistor Twith the second pole of the seventh transistor Tis implemented.

49 72 42 28 20 In an exemplary embodiment, the interlayer connecting electrodeis arranged between the reference signal lineand the second connecting electrode, is connected to the first electrodethrough the twentieth via hole V, and is configured to be connected to the subsequently formed second power line.

31 32 33 12 FIG. (6) A pattern of a fifth insulating layer is formed. In an exemplary embodiment, forming a pattern of a fifth insulating layer may include: coating a fifth insulating thin film on the base substrate, on which the aforementioned patterns are formed, and patterning the fifth insulating thin film through a patterning process to form a fifth insulating layer overlying the third conducting layer. The fifth insulating layer is provided with a plurality of via holes, which at least include: a thirty-first via hole V, a thirty-second via hole Vand a thirty-third via hole V, as shown in.

31 43 31 43 31 43 In an exemplary embodiment, the thirty-first via hole Vis located in an area where the third connecting electrodeis located, the fifth insulating layer in the thirty-first via hole Vis removed to expose a surface of the third connecting electrode, and the thirty-first via hole Vis configured in such a way that the subsequently formed data signal line is connected to the third connecting electrodethrough this via hole.

32 48 32 48 32 48 In an exemplary embodiment, the thirty-second via hole Vis located in an area where the eighth connecting electrodeis located, the fifth insulating layer in the thirty-second via hole Vis removed to expose a surface of the eighth connecting electrode, and the thirty-second via hole Vis configured in such a way that the subsequently formed anode connecting electrode is connected to the eighth connecting electrodethrough this via hole.

33 49 33 49 33 49 In an exemplary embodiment, the thirty-third via hole Vis located in an area where the interlayer connecting electrodeis located, the fifth insulating layer in the thirty-third via hole Vis removed to expose a surface of the interlayer connecting electrode, and the thirty-third via hole Vis configured in such a way that a subsequently formed second electrode line is connected to the interlayer connecting electrodethrough this via hole.

51 73 74 13 FIG. (7) A pattern of a fourth conducting layer is formed. In an exemplary embodiment, forming a pattern of a fourth conducting layer may include: depositing a fourth metal thin film on the base substrate, on which the aforementioned patterns are formed, and patterning the fourth metal thin film through a patterning process to form a fourth conducting layer arranged on the fifth insulating layer. The fourth conducting layer at least includes the anode connecting electrode, the second power lineand the data signal line, as shown in.

51 23 31 48 32 51 48 6 7 In an exemplary embodiment, the anode connecting electrodeis arranged between the third scan signal lineand the initial signal line, is in the shape of a rectangle and is connected to the eighth connecting electrodethrough the thirty-second via hole V. The anode connecting electrodeis configured to be connected to the anode of the light emitting device subsequently formed. Since the eighth connecting electrodealso serves as the second pole of the sixth transistor Tand the second pole of the seventh transistor T, the connection of the anode of the light emitting device with the pixel driving circuit is implemented, such that the pixel driving circuit can drive the light emitting device to emit light.

74 71 72 74 43 31 43 1 74 1 74 28 In an exemplary embodiment, the data signal lineextends along the second direction Y and is arranged between the first power lineand the reference signal line. The data signal lineis connected to the third connecting electrodethrough the thirty-first via hole V. Since the third connecting electrodeserves as the first pole of the first transistor T, the connection of the data signal linewith the first pole of the first transistor Tis implemented. There is an overlapping area between an orthographic projection of the data signal lineon the base substrate and the orthographic projection of the first electrodeon the base substrate.

73 71 75 73 75 75 73 75 49 33 49 28 73 28 73 28 28 In an exemplary embodiment, the second power lineextends along the second direction Y, and its position corresponds to the position of the first power line. A plurality of second power connecting linesare arranged on the second power line. Each second power connecting lineis provided in one sub-pixel. One end of the second power connecting lineis connected to the second power line, and the other end of the second power connecting lineextends along the opposite direction of the first direction X and is connected to the interlayer connecting electrodethrough the thirty-third via hole V. Since the interlayer connecting electrodeis connected to the first electrode, the connection of the second power linewith the first electrodeis implemented. The second power linemay provide constant low-level signals for the first electrode, so that the first electrodemay avoid the influence of jumps of the data voltage on the critical node effectively, thereby preventing the jumps of the data voltage from affecting the potential of the critical node of the pixel driving circuit and improving the display effect.

73 74 In an exemplary embodiment, the second power lineand the data signal linemay be arranged at equal intervals or at unequal intervals, and may be straight lines or fold lines.

In an exemplary embodiment, the subsequent manufacturing process may include: forming a planarization layer overlying the pattern of the fourth conducting layer; forming an anode of the light emitting device on the planarization layer; forming a pixel definition layer overlying the anode, the pixel definition layer of each sub-pixel being provided with a pixel opening exposing the anode; then forming an organic light emitting layer by an evaporation process, and forming a cathode on the organic light emitting layer; and finally forming an encapsulation layer. The encapsulation layer may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer that are stacked. The first encapsulation layer and the third encapsulation layer may be made of an inorganic material, and the second encapsulation layer may be made of an organic material. The second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer, which may ensure that external water vapor cannot enter the light emitting device.

In an exemplary implementation, the base substrate may be a flexible base substrate or a rigid base substrate. The rigid base substrate may be made of, but is not limited to, one or more of glass and quartz. The flexible base substrate may be made of, but is not limited to, one or more of polyethylene terephthalate, ethylene terephthalate, polyether ether ketone, polystyrene, polycarbonate, polyarylate, polyarylester, polyimide, polyvinyl chloride, polyethylene, and textile fibers. In an exemplary implementation, the flexible base substrate may include a first flexible material layer, a first inorganic material layer, a second flexible material layer and a second inorganic material layer which are stacked. Materials of the first and second flexible material layers may be polyimide (PI), polyethylene terephthalate (PET), surface treated polymer soft films, or the like; and materials of the first and second inorganic material layers may be silicon nitride (SiNx), silicon oxide (SiOx), or the like, for improving the water and oxygen resistance of the base substrate. In an exemplary implementation, the thickness of the first flexible material layer may be about 5 μm to 15 μm, for example, 10 μm; the thickness of the second flexible material layer may be about 5 μm to 15 μm, for example, 10 μm; the thickness of the first inorganic material layer may be about 0.3 μm to 0.9 μm, for example, 0.6 μm; and the thickness of the second inorganic material layer may be about 0.3 μm to 0.9 μm, for example, 0.6 μm.

1 2 1 2 In an exemplary embodiment, the first conducting layer, the second conducting layer, the third conducting layer and the fourth conducting layer may be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloy materials of the above metals, such as an aluminum neodymium alloy (AlNd) or a molybdenum niobium alloy (MoNb), and may be a single-layer structure or a multi-layer composite structure, such as Mo/Cu/Mo, etc. The first conducting layer is referred to as a first gate metal (Gate) layer, the second conducting layer is referred to as a second gate metal (Gate) layer, the third conducting layer is referred to as a first source-drain metal (SD) layer, and the fourth conducting layer is referred to as a second source-drain metal (SD) layer. The first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer and the fifth insulating layer may be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and may be a single layer, multiple layers, or a composite layer. The first insulating layer is referred to as a buffer layer for improving the water and oxygen resistance of the base substrate, the second and the third insulating layers are referred to as gate insulating (GI) layers, the fourth insulating layer is referred to as an interlayer insulating (ILD) layer, and the fifth insulating layer is referred to as a passivation (PVX) layer. The semiconductor layer may be made of a material, such as an amorphous indium gallium zinc oxide material (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), sexithiophene and polythiophene, that is, the present disclosure is applicable to transistors manufactured based on oxide technology, silicon technology and organic technology.

In an exemplary embodiment, the thickness of the first insulating layer is 3000 angstroms to 5000 angstroms, the thickness of the second insulating layer is 1000 angstroms to 2000 angstroms, the thickness of the third insulating layer is 4500 angstroms to 7000 angstroms, the thickness of the fourth insulating layer is 3000 angstroms to 5000 angstroms, and the thickness of the fifth insulating layer is 3000 angstroms to 5000 angstroms.

4 FIG. 6 FIG. 7 13 FIGS.to 2 1 1 3 1 1 3 1 1 High-resolution (PPI) display has finer picture quality and display quality, and has become a design trend. Since the pixel area of high-resolution display is relatively small, various interference factors, especially the influence of the data signal line on the critical node in the pixel driving circuit, need to be considered for arranging the pixel driving circuit in a limited space. In the pixel driving circuit shown in, the data voltage Vdt provided by the data signal line is written into the second node Nthrough the first transistor T, and is coupled to the first node Nthrough the threshold capacitor CVth, thereby controlling a potential of the gate electrode of the third transistor T(driving transistor) to implement display under different data voltages Vdt. As shown inand in conjunction with, the data signal lines of three sub-pixels in a sub-pixel row will form parasitic capacitance together with the first node N(the storage capacitor first polar plate and the threshold capacitor first polar plate) of the present sub-pixel or an adjacent sub-pixel. Since the data voltage Vdt is written row by row at different time and the data signal for each sub-pixel column is refreshed row by row, for the pixel driving circuit in the nth sub-pixel column, jumps of the data voltage Vdt in the n−1th sub-pixel column or the n+1th sub-pixel column will affect the potential of the first node Nof the pixel driving circuit in the nth sub-pixel column through parasitic effects, thereby affecting a driving current flowing through the third transistor T. In order to reduce the influence of jumps of the data voltage on the potential of the first node N, a solution of increasing a distance between the data signal line and the first node Nis used for a display substrate, but this solution is conducive to neither the layout nor improvement of resolution.

1 1 1 3 In an exemplary embodiment of the present disclosure, a first electrode is provided, the first electrode is arranged in the first conducting layer, there is an overlapping area between the orthographic projection of the first electrode on the base substrate and the orthographic projection of the data signal line on the base substrate, and the first electrode is connected to the second power line, which reduces the parasitic capacitance formed by the data signal line and the first node Nof the present sub-pixel or an adjacent sub-pixel, effectively avoids the influence of jumps of the data voltage Vdt on the first node N, and prevents the jumps of the data voltage Vdt from affecting the potential of the first node Nof the pixel driving circuit, thereby avoiding the influence on the driving current flowing through the third transistor T, and improving the display effect.

1 In an exemplary embodiment, the storage capacitor first polar plate, the threshold capacitor first polar plate (the first node N) and the first electrode are all arranged in the first conducting layer, and the data signal line is arranged in the fourth conducting layer. Since the second conducting layer is arranged between the first conducting layer and the fourth conducting layer, the storage capacitor second polar plate and the threshold capacitor second polar plate in the second conducting layer may shield an electric field between the surface of one side of the storage capacitor first polar plate and the threshold capacitor first polar plate facing the fourth conducting layer and the data signal line. Since the first electrode is provided on the first conducting layer, and there is an overlapping area between the orthographic projection of the first electrode on the base substrate and the orthographic projection of the data signal line on the base substrate, the first electrode may shield an electric field between the surface of one side of the storage capacitor first polar plate and the threshold capacitor first polar plate away from the fourth conducting layer and the data signal line.

1 1 1 As can be seen from the structure and manufacturing process of the display substrate described above, in the display substrate in accordance with an exemplary embodiment of the present disclosure, by arranging the first electrode on the first conducting layer, the first electrode reduces the parasitic capacitance formed by the data signal line and the first node Nof the present sub-pixel or an adjacent sub-pixel and effectively avoids the influence of jumps of the data voltage Vdt on the first node N, thereby improving the display effect. Although there is parasitic capacitance between the first electrode and the data signal line, the parasitic capacitance substantially has no influence on the performance of the pixel driving circuit because the first electrode is connected to the second power line. Since the first electrode provided in an exemplary embodiment of the present disclosure shields the influence of the jumps of the data voltage Vdt on the first nodes N, the distance between the data signal line and the storage capacitor and threshold capacitor may be reduced effectively, which not only is conducive to the layout, but also can reduce the pixel area and is therefore conducive to improving the resolution of the display substrate. The manufacturing process of the display substrate in accordance with an exemplary embodiment of the present disclosure may be compatible well with an existing manufacturing process, with simple process implementation, is easy to carry out, and has high production efficiency, a low production cost and a high yield.

The structure and the manufacturing process thereof shown in the present disclosure are illustrated exemplarily only. In an exemplary implementation, the first electrode may be arranged in the second conducting layer or the third conducting layer. For example, the first electrode may be arranged in the second conducting layer, and may be arranged in the same layer as the storage capacitor second polar plate and the threshold capacitor second polar plate, the first electrode, and the storage capacitor second polar plate and the threshold capacitor second polar plate may be formed simultaneously through a single patterning process, and the shape of the first electrode may be the same as the shape described in the aforementioned exemplary embodiments. Since the storage capacitor first polar plate and the threshold capacitor first polar plate are arranged in the first conducting layer and the data signal line is arranged in the fourth conducting layer, the first electrode is arranged between the threshold capacitor first polar plate and the data signal line, and the first electrode may not only shield the electric field between the surface of one side of the threshold capacitor first polar plate facing the fourth conducting layer and the data signal line, but also shield the electric field between the surface of one side of the threshold capacitor first polar plate away from the fourth conducting layer and the data signal line. As another example, the first electrode may be arranged in the third conducting layer, and may be arranged in the same layer as the first power line and the reference signal line, the first electrode, and the first power line and the reference signal line may be formed simultaneously through a single patterning process, and the shape of the first electrode may be the same as the shape of the second electrode segment in the aforementioned exemplary embodiments. Since the storage capacitor first polar plate and the threshold capacitor first polar plate are arranged in the first conducting layer and the data signal line is arranged in the fourth conducting layer, the first electrode is arranged between the threshold capacitor first polar plate and the data signal line, and the first electrode may not only shield the electric field between the surface of one side of the threshold capacitor first polar plate facing the fourth conducting layer and the data signal line, but also shield the electric field between the surface of one side of the threshold capacitor first polar plate away from the fourth conducting layer and the data signal line. For the case that the first electrode is arranged in the second conducting layer or the third conducting layer, the structure of the connecting electrode in the corresponding conducting layer may be altered according to actual needs, which is not limited herein in the present disclosure.

In an exemplary implementation, the display substrate of the present disclosure may be applied to a display apparatus with a pixel driving circuit, such as an OLED, a quantum dot display (QLED), a light emitting diode display (Micro LED or Mini LED) or a quantum dot light emitting diode display (QDLED), which is not limited herein in the present disclosure.

forming a semiconductor layer and a plurality of conducting layers, which are arranged at one side of the semiconductor layer away from the base substrate, on the base substrate, wherein a first electrode is arranged in at least one conducting layer, the first electrode is connected to the second power line, and there is an overlapping area between an orthographic projection of the first electrode on the base substrate and an orthographic projection of the data signal line on the base substrate. An exemplary embodiment of the present disclosure provides a method for manufacturing a display substrate, so as to manufacture the display substrate in accordance with the exemplary embodiment described above. In an exemplary embodiment, the display substrate includes a base substrate, a second power line, a data signal line and a plurality of sub-pixels, wherein at least one sub-pixel includes a pixel driving circuit and a light emitting device connected to the pixel driving circuit, the pixel driving circuit is connected respectively to the data signal line and the light emitting device is connected to the second power line; and the method includes:

forming a semiconductor layer on the base substrate; and forming sequentially a first conducting layer, a second conducting layer, a third conducting layer and a fourth conducting layer on the semiconductor layer, wherein the first electrode is arranged in the first conducting layer, the second conducting layer or the third conducting layer, the second power line and the data signal line are arranged in the fourth conducting layer, and the second power line is connected to the first electrode through a via hole. In an exemplary embodiment, the forming a semiconductor layer and a plurality of conducting layers, which are arranged at one side of the semiconductor layer away from the base substrate, on the base substrate may include:

The manufacturing process in the method for manufacturing the display substrate of an exemplary embodiment of the present disclosure is described in detail in the foregoing exemplary embodiments, and will not be repeated herein.

The present disclosure further provides a display apparatus which includes the aforementioned display substrate. The display apparatus may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, or a navigator, and the embodiments of the present invention are not limited thereto.

Although the implementations disclosed in the present disclosure are described as above, the described contents are only implementations which are used in order to facilitate understanding of the present disclosure, and are not intended to limit the present invention. Any skilled person in the art to which the present disclosure pertains may make any modifications and alterations in forms and details of implementation without departing from the spirit and scope of the present disclosure. However, the patent protection scope of the present invention should be subject to the scope defined by the appended claims.