Chunky Partial Load to Store Forwarding for Pipeline Loads

Modern CPUs support Load to Store forwarding to improve latency of loads which are dependent on stores. When the load requires data that is only partially covered by a store, or spread across multiple stores, then partial store forwarding is employed, enabling the load to be serviced from bytes gathered from several distinct locations in the machine (e.g. Store Buffer, Fill Buffer, Cache).

Various algorithms have been employed to implement partial forwarding, with different performance characteristics. Typical partial forwarding solutions implement greedy algorithms which attempt to gather the bytes required to service a load in as few passes as possible. While this reduces the power required to service the load, it increases computational complexity, and creates a dependency between passes. The machine waits for the completion of the current pass to know the bytes which are to be fetched in the subsequent pass. As pipeline depths increase, this creates a substantial latency penalty, because sequential accesses cannot be pipelined. For a pipeline depth T, requiring N passes, each supplying a variable number of bytes, the best case latency is N*T. For a 16-byte load, N will range from 2 to 16.

The present disclosure relates to methods, apparatus and systems for chunky partial load to store forwarding for pipelined loads. According to some examples, the technique described in the disclosure pertaining to chunky partial load to store forwarding simplifies the process of servicing loads through partial forwarding by breaking the load into uniform chunks, each of which is serviced by the machine as a separate load. These loads are scheduled into the memory unit load pipeline in adjacent cycles. This technique eliminates the dependency between passes, and, in some examples, improves the best-case latency to T+N−1, instead of N*T.

Furthermore, the Chunky Partial Forwarding (CPF) algorithm provides predictable latency for partial load to store forwarding, which scales more readily with pipeline depth, and number of passes required to service the load. This provides significant performance benefits for Central Processing Units (CPUs) with large Level 1 (L1) caches, and large store buffers.

CPF is a partial forwarding algorithm, together with a chunky partial load logic, that identifies and schedules loads for partial forwarding by decomposing the loads into chunks of uniform size, and issuing each chunk as a unique load. The results of each chunk load are stored in a register at the end of the pipeline, and the original load is completed if all chunks complete successfully. The technique scales well with pipeline depth and provides a low hardware cost for implementation.

CPF implementation requires three modifications to a typical load pipeline. First, loads are to be identified and marked as candidates for CPF, and the chunk size selected. Second, scheduling of the load pipeline is to account for CPF support, by allocating a register and logic (e.g., controller) to track the scheduling of chunks into the load pipe. Finally, the chunked loads are collected at the end of the pipeline, where completion of each chunk is tracked to determine the overall success or failure of the original load.

1 FIG. 1 FIG. 1 FIG. 100 101 101 102 101 100 103 illustrates an example of a load dispatch that has a partial overlap with a store according to some examples of the disclosure. As shown in diagram, a loadhas an N-byte range of 0x10-0x13, while a store has an N-byte range of 0x13-0x16. Load identification for CPF is managed through existing store forwarding checks. When a load checks a store buffer, the loads byte range is compared to that of the store identified as a forwarding candidate. If the overlap is incomplete, the load will be marked for CPF. In, the loadis incomplete due to the overlap with the store, as noted for byte range 0x13. Hence, the loadis a candidate for CPF. A chunk size for CPF is selected based on the alignment of the load, store and their overlap. For the diagram, if the overlap 0x13 is 4-byte aligned, then a 4-byte size chunkcan be selected. Other examples can implement other chunk sizes based on byte size, alignment and size of overlap. In some examples where a certain byte size cannot be achieved or the bytes are not aligned between the load and store, 1-byte chunks can be used. In, each chunk size is 4-bytes.

2 FIG. 2 FIG. 200 201 101 202 203 210 201 201 101 201 204 204 201 201 illustrates a portion of a processorfor implementing the CPF for a load pipeline according to some examples of the disclosure.shows a load pipefor executing the load. A chunky partial load logicworks in conjunction with a chunky partial load registerto process load chunks, when a partial overlap of load to store is detectedin the pipeline. Because pipelineprocesses the load, it is also referred to as load pipe. Also present is an Incomplete Load Buffer (ICLB). The ICLBholds loads that have been executed (e.g., by a corresponding address generation unit), but have not yet completed (e.g., have not retired). Note that the load pipeat the right side of the drawing is the same load pipeat the left side of the drawing. The duplication is for the purpose of explanation. However, some examples may use a separate pipeline.

101 201 201 202 203 In operation, the loadenters the load pipeat the top and when completed successfully, performs a writeback at the bottom of the load pipe. CPF loads arbitrate for the load pipe in the same manner as a non-CPF loads. Once a partial overlap is detected, the chunky partial load logicallocates the chunky partial load register (hereinafter noted as CPR) to hold the inputs to the first pipe stage, and provides a counter and supporting logic to track chunks (e.g., 4-byte chunks) to compute the base address of each chunk.

204 A load may be marked for chunky mode when it completes a pass down the load pipe, and would have completed, except that it failed the data overlap check. When this occurs, the load operation sets the chunky bit in the ICLB. When the load eventually schedules, it will proceed in chunky mode.

Load Linear Address [1:0]=2′b00 (The load is 4-byte aligned.) Load Linear Address End [1:0]=2′b11 (the load is a multiple of 4 bytes) The matching store overlaps with the load in multiples of 4 bytes. Given the alignment and overlap requirements. In some examples, at the time of selection, the load's chunk size will be chosen. The default chunk size is 1 byte. It will be promoted to 4-byte chunks if the following conditions are met:

A chunk size bit(s) indicating the chunk size is stored in the ICLB along with a chunky bit, indicating that this load is to be processed as a chunk. Defeature bits can be added for chunky selection to prevent 4-byte chunk selection and/or to prevent chunky selection completely.

201 203 203 201 203 201 103 201 3 FIG. Loads that are detected as chunky schedule pipelineto suppress early wakeup and prepare to acquire the CPR. If the CPRis free, chunky load will setup all its payload to be written in to the CPR and set the valid bit next cycle. Chunky load attempts to arbitrate for its first chunk into main load pipeline.shows each chunk dispatch from the CPRto enter the load pipe. Each chunkissues as a load down the load pipe, asserting an additional bit to indicate that the load is a CPF chunk.

202 203 201 202 201 204 201 The chunky partial load logicand the CPRhold the state of the chunky load while it is being executed, and control the issuing of individual chunks down the load pipe. The chunky partial load logicsits at the beginning of the load pipeand holds the address and control data from the ICLB, and is responsible for issuing chunk loads down the load pipe, and eventually issuing the wakeup.

201 305 305 203 305 201 305 3 FIG. 5 FIG. 4 FIG. Chunked loads proceed down the load pipeas shown inin the usual manner as for other loads, but in separate chunks as shown in. In the final stage of the pipeline, successful loads typically write back their data and signal completion. Instead, CPF loads write data into a data register, which accumulates the data until the final chunk. When the last chunk of the original load is dispatched (0x13 in the example), a last chunk indication is asserted.shows the dispatch of the last chunk. The bytes of the registerare enabled based on the count of chunks completed by the CPR. In addition, a bit is maintained for the life of the CPF load to track success or failure of each chunk. The first chunk that fails to complete will set this bit, and update the loads state accordingly. If the last chunk completes without having set the failure bit, then all data is in the registerand may be written back. In some examples, the chunky data collection can be achieved by the pipeline, a buffer or some other collection mechanism, instead of the register.

305 203 305 6 FIG. When the last chunk of the original load is dispatched (0x13 in the example), a last chunk indication is asserted. The bytes of the registerare enabled based on the count of chunks completed by the CPR. In addition, a bit (e.g., chunky_bad bit) is maintained for the life of the CPF load to track success or failure of each chunk. The first chunk that fails to complete will set this bit, and update the loads state accordingly. If the last chunk completes without having set the failure bit set, then all data is in the registerand may be written back, as shown in.

6 FIG. 305 601 In, the successfully collected and merged chunks (e.g., in register) are written to a storage location, such as a global storage buffer (GLB). In some examples, the collected and merged chunks are sent to a memory, such as a cache memory (e.g., L1 cache memory).

202 203 305 The chunky_bad bit is maintained (e.g., chunky partial logic, CPRor register) which indicates whether the chunky load in progress is on track to complete. The bit is cleared at reset, or the first chunk of a chunky load. It gets set on the first chunk that fails to complete successfully.

204 204 204 The first chunk of a load that fails to complete is responsible for updating the ICLB state. For the chunk that failed to complete, that chunk's block-code information is updated into the ICLB. Remaining chunks will not update ICLB. Failing chunks will also clear the chunky bit in the ICLBso that subsequent attempts of the load will re-assess the need for chunky mode.

204 201 204 203 201 Because the first failing chunk updates the ICLBwhen it reaches the end of the load pipe, it opens an opportunity for the same load to reschedule by clearing the bit in ICLB. However, the CPRdoes not know that the load is bad, and will continue to send the remaining chunks, which will block the load from scheduling again. If the failing chunk is early enough, there will be sufficient time for the load to reschedule and take the load pipeimmediately after the last chunk of the chunky load completes. This case results in the same load being in the load pipe in multiple stages simultaneously. This condition should be benign as it is guaranteed that the earlier chunky load will not write back.

7 FIG. 7 FIG. 201 305 Furthermore, as shown in, if a situation arises where a previous chunk through the load pipeis collected by register, the Store identity (ID) will identify that the collection is incorrect, thereby indicating failure, as shown in.

601 601 601 601 When a load binds to data in chunky mode, each pass through the pipe updates the GLBaccording to the conditions for a normal load. Because the load may bind to data multiple times, there is an additional condition that must be met with in updating the Store ID. Only the oldest Store ID is written into the GLB. The GLBdoes not support read-modify-write operations, so the determination is handled in the load pipe. The previously written Store ID and a valid indication is stored at the end of the load pipe. If the load needs to update a Store ID in the GLB, having passed unknown stores, it compares its Store ID against the ID of the previous chunk to determine if it is valid.

201 204 Furthermore, any chunk going down the load pipecould be canceled. The cancellation of the chunk will result in the chunky load being dropped. The clear mechanism is identical for that of normal loads. The chunk will have its load value de-asserted, but the chunky indication will remain asserted. This condition is used to identify that the load has been cleared. A canceled chunky load is marked as bad to prevent writeback, but doesn't update ICLB.

203 204 203 203 203 To ensure nothing escapes, the CPRwill be checked for clear conditions against the alignment, similar to the ICLB. The CPRvalid bit is cleared, and a new load (chunky or otherwise) may be scheduled at the next opportunity. The CPRdoes not indicate last-chunk in the load pipe in this case. However, the first chunk of the next chunky load will resolve this condition. Even though the CPRis cleared, an arbitrary number of chunks may exist in the pipe and will drain. Some or all of these may signal cancellation.

Loads are marked for chunky mode after failing to forward from the store data buffer due to a partial data overlap. A load marked for chunky mode will enter chunky mode the next time it is scheduled from the ICLB. The chunky load blocks the ICLB and lower priority requests from issuing down the pipe until it issues all chunks. Higher priority requests may interrupt the chunky load causing it to stall until the pipe is free. The default chunk size is one byte. A load may instead attempt 4-byte chunks if certain alignment conditions are met. Either half of a split load may enter chunky mode if normal conditions are met. 256-bit loads, or the split halves of 256-bit loads are prevented from entering chunky mode. This reduces the size of the CPR and reduces complexity in rotating split requests. Chunky loads will not send a wakeup to out of order until the final chunk enters the pipe successfully. Chunky loads will not write-back to out of order until the final chunk (and all prior) successfully complete and bind to data. Chunky loads that are unable to complete a chunk will continue to block the pipe until the last chunk is scheduled. This is to reduce complexity of validating all possible cancel alignments. Each chunk that completes successfully is considered data-bound, and updates the GLB. In some examples, one or more of the following basic rules can be implemented for loads to enter and execute in chunky mode.

8 FIG. 400 801 400 802 500 803 500 804 illustrates a flow diagram of a methodwhich can be practiced by a processor as described above that operates on a chunky partial load logic and chunky partial register with attended pipeline and storage. At operation, the methodidentifies an overlap of partial load to store forwarding in a load pipeline for a load. At operation, the methoddecomposes the load into chunks of uniform size for issuing each chunk as a separate chunky load. At operation, the methodissues the decomposed chunks separately into the load pipeline as a set of load operations. At operation, the method collects separate results of the set of load operations on processing the chunks at an output of the load pipeline to merge the separate results.

This method provides predictable latency for partial forwarding that scales well with pipeline depth. Given a pipeline depth of T and a load of N chunks, the load can complete in T+N−1 cycles, while greedy algorithms requiring feedback will take T*n cycles, where n<=N. While the greedy algorithms may use fewer chunks, the CPF algorithm has superior latency for deeper pipelines.

200 200 200 9 FIG. 11 FIG. 12 FIG. 10 FIG. 13 FIG.A 13 FIG.B 14 FIG. 15 FIG. 16 FIG. 17 FIG. Although the disclosure describes some examples above, other techniques can implement the same or equivalent techniques described. The processorcan be implemented in a processor or coprocessor shown in,andperforming operations () to execute a load instruction.shows a pipeline that can be duplicated in a processor, including the processor.shows an example system having execution units and memory units to operate on Loads and Stores to perform the above described operations.shows another example of an execution unit to perform the functions described herein.shows a register architecture showing various registers that can be used with the processor.andshow an instruction format and addressing information which can be used for a Load instructions to perform the load operations described herein.

9 FIG. 903 901 illustrates examples of computing hardware to process a load instruction. As illustrated, storagestores a load instructionto be executed.

901 905 905 16 FIG. The instructionis received by decoder circuitry. For example, the decoder circuitryreceives this instruction from fetch circuitry (not shown). The instruction may be in any suitable format, such as that describe with reference tobelow. In an example, the instruction includes fields for an opcode and a destination identifier. In some examples, the sources and destination are registers, and in other examples one or more are memory locations. In some examples, one or more of the sources may be an immediate operand.

905 909 905 More detailed examples of at least one instruction format for the instruction will be detailed later. The decoder circuitrydecodes the instruction into one or more operations. In some examples, this decoding includes generating a plurality of micro-operations to be performed by execution circuitry (such as execution circuitry). The decoder circuitryalso decodes instruction prefixes.

907 In some examples, register renaming, register allocation, and/or scheduling circuitryprovides functionality for one or more of: 1) renaming logical operand values to physical operand values (e.g., a register alias table in some examples), 2) allocating status bits and flags to the decoded instruction, and 3) scheduling the decoded instruction for execution by execution circuitry out of an instruction pool (e.g., using a reservation station in some examples).

908 909 Registers (register file) and/or memorystore data as operands of the instruction to be operated by execution circuitry. Example register types include packed data registers, general purpose registers (GPRs), and floating-point registers.

909 Execution circuitryexecutes the decoded instruction.

911 908 In some examples, retirement/write back circuitryarchitecturally commits the destination register into the registers or memoryand retires the instruction.

10 FIG. 13 FIG.(B) illustrates an example method performed by a processor to process a load instruction. For example, a processor core as shown in, a pipeline as detailed below, etc., performs this method.

1001 At, an instance of single instruction is fetched. For example, a load instruction is fetched. In some examples, the instruction further includes a field for a writemask. In some examples, the instruction is fetched from an instruction cache. The opcode indicates a load to be perform.

1003 905 1340 The fetched instruction is decoded at. For example, the fetched load instruction is decoded by decoder circuitry such as decoder circuitryor decode circuitrydetailed herein.

1005 1007 909 1360 9 FIG. 13 FIG.(B) Data values associated with the source operands of the decoded instruction are retrieved when the decoded instruction is scheduled at. For example, when one or more of the source operands are memory operands, the data from the indicated memory location is retrieved. At, the decoded instruction is executed by execution circuitry (hardware)shown in, or execution cluster(s)shown in.

1009 In some examples, the instruction is committed or retired at.

11 FIG. 1100 1170 1180 1150 1170 1180 1170 1180 1100 illustrates an example computing system. Multiprocessor systemis an interfaced system and includes a plurality of processors or cores including a first processorand a second processorcoupled via an interfacesuch as a point-to-point (P-P) interconnect, a fabric, and/or bus. In some examples, the first processorand the second processorare homogeneous. In some examples, first processorand the second processorare heterogenous. Though the example multiprocessor systemis shown to have two processors, the system may have three or more processors, or may be a single processor system. In some examples, the computing system is a system on a chip (SoC).

1170 1180 1172 1182 1170 1176 1178 1180 1186 1188 1170 1180 1150 1178 1188 1172 1182 1170 1180 1132 1134 Processorsandare shown including integrated memory controller (IMC) circuitryand, respectively. Processoralso includes interface circuitsand; similarly, second processorincludes interface circuitsand. Processors,may exchange information via the interfaceusing interface circuits,. IMCsandcouple the processors,to respective memories, namely a memoryand a memory, which may be portions of main memory locally attached to the respective processors.

1170 1180 1190 1152 1154 1176 1194 1186 1198 1190 1138 1192 1138 Processors,may each exchange information with a network interface (NW I/F)via individual interfaces,using interface circuits,,,. The network interface(e.g., one or more of an interconnect, bus, and/or fabric, and in some examples is a chipset) may optionally exchange information with a co-processorvia an interface circuit. In some examples, the co-processoris a special-purpose processor, such as, for example, a high-throughput processor, a network or communication processor, a compression engine, a graphics processor, a general purpose graphics processing unit (GPGPU), a neural-network processing unit (NPU), an embedded processor, a security processor, a cryptographic accelerator, a matrix accelerator, an in-memory analytics accelerator,, a data streaming accelerator, data graph operations, or the like.

1170 1180 A shared cache (not shown) may be included in either processor,or outside of both processors, yet connected with the processors via an interface such as P-P interconnect, such that either or both processors' local cache information may be stored in the shared cache if a processor is placed into a low power mode.

1190 1116 1196 1116 1116 1117 1170 1180 1138 1117 1117 1117 Network interfacemay be coupled to a first interfacevia interface circuit. In some examples, first interfacemay be an interface such as a Peripheral Component Interconnect (PCI) interconnect, a PCI Express interconnect or another I/O interconnect. In some examples, first interfaceis coupled to a power control unit (PCU), which may include circuitry, software, and/or firmware to perform power management operations with regard to the processors,and/or co-processor. PCUprovides control information to a voltage regulator (not shown) to cause the voltage regulator to generate the appropriate regulated voltage. PCUalso provides control information to control the operating voltage generated. In various examples, PCUmay include a variety of power management logic units (circuitry) to perform hardware-based power management. Such power management may be wholly processor controlled (e.g., by various processor hardware, and which may be triggered by workload and/or power, thermal or other processor constraints) and/or the power management may be performed responsive to external sources (such as a platform or power management source or system software).

1117 1170 1180 1117 1170 1180 1117 1117 1117 PCUis illustrated as being present as logic separate from the processorand/or processor. In other cases, PCUmay execute on a given one or more of cores (not shown) of processoror. In some cases, PCUmay be implemented as a microcontroller (dedicated or general-purpose) or other control logic configured to execute its own dedicated power management code, sometimes referred to as P-code. In yet other examples, power management operations to be performed by PCUmay be implemented externally to a processor, such as by way of a separate power management integrated circuit (PMIC) or another component external to the processor. In yet other examples, power management operations to be performed by PCUmay be implemented within BIOS or other system software.

1114 1116 1118 1116 1120 1115 1116 1120 1120 1122 1127 1128 1128 1130 903 1124 1120 1100 Various I/O devicesmay be coupled to first interface, along with a bus bridgewhich couples first interfaceto a second interface. In some examples, one or more additional processor(s), such as co-processors, high throughput many integrated core (MIC) processors, GPGPUs, accelerators (such as graphics accelerators or digital signal processing (DSP) units), field programmable gate arrays (FPGAs), or any other processor, are coupled to first interface. In some examples, second interfacemay be a low pin count (LPC) interface. Various devices may be coupled to second interfaceincluding, for example, a keyboard and/or mouse, communication devicesand storage circuitry. Storage circuitrymay be one or more non-transitory machine-readable storage media as described below, such as a disk drive or other mass storage device which may include instructions/code and dataand may implement the storagein some examples. Further, an audio I/Omay be coupled to second interface. Note that other architectures than the point-to-point architecture described above are possible. For example, instead of the point-to-point architecture, a system such as multiprocessor systemmay implement a multi-drop interface or other such architecture.

Processor cores may be implemented in different ways, for different purposes, and in different processors. For instance, implementations of such cores may include: 1) a general purpose in-order core intended for general-purpose computing; 2) a high-performance general purpose out-of-order core intended for general-purpose computing; 3) a special purpose core intended primarily for graphics and/or scientific (throughput) computing. Implementations of different processors may include: 1) a CPU including one or more general purpose in-order cores intended for general-purpose computing and/or one or more general purpose out-of-order cores intended for general-purpose computing; and 2) a co-processor including one or more special purpose cores intended primarily for graphics and/or scientific (throughput) computing. Such different processors lead to different computer system architectures, which may include: 1) the co-processor on a separate chip from the CPU; 2) the co-processor on a separate die in the same package as a CPU; 3) the co-processor on the same die as a CPU (in which case, such a co-processor is sometimes referred to as special purpose logic, such as integrated graphics and/or scientific (throughput) logic, or as special purpose cores); and 4) a system on a chip (SoC) that may be included on the same die as the described CPU (sometimes referred to as the application core(s) or application processor(s)), the above described co-processor, and additional functionality. Example core architectures are described next, followed by descriptions of example processors and computer architectures.

12 FIG. 11 FIG. 1200 1200 1202 1210 1216 1200 1202 1214 1210 1208 1216 1200 1170 1180 1138 1115 illustrates a block diagram of an example processor and/or SoCthat may have one or more cores and an integrated memory controller. The solid lined boxes illustrate a processor and/or SoCwith a single core(A), system agent unit circuitry, and a set of one or more interface controller unit(s) circuitry, while the optional addition of the dashed lined boxes illustrates an alternative processor and/or SoCwith multiple cores(A)-(N), a set of one or more integrated memory controller unit(s) circuitryin the system agent unit circuitry, and special purpose logic, as well as a set of one or more interface controller unit(s) circuitry. Note that the processor and/or SoCmay be one of the processorsor, or co-processororof.

1200 1208 1202 1202 1202 1200 1200 Thus, different implementations of the processor and/or SoCmay include: 1) a CPU with the special purpose logicbeing a high-throughput processor, a network or communication processor, a compression engine, a graphics processor, a general purpose graphics processing unit (GPGPU), a neural-network processing unit (NPU), an embedded processor, a security processor, a matrix accelerator, an in-memory analytics accelerator, a compression accelerator, a data streaming accelerator, data graph operations, or the like(which may include one or more cores, not shown), and the cores(A)-(N) being one or more general purpose cores (e.g., general purpose in-order cores, general purpose out-of-order cores, or a combination of the two); 2) a co-processor with the cores(A)-(N) being a large number of special purpose cores intended primarily for graphics and/or scientific (throughput); and 3) a co-processor with the cores(A)-(N) being a large number of general purpose in-order cores. Thus, the processor and/or SoCmay be a general-purpose processor, co-processor or special-purpose processor, such as, for example, a network or communication processor, compression engine, graphics processor, GPGPU (general purpose graphics processing unit), a high throughput many integrated core (MIC) co-processor (including 30 or more cores), embedded processor, or the like. The processor may be implemented on one or more chips. The processor and/or SoCmay be a part of and/or may be implemented on one or more substrates using any of a number of process technologies, such as, for example, complementary metal oxide semiconductor (CMOS), bipolar CMOS (BiCMOS), P-type metal oxide semiconductor (PMOS), or N-type metal oxide semiconductor (NMOS).

1204 1202 1206 1214 1206 1212 1208 1206 1210 1206 1202 1216 1202 1218 A memory hierarchy includes one or more levels of cache unit(s) circuitry(A)-(N) within the cores(A)-(N), a set of one or more shared cache unit(s) circuitry, and external memory (not shown) coupled to the set of integrated memory controller unit(s) circuitry. The set of one or more shared cache unit(s) circuitrymay include one or more mid-level caches, such as level 2 (L2), level 3 (L3), level 4 (L4), or other levels of cache, such as a last level cache (LLC), and/or combinations thereof. While in some examples interface network circuitry(e.g., a ring interconnect) interfaces the special purpose logic(e.g., integrated graphics logic), the set of shared cache unit(s) circuitry, and the system agent unit circuitry, alternative examples use any number of well-known techniques for interfacing such units. In some examples, coherency is maintained between one or more of the shared cache unit(s) circuitryand cores(A)-(N). In some examples, interface controller unit(s) circuitrycouple the cores(A)-(N) to one or more other devicessuch as one or more I/O devices, storage, one or more communication devices (e.g., wireless networking, wired networking, etc.), etc.

1202 1210 1202 1210 1202 1208 In some examples, one or more of the cores(A)-(N) are capable of multi-threading. The system agent unit circuitryincludes those components coordinating and operating cores(A)-(N). The system agent unit circuitrymay include, for example, power control unit (PCU) circuitry and/or display unit circuitry (not shown). The PCU may be or may include logic and components needed for regulating the power state of the cores(A)-(N) and/or the special purpose logic(e.g., integrated graphics logic). The display unit circuitry is for driving one or more externally connected displays.

1202 1202 1202 The cores(A)-(N) may be homogenous in terms of instruction set architecture (ISA). Alternatively, the cores(A)-(N) may be heterogeneous in terms of ISA; that is, a subset of the cores(A)-(N) may be capable of executing an ISA, while other cores may be capable of executing only a subset of that ISA or another ISA.

13 FIG.(A) 1300 1302 1304 1306 1308 1310 1312 1314 1316 1318 1322 1324 1302 1306 1306 1314 1316 In, a processor pipelineincludes a fetch stage, an optional length decoding stage, a decode stage, an optional allocation (Alloc) stage, an optional renaming stage, a schedule (also known as a dispatch or issue) stage, an optional register read/memory read stage, an execute stage, a write back/memory write stage, an optional exception handling stage, and an optional commit stage. One or more operations can be performed in each of these processor pipeline stages. For example, during the fetch stage, one or more instructions are fetched from instruction memory, and during the decode stage, the one or more fetched instructions may be decoded, addresses (e.g., load store unit (LSU) addresses) using forwarded register ports may be generated, and branch forwarding (e.g., immediate offset or a link register (LR)) may be performed. In some examples, the decode stageand the register read/memory read stagemay be combined into one pipeline stage. In some examples, during the execute stage, the decoded instructions may be executed, LSU address/data pipelining to an Advanced Microcontroller Bus (AMB) interface may be performed, multiply and add operations may be performed, arithmetic operations with branch results may be performed, etc.

13 FIG.(B) 1300 1338 1302 1304 1340 1306 1352 1308 1310 1356 1312 1358 1370 1314 1360 1316 1370 1358 1318 1322 1354 1358 1324 By way of example, the example register renaming, out-of-order issue/execution architecture core ofmay implement the pipelineas follows: 1) the instruction fetch circuitryperforms the fetch and length decoding stagesand; 2) the decode circuitryperforms the decode stage; 3) the rename/allocator unit circuitryperforms the allocation stageand renaming stage; 4) the scheduler(s) circuitryperforms the schedule stage; 5) the physical register file(s) circuitryand the memory unit circuitryperform the register read/memory read stage; the execution cluster(s)perform the execute stage; 6) the memory unit circuitryand the physical register file(s) circuitryperform the write back/memory write stage; 7) various circuitry may be involved in the exception handling stage; and 8) the retirement unit circuitryand the physical register file(s) circuitryperform the commit stage.

13 FIG.(B) 1390 1330 1350 1370 1390 1390 shows a processor coreincluding front-end unit circuitrycoupled to execution engine unit circuitry, and both are coupled to memory unit circuitry. The coremay be a reduced instruction set architecture computing (RISC) core, a complex instruction set architecture computing (CISC) core, a very long instruction word (VLIW) core, or a hybrid or alternative core type. As yet another option, the coremay be a special-purpose core, such as, for example, a network or communication core, compression engine, co-processor core, general purpose computing graphics processing unit (GPGPU) core, graphics core, or the like.

1330 1332 1334 1336 1338 1340 1334 1370 1330 1340 1340 1340 1390 1340 1330 1340 1300 1340 1352 1350 The front-end unit circuitrymay include branch prediction circuitrycoupled to instruction cache circuitry, which is coupled to an instruction translation lookaside buffer (TLB), which is coupled to instruction fetch circuitry, which is coupled to decode circuitry. In some examples, the instruction cache circuitryis included in the memory unit circuitryrather than the front-end unit circuitry. The decode circuitry(or decoder) may decode instructions, and generate as an output one or more micro-operations, micro-code entry points, microinstructions, other instructions, or other control signals, which are decoded from, or which otherwise reflect, or are derived from, the original instructions. The decode circuitrymay further include address generation unit (AGU, not shown) circuitry. In some examples, the AGU generates an LSU address using forwarded register ports, and may further perform branch forwarding (e.g., immediate offset branch forwarding, LR register branch forwarding, etc.). The decode circuitrymay be implemented using various different mechanisms. Examples of suitable mechanisms include, but are not limited to, look-up tables, hardware implementations, programmable logic arrays (PLAs), microcode read only memories (ROMs), etc. In some examples, the coreincludes a microcode ROM (not shown) or other medium that stores microcode for certain macroinstructions (e.g., in decode circuitryor otherwise within the front-end unit circuitry). In some examples, the decode circuitryincludes a micro-operation (micro-op) or operation cache (not shown) to hold/cache decoded operations, micro-tags, or micro-operations generated during the decode or other stages of the processor pipeline. The decode circuitrymay be coupled to rename/allocator unit circuitryin the execution engine unit circuitry.

1350 1352 1354 1356 1356 1356 1356 1358 1358 1358 1358 1354 1354 1358 1360 1360 1362 1364 1362 1362 The execution engine unit circuitryincludes the rename/allocator unit circuitrycoupled to retirement unit circuitryand a set of one or more scheduler(s) circuitry. The scheduler(s) circuitryrepresents any number of different schedulers, including reservations stations, central instruction window, etc. In some examples, the scheduler(s) circuitrycan include arithmetic logic unit (ALU) scheduler/scheduling circuitry, ALU queues, address generation unit (AGU) scheduler/scheduling circuitry, AGU queues, etc. The scheduler(s) circuitryis coupled to the physical register file(s) circuitry. Each of the physical register file(s) circuitryrepresents one or more physical register files, different ones of which store one or more different data types, such as scalar integer, scalar floating-point, packed integer, packed floating-point, vector integer, vector floating-point, status (e.g., an instruction pointer that is the address of the next instruction to be executed), etc. In some examples, the physical register file(s) circuitryincludes vector registers unit circuitry, writemask registers unit circuitry, and scalar register unit circuitry. These register units may provide architectural vector registers, vector mask registers, general-purpose registers, etc. The physical register file(s) circuitryis coupled to the retirement unit circuitry(also known as a retire queue or a retirement queue) to illustrate various ways in which register renaming and out-of-order execution may be implemented (e.g., using a reorder buffer(s) (ROB(s)) and a retirement register file(s); using a future file(s), a history buffer(s), and a retirement register file(s); using a register maps and a pool of registers; etc.). The retirement unit circuitryand the physical register file(s) circuitryare coupled to the execution cluster(s). The execution cluster(s)includes a set of one or more execution unit(s) circuitryand a set of one or more memory access circuitry. The execution unit(s) circuitrymay perform various arithmetic, logic, floating-point or other types of operations (e.g., shifts, addition, subtraction, multiplication) and on various types of data (e.g., scalar integer, scalar floating-point, packed integer, packed floating-point, vector integer, vector floating-point). In some examples, execution unit(s) circuitrymay include hardware to support functionality for instructions for one or more of a compression engine, graphics processing, neural-network processing, in-memory analytics, matrix operations, cryptographic operations, data streaming operations, data graph operations, etc.

1356 1358 1360 1364 While some examples may include a number of execution units or execution unit circuitry dedicated to specific functions or sets of functions, other examples may include only one execution unit circuitry or multiple execution units/execution unit circuitry that all perform all functions. The scheduler(s) circuitry, physical register file(s) circuitry, and execution cluster(s)are shown as being possibly plural because certain examples create separate pipelines for certain types of data/operations (e.g., a scalar integer pipeline, a scalar floating-point/packed integer/packed floating-point/vector integer/vector floating-point pipeline, and/or a memory access pipeline that each have their own scheduler circuitry, physical register file(s) circuitry, and/or execution cluster—and in the case of a separate memory access pipeline, certain examples are implemented in which only the execution cluster of this pipeline has the memory access unit(s) circuitry). It should also be understood that where separate pipelines are used, one or more of these pipelines may be out-of-order issue/execution and the rest in-order.

1350 In some examples, the execution engine unit circuitrymay perform load store unit (LSU) address/data pipelining to an Advanced Microcontroller Bus (AMB) interface (not shown), and address phase and writeback, data phase load, store, and branches.

1364 1370 1372 1374 1376 1364 1372 1370 1334 1376 1370 1334 1374 1376 1376 The set of memory access circuitryis coupled to the memory unit circuitry, which includes data TLB circuitrycoupled to data cache circuitrycoupled to level 2 (L2) cache circuitry. In some examples, the memory access circuitrymay include load unit circuitry, store address unit circuitry, and store data unit circuitry, each of which is coupled to the data TLB circuitryin the memory unit circuitry. The instruction cache circuitryis further coupled to the level 2 (L2) cache circuitryin the memory unit circuitry. In some examples, the instruction cacheand the data cacheare combined into a single instruction and data cache (not shown) in L2 cache circuitry, level 3 (L3) cache circuitry (not shown), and/or main memory. The L2 cache circuitryis coupled to one or more other levels of cache and eventually to a main memory.

1390 1390 The coremay support one or more instructions sets (e.g., the x86 instruction set architecture (optionally with some extensions that have been added with newer versions); the MIPS instruction set architecture; the ARM instruction set architecture (optionally with optional additional extensions such as NEON, etc.); RISC instruction set architecture), including the instruction(s) described herein. In some examples, the coreincludes logic to support a packed data instruction set architecture extension (e.g., AVX1, AVX2, AVX512, AMX, etc.), thereby allowing the operations used by many multimedia applications to be performed using packed data.

14 FIG. 13 FIG.(B) 1362 1362 1401 1403 1405 1407 1409 1401 1403 1405 1405 1407 1409 1362 illustrates examples of execution unit(s) circuitry, such as execution unit(s) circuitryof. As illustrated, execution unit(s) circuitrymay include one or more ALU circuits, optional vector/single instruction multiple data (SIMD) circuits, load/store circuits, branch/jump circuits, and/or Floating-point unit (FPU) circuits. ALU circuitsperform integer arithmetic and/or Boolean operations. Vector/SIMD circuitsperform vector/SIMD operations on packed data (such as SIMD/vector registers). Load/store circuitsexecute load and store instructions to load data from memory into registers or store from registers to memory. Load/store circuitsmay also generate addresses. Branch/jump circuitscause a branch or jump to a memory address depending on the instruction. FPU circuitsperform floating-point arithmetic. The width of the execution unit(s) circuitryvaries depending upon the example and can range from 16-bit to 1,024-bit, for example. In some examples, two or more smaller execution units are logically combined to form a larger execution unit (e.g., two 128-bit execution units are logically combined to form a 256-bit execution unit).

15 FIG. 1500 1500 1510 1510 1510 is a block diagram of a register architectureaccording to some examples. As illustrated, the register architectureincludes vector/SIMD registersthat vary from 128-bit to 1,024 bits width. In some examples, the vector/SIMD registersare physically 512-bits and, depending upon the mapping, only some of the lower bits are used. For example, in some examples, the vector/SIMD registersare ZMM registers which are 512 bits: the lower 256 bits are used for YMM registers and the lower 128 bits are used for XMM registers. As such, there is an overlay of registers. In some examples, a vector length field selects between a maximum length and one or more other shorter lengths, where each such shorter length is half the length of the preceding length. Scalar operations are operations performed on the lowest order data element position in a ZMM/YMM/XMM register; the higher order data element positions are either left the same as they were prior to the instruction or zeroed depending on the example.

1500 1515 1515 1515 1515 In some examples, the register architectureincludes writemask/predicate registers. For example, in some examples, there are 8 writemask/predicate registers (sometimes called k0 through k7) that are each 16-bit, 32-bit, 64-bit, or 128-bit in size. Writemask/predicate registersmay allow for merging (e.g., allowing any set of elements in the destination to be protected from updates during the execution of any operation) and/or zeroing (e.g., zeroing vector masks allow any set of elements in the destination to be zeroed during the execution of any operation). In some examples, each data element position in a given writemask/predicate registercorresponds to a data element position of the destination. In other examples, the writemask/predicate registersare scalable and consists of a set number of enable bits for a given vector element (e.g., 8 enable bits per 64-bit vector element).

1500 1525 The register architectureincludes a plurality of general-purpose registers. These registers may be 16-bit, 32-bit, 64-bit, etc. and can be used for scalar operations. In some examples, these registers are referenced by the names RAX, RBX, RCX, RDX, RBP, RSI, RDI, RSP, and R8 through R15.

1500 1545 In some examples, the register architectureincludes scalar floating-point (FP) register filewhich is used for scalar floating-point operations on 32/64/80-bit floating-point data using the x87 instruction set architecture extension or as MMX registers to perform operations on 64-bit packed integer data, as well as to hold operands for some operations performed between the MMX and XMM registers.

1540 1540 1540 One or more flag registers(e.g., EFLAGS, RFLAGS, etc.) store status and control information for arithmetic, compare, and system operations. For example, the one or more flag registersmay store condition code information such as carry, parity, auxiliary carry, zero, sign, and overflow. In some examples, the one or more flag registersare called program status and control registers.

1520 Segment registerscontain segment points for use in accessing memory. In some examples, these registers are referenced by the names CS, DS, SS, ES, FS, and GS.

1535 1535 1560 1555 1170 1180 1138 1115 1200 1535 1555 Model specific registers or machine specific registers (MSRs)control and report on processor performance. Most MSRshandle system-related functions and are not accessible to an application program. For example, MSRs may provide control for one or more of: performance-monitoring counters, debug extensions, memory type range registers, thermal and power management, instruction-specific support, and/or processor feature/mode support. Machine check registersconsist of control, status, and error reporting MSRs that are used to detect and report on hardware errors. Control register(s)(e.g., CR0-CR4) determine the operating mode of a processor (e.g., processor,,,, and/or) and the characteristics of a currently executing task. In some examples, MSRsare a subset of control registers.

1530 1550 One or more instruction pointer register(s)store an instruction pointer value. Debug registerscontrol and allow for the monitoring of a processor or core's debugging operations.

1565 Memory (mem) management registersspecify the locations of data structures used in protected mode memory management. These registers may include a global descriptor table register (GDTR), interrupt descriptor table register (IDTR), task register, and a local descriptor table register (LDTR) register.

1500 908 13 58 Alternative examples may use wider or narrower registers. Additionally, alternative examples may use more, less, or different register files and registers. The register architecturemay, for example, be used in register file/memory, or physical register file(s) circuitry.

An instruction set architecture (ISA) may include one or more instruction formats. A given instruction format may define various fields (e.g., number of bits, location of bits) to specify, among other things, the operation to be performed (e.g., opcode) and the operand(s) on which that operation is to be performed and/or other data field(s) (e.g., mask). Some instruction formats are further broken down through the definition of instruction templates (or sub-formats). For example, the instruction templates of a given instruction format may be defined to have different subsets of the instruction format's fields (the included fields are typically in the same order, but at least some have different bit positions because there are less fields included) and/or defined to have a given field interpreted differently. Thus, each instruction of an ISA is expressed using a given instruction format (and, if defined, in a given one of the instruction templates of that instruction format) and includes fields for specifying the operation and the operands. For example, an example ADD instruction has a specific opcode and an instruction format that includes an opcode field to specify that opcode and operand fields to select operands (source1/destination and source2); and an occurrence of this ADD instruction in an instruction stream will have specific contents in the operand fields that select specific operands. In addition, though the description below is made in the context of x86 ISA, it is within the knowledge of one skilled in the art to apply the teachings of the present disclosure in another ISA.

Examples of the instruction(s) described herein may be embodied in different formats. Additionally, example systems, architectures, and pipelines are detailed below. Examples of the instruction(s) may be executed on such systems, architectures, and pipelines, but are not limited to those detailed.

16 FIG. 1603 illustrates examples of an instruction format. As illustrated, an instruction may include multiple components including, but not limited to, one or more fields for: one or more prefixes, an opcode, addressing information (e.g., register identifiers, memory addressing information, etc.), a displacement value, and/or an immediate value. Note that some instructions utilize some or all the fields of the format whereas others may only use the field for the opcode. In some examples, the order illustrated is the order in which these fields are to be encoded, however, it should be appreciated that in other examples these fields may be encoded in a different order, combined, etc.

1601 The prefix(es) f, when used, modifies an instruction. In some examples, one or more prefixes are used to repeat string instructions (e.g., 0xF0, 0xF 2, 0xF 3, etc.), to provide section overrides (e.g., 0x2E, 0x36, 0x3E, 0x26, 0x64, 0x65, 0x2E, 0x3E, etc.), to perform bus lock operations, and/or to change operand (e.g., 0x66) and address sizes (e.g., 0x67). Certain instructions require a mandatory prefix (e.g., 0x66, 0xF2, 0xF3, etc.). Certain of these prefixes may be considered “legacy” prefixes. Other prefixes, one or more examples of which are detailed herein, indicate, and/or provide further capability, such as specifying particular registers, etc. The other prefixes typically follow the “legacy” prefixes.

1603 1603 The opcode fieldis used to at least partially define the operation to be performed upon a decoding of the instruction. In some examples, a primary opcode encoded in the opcode fieldis one, two, or three bytes in length. In other examples, a primary opcode can be a different length. An additional 3-bit opcode field is sometimes encoded in another field.

1605 1605 1702 1704 1702 1704 1702 1742 1744 1746 17 FIG. The addressing information fieldis used to address one or more operands of the instruction, such as a location in memory or one or more registers.illustrates examples of the addressing information field. In this illustration, an optional MOD R/M byteand an optional Scale, Index, Base (SIB) byteare shown. The MOD R/M byteand the SIB byteare used to encode up to two operands of an instruction, each of which is a direct register or effective memory address. Note that both of these fields are optional in that not all instructions include one or more of these fields. The MOD R/M byteincludes a MOD field, a register (reg) field, and R/M field.

1742 1742 The content of the MOD fielddistinguishes between memory access and non-memory access modes. In some examples, when the MOD fieldhas a binary value of 11 (11b), a register-direct addressing mode is utilized, and otherwise a register-indirect addressing mode is used.

1744 1744 1744 1601 The register fieldmay encode either the destination register operand or a source register operand or may encode an opcode extension and not be used to encode any instruction operand. The content of register field, directly or through address generation, specifies the locations of a source or destination operand (either in a register or in memory). In some examples, the register fieldis supplemented with an additional bit from a prefix (e.g., prefix) to allow for greater addressing.

1746 1746 1742 The R/M fieldmay be used to encode an instruction operand that references a memory address or may be used to encode either the destination register operand or a source register operand. Note the R/M fieldmay be combined with the MOD fieldto dictate an addressing mode in some examples.

1704 1752 1754 1756 1752 1754 1754 1601 1756 1756 1601 1752 1754 scale The SIB byteincludes a scale field, an index field, and a base fieldto be used in the generation of an address. The scale fieldindicates a scaling factor. The index fieldspecifies an index register to use. In some examples, the index fieldis supplemented with an additional bit from a prefix (e.g., prefix) to allow for greater addressing. The base fieldspecifies a base register to use. In some examples, the base fieldis supplemented with an additional bit from a prefix (e.g., prefix) to allow for greater addressing. In practice, the content of the scale fieldallows for the scaling of the content of the index fieldfor memory address generation (e.g., for address generation that uses 2*index+base).

scale 1607 1605 1607 Some addressing forms utilize a displacement value to generate a memory address. For example, a memory address may be generated according to 2*index+base+displacement, index*scale+displacement, r/m+displacement, instruction pointer (RIP/EIP)+displacement, register+displacement, etc. The displacement may be a 1-byte, 2-byte, 4-byte, etc. value. In some examples, the displacement fieldprovides this value. Additionally, in some examples, a displacement factor usage is encoded in the MOD field of the addressing information fieldthat indicates a compressed displacement scheme for which a displacement value is calculated and stored in the displacement field.

1609 In some examples, the immediate value fieldspecifies an immediate value for the instruction. An immediate value may be encoded as a 1-byte value, a 2-byte value, a 4-byte value, etc.

References to “some examples,” “an example,” etc., indicate that the example described may include a particular feature, structure, or characteristic, but every example may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same example. Further, when a particular feature, structure, or characteristic is described in connection with an example, it is submitted that it is within the knowledge of one skilled in the art to affect such feature, structure, or characteristic in connection with other examples whether or not explicitly described.

Moreover, in the various examples described above, unless specifically noted otherwise, disjunctive language such as the phrase “at least one of A, B, or C” or “A, B, and/or C” is intended to be understood to mean either A, B, or C, or any combination thereof (i.e. A and B, A and C, B and C, and A, B and C).

The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense. It will, however, be evident that various modifications and changes may be made thereunto without departing from the broader spirit and scope of the disclosure as set forth in the claims.

Furthermore, the disclosure describes various examples in detail as noted above. Further examples are noted below that can be implemented:

a chunky partial logic to identify overlap of partial load to store forwarding in a load pipeline for a load, decompose the load into chunks of uniform size for issuance of each chunk as a separate chunky load and schedule the issuance of the chunks; and a chunky partial register to receive and store the chunks decomposed into the chunks and issue the chunks separately into the load pipeline as a load operation. Example 1. An apparatus comprising:

a data register to collect separate results of load pipeline operations on processing the chunks at an output of the load pipeline and merge the separate results upon completion of collecting the separate results. Example 2. The apparatus of Example 1 further comprising:

Example 3. The apparatus according to Examples 1-2, wherein a size of the chunks of uniform size is determined by the overlap of the load and store of the partial load to store forwarding.

Example 4. The apparatus according to Examples 2, wherein the size is further determined by an alignment of the load, store and the overlap.

Example 5. The apparatus according to Examples 2-4, wherein the size is 4-bytes when the load and store are aligned.

Example 6. The apparatus according to Examples 2-4, wherein the size defaults to 1-byte when the load and store are misaligned.

Example 7. The apparatus according to Example 1, wherein issuance of each chunk asserts a chunk bit as an indicator to indicate a chunk load operation to the load pipeline.

Example 8. The apparatus according to Example 7, wherein the issuance of a last chunk asserts a last chunk indicator to indicate a last chunk to be collected for completion of separate chunk load operations for the load.

identifying an overlap of partial load to store forwarding in a load pipeline for a load; decomposing the load into chunks of uniform size for issuing each chunk as a separate chunky load; issuing the decomposed chunks separately into the load pipeline as a set of load operations; and collecting separate results of the set of load operations on processing the chunks at an output of the load pipeline to merge the separate results. Example 9. A method comprising:

Example 10. The method according to Example 9, wherein a size of the chunks of uniform size is determined by the overlap of the load and store of the partial load to store forwarding.

Example 11. The method according to Example 10, wherein the size is further determined by an alignment of the load, store and the overlap.

Example 12. The method according to Example 11, wherein the size is 4-bytes when the load and store are aligned and the size defaults to 1-byte when the load and store are misaligned.

Example 13. The method according to Examples 9-11 further comprising asserting a chunk bit as an indicator to indicate a chunk load operation to the load pipeline.

Example 14. The method according to Example 13 further comprising asserting a last chunk indicator to indicate a last chunk to be collected for completion of separate chunk load operations for the load.

Example 15. The method according to Examples 9-14 further comprising indicating a failed chunk load operation for a chunk in the load pipeline to invalidate merging of the separate results as an invalid output.

a load pipeline; a chunky partial logic to identify overlap of partial load to store forwarding in the load pipeline for a load, decompose the load into chunks of uniform size for issuance of each chunk as a separate chunky load and schedule the issuance of the chunks; a chunky partial register to receive and store the chunks decomposed into the chunks and issue the chunks separately into the load pipeline as a load operation; and storage to collect separate results of load pipeline operations on processing the chunks at an output of the load pipeline and merge the separate results upon completion of collecting the separate results. Example 16. A system comprising:

Example 17. The system according to Example 16, wherein a size of the chunks of uniform size is determined by the overlap of the load and store of the partial load to store forwarding.

Example 18. The system according to Example 17, wherein the size is further determined by an alignment of the load, store and the overlap.

Example 19. The system according to Example 18, wherein the load pipeline indicates a failed chunk load operation for a chunk in the load pipeline to invalidate the merge of the separate results as an invalid output.

Example 20. The system according to Examples 16-18, wherein the storage is a store buffer or a cache memory.