Display Device Including Driving Transistor

Pursuant to 35 U.S.C. § 119(a), this application claims the benefit of an earlier filing date and right of priority to Korean Patent Application No. 10-2024-0188625, filed on December 17, 2024, the contents of which are hereby incorporated by reference in their entirety.

The present disclosure relates generally to a display device.

Recently, various flat panel display devices such as a liquid crystal display device (LCD), an organic light emitting diode (OLED) display device and a field emission display (FED) device having excellent properties of a thin profile, a light weight and a low power consumption have been developed and applied to various fields.

In an aspect of the present disclosure, a display device includes: a display panel including a display area having a plurality of subpixels and a non-display area at a periphery of the display area; a first transistor in each of the plurality of subpixels, the first transistor switched according to a voltage of a second node and connected to a first node and a third node; a second transistor in each of the plurality of subpixels, the second transistor switched according to a scan1 signal and connected to the second node and the third node, and the second transistor having a double gate type; a third transistor in each of the plurality of subpixels, the third transistor switched according to one of an odd scan2 signal and an even scan2 signal and connected to a data signal and the first node; a fourth transistor in each of the plurality of subpixels, the fourth transistor switched according to an emission signal and connected to a high level signal and the first node; a fifth transistor in each of the plurality of subpixels, the fifth transistor switched according to the emission signal and connected to the third node and a fourth node; a sixth transistor in each of the plurality of subpixels, the sixth transistor switched according to a scan4 signal and connected to an initial signal and the second node; a seventh transistor in each of the plurality of subpixels, the seventh transistor switched according to a scan3 signal and connected to an anode reset signal and the fourth node; an eighth transistor in each of the plurality of subpixels, the eighth transistor switched according to the scan3 signal and connected to a stress signal and the first node; and a light emitting diode in each of the plurality of subpixels, the light emitting diode connected to a low level signal and the fourth node.

It is to be understood that both the foregoing general description and the following detailed description are explanatory and are intended to provide further explanation of the disclosure as claimed.

A display device generally includes a display panel displaying an image and a driving unit supplying a signal and a power to the display panel. The driving unit includes a gate driving unit and a data driving unit supplying a gate voltage and a data voltage, respectively, to each pixel of the display panel.

The display device can display an image by compensating a threshold voltage of a driving transistor of each subpixel. However, problems can occur because the measured threshold voltage can vary across the display device due to a mobility difference between a transistor for detecting the threshold voltage and the driving transistor. As such, deterioration such as a local luminance deviation may occur.

Implementations of the present disclosure can provide a display device wherein a gate electrode of a driving transistor is charged to the same voltage regardless of a mobility deviation of a sampling transistor.

In some implementations, a display device is provided where deterioration such as a local luminance deviation can be mitigated, and a display quality can be improved. The improvements can be achieved by reduction of a difference of a measured threshold voltage by reducing a width of an initialization period and charging up a gate electrode of a driving transistor with the same voltage regardless of a mobility deviation of a sampling transistor.

1 2 Further, implementations of the present disclosure can provide a display device where deterioration such as a local luminance deviation can be mitigated, and a low power driving can be obtained due to reduction of a difference of a measured threshold voltage by forming a coupling capacitor between a scansignal and a scansignal and increasing an on-current of a sampling transistor.

Additional features and advantages of the disclosure will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the disclosure. These and other advantages of the disclosure will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

Advantages and features of the present disclosure, and implementation methods thereof will be clarified through following example aspects described with reference to the accompanying drawings. The present disclosure may, however, be embodied in different forms and should not be construed as limited to the example aspects set forth herein. Rather, these example aspects are provided so that this disclosure may be sufficiently thorough and complete to assist those skilled in the art to fully understand the scope of the present disclosure. Further, the present disclosure is only defined by scopes of claims.

The shapes, sizes, ratios, angles, numbers, and the like, which are illustrated in the drawings to describe various example aspects of the present disclosure, are merely given by way of example. Therefore, the present disclosure is not limited to the illustrations in the drawings. Like reference numerals refer to like elements throughout the specification, unless otherwise specified.

In the following description, where the detailed description of the relevant known function or configuration may unnecessarily obscure a feature or aspect of the present disclosure, a detailed description of such known function or configuration may be omitted or a brief description may be provided.

Where the terms "comprise," "have," "include," and the like are used, one or more other elements may be added unless the term, such as "only," is used. An element described in the singular form is intended to include a plurality of elements, and vice versa, unless the context clearly indicates otherwise.

In construing an element, the element is to be construed as including an error or a tolerance range even where no explicit description of such an error or tolerance range is provided.

Where positional relationships are described, for example, where the positional relationship between two parts is described using "on," "over," "under," "above," "below," "beside," "next," or the like, one or more other parts may be located between the two parts unless a more limiting term, such as "immediate(ly)," "direct(ly)," or "close(ly)" is used. For example, where an element or layer is disposed "on" another element or layer, a third layer or element may be interposed therebetween.

Although the terms "first," "second," A, B, (a), (b), and the like may be used herein to refer to various elements, these elements should not be interpreted to be limited by these terms as they are not used to define a particular order or precedence. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure.

The term "at least one" should be understood to include all combinations of one or more of related elements. For example, the term of "at least one of first, second and third elements" may include all combinations of two or more of the first, second and third elements as well as the first, second or third element.

The term "display device" may include a display device in a narrow sense such as liquid crystal module (LCM), an organic light emitting diode (OLED) module and a quantum dot (QD) module including a display panel and a driving unit for driving the display panel. In addition, the term "display device" may include a complete product (or a final product) including the LCM, the OLED module and the QD module such as a notebook computer, a television, a computer monitor, an equipment display device including an automotive display apparatus or other industrial or consumer equipment displays, and a set electronic apparatus or a set device (or a set apparatus) such as a mobile electronic apparatus of a smart phone or an electronic pad.

Accordingly, a display device of the present disclosure may include an applied product or a set device of a final user's device including the LCM, the OLED module and the QD module as well as a display device in a narrow sense such as the LCM, the OLED module and the QD module.

According to circumstances, the LCM, the OLED module and the QD module having a display panel and a driving unit may be expressed as "a display device", and an electronic apparatus of a complete product including the LCM, the OLED module and the QD module may be expressed as "a set device." For example, a display device in a narrow sense may include a display panel of a liquid crystal, an organic light emitting diode and a quantum dot and a source printed circuit board (PCB) of a control unit for driving the display panel, and a set device may further include a set PCB of a set control unit electrically connected to the source PCB for controlling the entire set device.

The display panel of the present disclosure may include all kinds of display panels such as a liquid crystal display panel, an organic light emitting diode display panel, a quantum dot display panel and an electroluminescent display panel. The display panel of the present disclosure is not limited to a specific display panel of a bezel bending having a flexible substrate for an organic light emitting diode display panel and a lower back plate supporter. A shape or a size of the display panel for the display device of the present disclosure is not limited thereto.

For example, when the display panel is an organic light emitting diode display panel, the display panel may include a plurality of gate lines, a plurality of data lines and a subpixel in a crossing region of the plurality of gate lines and the plurality of data lines. The display panel may include an array having a thin film transistor of an element for selectively applying a voltage to each subpixel, an emitting element layer on the array and an encapsulating substrate or an encapsulation part covering the emitting element layer. The encapsulation part may protect the thin film transistor and the emitting element layer from an external impact and may prevent or at least reduce penetration of a moisture or oxygen into the emitting element layer. In addition, the emitting element layer on the array may include an inorganic light emitting layer, for example, a nano-sized material layer or a quantum dot.

The thin film transistor of the present disclosure may include one of an oxide thin film transistor, an amorphous silicon thin film transistor, and a low temperature polycrystalline silicon thin film transistor.

Features of various implementations of the present disclosure may be partially or entirely coupled to or combined with each other. They may be linked and operated technically in various ways as those skilled in the art may sufficiently understand. The aspects may be carried out independently of or in association with each other in various combinations.

Hereinafter, a display device according to various example implementations of the present disclosure where an influence on an oxide semiconductor layer of a thin film transistor of a driving element is reduced by shielding a light emitted and transmitted from a subpixel and/or a light inputted from an exterior will be described in detail with reference to the accompanying drawings.

1 FIG. is a view showing a display device according to a first implementation of the present disclosure. Although the display device may be an organic light emitting diode (OLED) display device, it is not limited thereto. For example, the display device may be a quantum dot display device, a micro light emitting diode (LED) display device or a mini light emitting diode (LED) display device.

1 FIG. 110 120 122 124 126 128 In, a display deviceaccording to a first implementation of the present disclosure includes a timing controlling unit(e.g., a circuit), a data driving unit(e.g., a circuit), first and second gate driving unitsand(e.g., circuits) and a display panel.

120 The timing controlling unitgenerates an image data RGB, a data control signal DCS and a gate control signal GCS using an image signal IS and a plurality of timing signals including a data enable signal DE, a horizontal synchronization signal HSY, a vertical synchronization signal VSY and a clock signal CLK transmitted from an external system such as a graphic card or a television system.

120 122 124 126 The timing controlling unittransmits the image data RGB and the data control signal DCS to the data driving unitand transmits the gate control signal GCS to the first and second gate driving unitsand.

122 120 128 3 FIG. The data driving unitgenerates a data signal (data voltage) Vda (of) using the image data RGB and the data control signal DCS transmitted from the timing controlling unitand applies the data signal Vda to a data line DL of the display panel.

124 126 1 2 2 4 120 1 2 2 3 4 128 3 FIG. The first and second gate driving unitsandgenerate gate signals (gate voltages) Sc(n), Sco(n), Sce(n), Sc3(n), Sc(n) and Em(n) (of) using the gate control signal GCS transmitted from the timing controlling unitand apply the gate signals Sc(n), Sco(n), Sce(n), Sc(n), Sc(n) and Em(n) to a gate line GL of the display panel.

124 126 128 The first and second gate driving unitsandmay have a gate in panel (GIP) type to be formed in a non-display area NDA of a substrate of the display panelhaving the gate line GL, the data line DL and a pixel P.

124 126 128 128 1 FIG. Although the first and second gate driving unitsandare disposed in both side portions of the display panelin a first implementation of, one gate driving unit may be disposed in one side portion of the display panelin another implementation.

128 128 1 2 2 3 4 128 The display panelincludes a display area DA at a central portion thereof and a non-display area NDA surrounding the display area DA. The display paneldisplays an image using the gate signals Sc(n), Sco(n), Sce(n), Sc(n), Sc(n) and Em(n) and the data signal Vda. For displaying an image, the display panelincludes a plurality of pixels P, a plurality of gate lines GL and a plurality of data lines DL in the display area DA.

1 2 3 4 1 2 3 4 1 2 3 4 Each of the plurality of pixels P includes first, second, third and fourth subpixels SP, SP, SPand SP. The gate line GL and the data line DL cross each other to define the first, second, third and fourth subpixels SP, SP, SPand SP, and each of the first, second, third and fourth subpixels SP, SP, SPand SPis connected to the gate line GL and the data line DL.

1 2 3 4 For example, the first, second, third and fourth subpixels SP, SP, SPand SPmay correspond to red, green, blue and white colors, respectively.

1 2 3 4 1 2 3 1 FIG. Although one pixel P exemplarily includes the first, second, third and fourth subpixels SP, SP, SPand SPin a first implementation of, one pixel P may include first, second and third subpixels SP, SPand SPcorresponding to red, green and blue colors, respectively, in another implementation.

110 1 2 3 4 When the display deviceis an organic light emitting diode (OLED) display device, each of the first, second, third and fourth subpixels SP, SP, SPand SPmay include a plurality of transistors such as a switching transistor, a driving transistor and a sampling transistor, a storage capacitor and a light emitting diode.

128 1 4 110 A structure of the display paneland the subpixels SPto SPof the display devicewill be illustrated with reference to drawings.

2 FIG. 3 FIG. is a block diagram showing first and second gate driving units and a display panel of a display device according to a first implementation of the present disclosure, andis a circuit diagram showing a subpixel of a display device according to a first implementation of the present disclosure.

2 FIG. 124 110 1 1 2 2 2 2 3 3 126 110 2 2 2 2 4 4 128 124 126 In, the first gate driving unitof the display deviceaccording to a first implementation of the present disclosure includes a scanblock Bsc, an odd scanblock Bsco, an even scanblock Bsce and a scanblock Bsc, and the second gate driving unitof the display deviceaccording to a first implementation of the present disclosure includes an odd scanblock Bsco, an even scanblock Bsce, a scanblock Bscand an emission block Bem. The display area DA of the display panelis disposed between the first and second gate driving unitsand.

1 1 2 2 2 2 3 3 4 4 124 126 In another implementation, the disposition structure of the scanblock Bsc, the odd scanblock Bsco, the even scanblock Bsce, the scanblock Bsc, the scanblock Bscand the emission block Bem in the first and second gate driving unitsandmay be variously changed.

1 128 3 3 4 4 128 3 3 128 1 1 128 4 4 2 FIG. For example, the scanblock Bsc1 may be disposed farther from the display panelthan the scanblock Bscand the scanblock Bscmay be disposed farther from the display panelthan the emission block Bem in a first implementation of. In another implementation, the scanblock Bscmay be disposed farther from the display panelthan the scanblock Bscand the emission block Bem may be disposed farther from the display panelthan the scanblock Bsc.

1 1 2 2 2 2 3 3 124 2 2 2 2 4 4 126 Each of the scanblock Bsc, the odd scanblock Bsco, the even scanblock Bsce and the scanblock Bscof the first gate driving unitand the odd scanblock Bsco, the even scanblock Bsce, the scanblock Bscand the emission block Bem of the second gate driving unitmay be one stage of a shift register, and the shift register may include a plurality of stages connected to each other in a cascade type.

124 1 2 2 2 2 3 3 1 1 2 2 2 2 3 3 3 FIG. 3 FIG. 3 FIG. 3 FIG. In the first gate driving unit, the scan1 block Bsc, the odd scanblock Bsco, the even scanblock Bsce and the scanblock Bscgenerate a scansignal Sc(n) (of), an odd scansignal Sco(n) (of), an even scansignal Sce(n) (of) and a scansignal Sc(n) (of), respectively.

126 2 2 2 2 4 4 2 2 2 2 4 4 3 FIG. 3 FIG. In the second gate driving unit, the odd scanblock Bsco, the even scanblock Bsce, the scanblock Bscand the emission block Bem generate the odd scansignal Sco(n), the even scansignal Sce(n), a scansignal Sc(n) (of) and an emission signal Em(n) (of), respectively.

1 1 1 2 1 4 2 2 2 2 3 1 4 2 2 2 2 3 1 4 3 FIG. 3 FIG. The scan1 signal Sc(n) of the scanblock Bscis supplied to a second transistor T(of) in each subpixel SPto SPof odd and even horizontal pixel lines of the display area DA through the gate line GL. The odd scansignal Sco(n) of the odd scanblock Bsco is supplied to a third transistor T(of) in each subpixel SPto SPof the odd horizontal pixel line of the display area DA through the gate line GL, and the even scansignal Sce(n) of the even scanblock Bsce is supplied to the third transistor Tin each subpixel SPto SPof the even horizontal pixel line of the display area DA through the gate line GL.

3 3 3 3 7 8 1 4 4 4 4 6 1 4 4 5 1 4 3 FIG. 3 FIG. 3 FIG. The scansignal Sc(n) of the scanblock Bscis supplied to seventh and eighth transistors Tand T(of) in each subpixel SPto SPof the odd and even horizontal pixel lines of the display area DA through the gate line GL, and the scansignal Sc(n) of the scan4 block Bscis supplied to a sixth transistor T(of) in each subpixel SPto SPof the odd and even horizontal pixel lines of the display area DA through the gate line GL. The emission signal Em(n) of the emission block Bem is supplied to fourth and fifth transistors Tand T(of) in each subpixel SPto SPof the odd and even horizontal pixel lines of the display area DA through the gate line GL.

124 126 124 126 1 1 2 2 2 2 3 3 4 4 In another implementation, the first and second gate driving unitsandmay have a symmetric structure. For example, each of the first and second gate driving unitsandmay include the scanblock Bsc, the odd scanblock Bsco, the even scanblock Bsce, the scanblock Bsc, the scanblock Bscand the emission block Bem.

3 FIG. 1 4 128 110 1 8 1 8 1 8 In, each of the first to fourth subpixels SPto SPof the display panelof the display deviceaccording to a first implementation of the present disclosure includes first to eighth transistors Tto T, a storage capacitor Cs and a light emitting diode De. At least one of the first to eighth transistors Tto Tmay be an oxide semiconductor thin film transistor, and the others of the first to eighth transistors Tto Tmay be low temperature polycrystalline silicon thin film transistor.

1 3 4 5 7 8 2 6 For example, the first, third, fourth, fifth, seventh and eighth transistors T, T, T, T, Tand Tmay be a p-type low temperature polycrystalline silicon thin film transistor, and the second and sixth transistors Tand Tmay be a n-type oxide semiconductor thin film transistor.

2 6 Further, the second and sixth transistors Tand Tmay be transistors of a double gate type. As described herein, a transistor of a double gate type represents a transistor with two gate electrodes positioned on opposite sides of the semiconductor layer (one above and one below), which are electrically connected to and driven by the same control signal.

1 1 2 1 1 1 3 The first transistor Tas a driving transistor is switched according to a voltage of a first capacitor electrode of the storage capacitor Cs. A gate electrode of the first transistor Tis connected to a second node N, a source electrode of the first transistor Tis connected to a first node N, and a drain electrode of the first transistor Tis connected to a third node N.

2 1 1 2 1 1 2 3 2 2 The second transistor Tas a sampling transistor is switched according to a scansignal Sc(n). A gate electrode (top and bottom gate electrodes) of the second transistor Tis connected to the scansignal Sc(n), a source electrode of the second transistor Tis connected to the third node N, and a drain electrode of the second transistor Tis connected to the second node N.

3 2 2 2 2 3 2 2 2 2 3 1 3 The third transistor Tas a switching transistor is switched according to an odd scansignal Sco(n) or an even scansignal Sce(n). A gate electrode of the third transistor Tis connected to the odd scansignal Sco(n) or the even scansignal Sce(n), a source electrode of the third transistor Tis connected to the first node N, and a drain electrode of the third transistor Tis connected to the data signal Vda.

4 4 4 3 4 4 The fourth transistor Tas an emitting transistor is switched according to an emission signal Em(n). A gate electrode of the fourth transistor Tis connected to the emission signal Em(n), a source electrode of the fourth transistor Tis connected to the third node N, and a drain electrode of the fourth transistor Tis connected to a fourth node N.

5 5 5 3 5 4 The fifth transistor Tas an emitting transistor is switched according to the emission signal Em(n). A gate electrode of the fifth transistor Tis connected to the emission signal Em(n), a source electrode of the fifth transistor Tis connected to the third node N, and a drain electrode of the fifth transistor Tis connected to the fourth node N.

6 4 4 6 4 4 6 5 6 2 The sixth transistor Tas an initializing transistor is switched according to a scansignal Sc(n). A gate electrode (top and bottom electrodes) of the sixth transistor Tis connected to the scansignal Sc(n), a source electrode of the sixth transistor Tis connected to an initial signal (initial voltage) Vin (e.g., about -V), and a drain electrode of the sixth transistor Tis connected to the second node N.

7 3 3 7 3 3 7 4 7 The seventh transistor Tas a reset transistor is switched according to a scansignal Sc(n). A gate electrode of the seventh transistor Tis connected to the scansignal Sc(n), a source electrode of the seventh transistor Tis connected to the fourth node N, and a drain electrode of the seventh transistor Tis connected to an anode reset signal (anode reset voltage) Var.

8 3 3 8 3 3 8 1 8 The eighth transistor Tas a reset transistor is switched according to a scansignal Sc(n). A gate electrode of the eighth transistor Tis connected to the scansignal Sc(n), a source electrode of the eighth transistor Tis connected to the first node N, and a drain electrode of the eighth transistor Tis connected to a stress signal (stress voltage) Vobs.

2 4 The storage capacitor Cs stores the data signal Vda and the threshold voltage Vth. A first capacitor electrode of the storage capacitor Cs is connected to the second node N, and a second capacitor electrode of the storage capacitor Cs is connected to the high level signal Vdd and the source electrode of the fourth transistor T.

4 1 4 The light emitting diode De is connected between the fourth node Nand the low level signal Vss to emit a light of a luminance proportional to a current of the first transistor T. An anode of the light emitting diode De is connected to the fourth node N, and a cathode of the light emitting diode De is connected to the low level signal Vss.

1 3 4 8 1 1 2 6 2 1 2 5 3 5 7 4 The source electrode of the first transistor T, the source electrode of the third transistor T, the drain electrode of the fourth transistor Tand the source electrode of the eighth transistor Tconstitute the first node N, and the gate electrode of the first transistor T, the drain electrode of the second transistor T, the first capacitor electrode of the storage capacitor Cs and the drain electrode of the sixth transistor Tconstitute the second node N. The drain electrode of the first transistor T, the source electrode of the second transistor Tand the source electrode of the fifth transistor Tconstitute the third node N, and the drain electrode of the fifth transistor T, the source electrode of the seventh transistor Tand the anode of the light emitting diode De constitute the fourth node N.

1 4 128 110 A cross-sectional structure of each subpixel SPto SPof the display panelof the display devicewill be illustrated with reference to a drawing.

4 FIG. is a cross-sectional view showing a subpixel of a display panel of a display device according to a first implementation of the present disclosure.

4 FIG. 132 1 4 130 134 132 130 In, a first light shielding patternis disposed in each of the first to fourth subpixels SPto SPon a substrate, and a first buffer layeris disposed on the first light shielding patternover the entire substrate.

132 130 132 The first light shielding patternmay block a light incident from a lower portion of the substrate. For example, the first light shielding patternmay have a single layer or a multiple layer of a metallic material such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu) and an alloy thereof.

134 134 2 The first buffer layermay block a moisture or an oxygen permeating from an exterior. For example, the first buffer layermay have a single layer or a multiple layer of an inorganic insulating material such as silicon oxide (SiO) and silicon nitride (SiNx).

136 134 132 138 136 130 A first semiconductor layeris disposed on the first buffer layercorresponding to the first light shielding pattern, and a first gate insulating layeris disposed on the first semiconductor layerover the entire substrate.

136 136 136 136 136 136 a b c a The first semiconductor layerincludes a first channel regionnot doped with an impurity at a central portion thereof and first source and drain regionsanddoped with an impurity at both side portions of the first channel region. For example, the first semiconductor layermay include a polycrystalline semiconductor material such as polycrystalline silicon

138 2 For example, the first gate insulating layermay have a single layer or a multiple layer of an inorganic insulating material such as silicon oxide (SiO) and silicon nitride (SiNx).

140 138 136 136 142 140 138 144 140 142 130 a A first gate electrodeis disposed on the first gate insulating layercorresponding to the first channel regionof the first semiconductor layer, and a first capacitor electrodeseparated from the first gate electrodeis disposed on the first gate insulating layer. A first interlayer insulating layeris disposed on the first gate electrodeand the first capacitor electrodeover the entire substrate.

140 142 140 142 The first gate electrodeand the first capacitor electrodemay have the same layer and the same material as each other. For example, the first gate electrodeand the first capacitor electrodemay have a single layer or a multiple layer of a metallic material such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu) and an alloy thereof.

144 2 For example, the first interlayer insulating layermay have a single layer or a multiple layer of an inorganic insulating material such as silicon oxide (SiO) and silicon nitride (SiNx).

146 144 142 148 146 144 150 146 148 130 A second capacitor electrodeis disposed on the first interlayer insulating layercorresponding to the first capacitor electrode, and a second light shielding patternseparated from the second capacitor electrodeis disposed on the first interlayer insulating layer. A second buffer layeris disposed on the second capacitor electrodeand the second light shielding patternover the entire substrate.

146 148 146 148 The second capacitor electrodeand the second light shielding patternmay have the same layer and the same material as each other. For example, the second capacitor electrodeand the second light shielding patternmay have a single layer or a multiple layer of a metallic material such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu) and an alloy thereof.

142 144 146 The first capacitor electrode, the first interlayer insulating layerand the second capacitor electrodemay constitute the storage capacitor Cst.

150 150 2 The second buffer layermay block a moisture or an oxygen permeating from an exterior. For example, the second buffer layermay have a single layer or a multiple layer of an inorganic insulating material such as silicon oxide (SiO) and silicon nitride (SiNx).

152 150 148 154 152 130 A second semiconductor layeris disposed on the second buffer layercorresponding to the second light shielding pattern, and a second gate insulating layeris disposed on the second semiconductor layerover the entire substrate.

152 152 152 152 152 152 2 2 The second semiconductor layerincludes a second channel regiona not conductorized at a central portion thereof and second source and drain regionsb andc conductorized at both side portions of the second channel regiona. For example, the second semiconductor layermay include an oxide semiconductor material such as indium gallium zinc oxide (IGZO), zinc oxide (ZnO), tin oxide (SnO), copper oxide (CuO), nickel oxide (NiO), indium tin zinc oxide (ITZO) and indium aluminum zinc oxide (IAZO).

154 2 For example, the second gate insulating layermay have a single layer or a multiple layer of an inorganic insulating material such as silicon oxide (SiO) and silicon nitride (SiNx).

156 154 152 152 158 156 130 a A second gate electrodeis disposed on the second gate insulating layercorresponding to the second channel regionof the second semiconductor layer, and a second interlayer insulating layeris disposed on the second gate electrodeover the entire substrate.

156 For example, the second gate electrodemay have a single layer or a multiple layer of a metallic material such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu) and an alloy thereof.

158 2 For example, the second interlayer insulating layermay have a single layer or a multiple layer of an inorganic insulating material such as silicon oxide (SiO) and silicon nitride (SiNx).

160 162 164 166 158 168 160 162 164 166 130 A first source electrode, a first drain electrode, a second source electrodeand a second drain electrodespaced apart from each other are disposed on the second interlayer insulating layer, and a first planarizing layeris disposed on the first source electrode, the first drain electrode, the second source electrodeand the second drain electrodeover the entire substrate.

160 162 136 136 136 158 154 150 144 138 160 146 158 154 150 b c The first source electrodeand the first drain electrodeare connected to the first source regionand the first drain region, respectively, of the first semiconductor layerthrough contact holes in the second interlayer insulating layer, the second gate insulating layer, the second buffer layer, the first interlayer insulating layerand the first gate insulating layer. The first source electrodeis connected to the second capacitor electrodethrough a contact hole in the second interlayer insulating layer, the second gate insulating layerand the second buffer layer.

164 166 152 152 152 158 154 b c The second source electrodeand the second drain electrodeare connected to the second source regionand the second drain region, respectively, of the second semiconductor layerthrough contact holes in the second interlayer insulating layerand the second gate insulating layer.

160 162 164 166 160 162 164 166 The first source electrode, the first drain electrode, the second source electrodeand the second drain electrodemay have the same layer and the same material as each other. For example, the first source electrode, the first drain electrode, the second source electrodeand the second drain electrodemay have a single layer or a multiple layer of a metallic material such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu) and an alloy thereof.

168 For example, the first planarizing layermay have a single layer or a multiple layer of an organic insulating material such as photoacryl and benzocyclobutene (BCB).

136 140 160 162 4 152 156 164 166 2 The first semiconductor layer, the first gate electrode, the first source electrodeand the first drain electrodemay constitute the fourth transistor T, and the second semiconductor layer, the second gate electrode, the second source electrodeand the second drain electrodemay constitute the second transistor T.

1 3 5 7 8 4 6 2 The first, third, fifth and eighth transistors T, T, T, Tand Tmay have the same cross-sectional structure as the fourth transistor T, and the sixth transistor Tmay have the same cross-sectional structure as the second transistor T.

170 168 160 172 170 130 A connecting electrodeis disposed on the first planarizing layercorresponding to the first source electrode, and a second planarizing layeris disposed on the connecting electrodeover the entire substrate.

170 5 7 168 170 5 7 4 170 2 170 6 2 The connecting electrodeis connected to the drain electrode of the fifth transistor Tor the source electrode of the seventh transistor Tthrough a contact hole in the first planarizing layer. For example, the connecting electrodemay be connected to the drain electrode of the fifth transistor Tor the source electrode of the seventh transistor Thaving the same cross-sectional structure as the fourth transistor T, and it is not limited thereto. For example, the connecting electrodemay be electrically connected to the second transistor T, and the connecting electrodemay be electrically connected to the sixth transistor Thaving the same cross-sectional structure as the second transistor T.

170 For example, the connecting electrodemay have a triple layer of a metallic material such as aluminum (Al) and titanium (Ti).

172 For example, the second planarizing layermay have a single layer or a multiple layer of an organic insulating material such as photoacryl and benzocyclobutene (BCB).

174 172 170 176 174 A first electrodeis disposed on the second planarizing layercorresponding to the connecting electrode, and a bank layeris disposed on the first electrode.

174 170 172 The first electrodeis connected to the connecting electrodethrough a contact hole in the second planarizing layer.

174 For example, the first electrodemay be an anode and may have a single layer or a multiple layer of a transparent conductive material such as indium tin oxide (ITO) and indium zinc oxide (IZO) or an opaque metallic material such as aluminum (Al), silver (Ag), copper (Cu), lead (Pb), molybdenum (Mo), titanium (Ti) and an alloy thereof.

176 174 174 The bank layercovers an edge portion of the first electrodeand has an opening exposing a central portion of the first electrode.

176 For example, the bank layermay have a single layer or a multiple layer of an organic insulating material such as photoacryl and benzocyclobutene (BCB).

178 176 180 178 130 182 180 130 A spaceris disposed on the bank layer, an emitting layeris disposed on the spacerover the entire substrate, and a second electrodeis disposed on the emitting layerover the entire substrate.

178 For example, the spacermay have a single layer or a multiple layer of an organic insulating material such as photoacryl and benzocyclobutene (BCB).

180 174 176 176 176 178 The emitting layercontacts the first electrodeexposed through the opening of the bank layer, a sidewall of the opening of the bank layer, a top surface of the bank layerand side and top surfaces of the spacer.

180 The emitting layermay include a hole assisting layer such as a hole injecting layer and a hole transporting layer, an emitting material layer and an electron assisting layer such as an electron transporting layer and an electron injecting layer.

182 For example, the second electrodemay be a cathode and may have a single layer or a multiple layer of a transparent conductive material such as indium tin oxide (ITO) and indium zinc oxide (IZO) or a half-transmissive or opaque metallic material such as aluminum (Al), silver (Ag), copper (Cu), lead (Pb), magnesium (Mg), molybdenum (Mo), titanium (Ti) and an alloy thereof.

174 180 182 The first electrode, the emitting layerand the second electrodemay constitute the light emitting diode Del.

184 182 130 184 184 184 184 182 a b c An encapsulating layerpreventing a permeation of a moisture is disposed on the second electrodeover the entire substrate. The encapsulating layerincludes a first encapsulating layer, a second encapsulating layerand a third encapsulating layersequentially disposed on the second electrode.

184 184 184 2 b For example, the first encapsulating layera and the third encapsulating layerc may have a single layer or a multiple layer of an inorganic insulating material such as silicon oxide (SiO) and silicon nitride (SiNx), and the second encapsulating layermay include an organic insulating material such as an acryl resin, an epoxy resin, a phenolic resin, a polyamide resin and a polyimide resin.

1 2 6 110 A structure of the first, second and sixth transistors T, Tand Tof each subpixel SP1 to SP4 of the display devicewill be illustrated with reference to drawings.

5 FIG. 6 FIG. 5 FIG. is a plan view showing first, second and sixth transistors of a display device according to a first implementation of the present disclosure, andis a cross-sectional view taken along a line VI-VI of.

5 FIG. 1 4 110 4 4 1 1 136 152 136 152 In, in each of the first to fourth subpixels SPto SPof the display deviceaccording to a first implementation of the present disclosure, a base line BL and the gate line GL transmitting the (n)th scansignal Sc(n) and a base line BL and the gate line GL transmitting the (n)th scansignal Sc(n) are sequentially disposed along a horizontal direction, and the first semiconductor layerand the second semiconductor layerare sequentially disposed along a vertical direction. The first semiconductor layermay be bent along the horizontal direction to be connected to the second semiconductor layer.

4 4 152 6 1 152 2 The base line BL and the gate line GL transmitting the (n)th scansignal Sc(n) cross the second semiconductor layerto form the sixth transistor T, and the base line BL and the gate line transmitting the scan1 signal Sc(n) cross the second semiconductor layerto form the second transistor T.

1 136 2 1 1 6 4 4 The first transistor Tincludes a portion of the first semiconductor layer, the second transistor Tincludes a portion of the base line BL and the gate line GL transmitting the (n)th scansignal Sc(n), and the sixth transistor Tincludes a portion of the base line BL and the gate line GL transmitting the (n)th scansignal Sc(n).

6 FIG. 134 138 144 1 4 130 4 4 1 1 144 In, the first buffer layer, the first gate insulating layerand the first interlayer insulating layerare sequentially disposed in each of the first to fourth subpixels SPto SPon the substrate, and the base line BL transmitting the (n)th scansignal Sc(n) and the base line BL transmitting the (n)th scansignal Sc(n) are spaced apart from each other on the first interlayer insulating layer.

150 4 4 1 1 152 150 The second buffer layeris disposed on the base line BL transmitting the (n)th scansignal Sc(n) and the base line BL transmitting the (n)th scansignal Sc(n), and the second semiconductor layeris disposed on the second buffer layer.

154 152 4 1 1 154 158 4 4 1 The second gate insulating layeris disposed on the second semiconductor layer, and the gate line GL transmitting the (n)th scan4 signal Sc(n) and the gate line GL transmitting the (n)th scansignal Sc(n) are spaced apart from each other on the second gate insulating layer. The second interlayer insulating layeris disposed on the gate line GL transmitting the (n)th scansignal Sc(n) and the gate line GL transmitting the (n)th scan1 signal Sc(n).

4 4 150 152 154 4 6 4 4 4 6 A portion of the base line BL transmitting the (n)th scansignal Sc(n), the second buffer layer, the second semiconductor layer, the second gate insulating layerand a portion of the gate line GL transmitting the (n)th scan4 signal Sc(n) constitute the sixth transistor Tof a double gate type. The portion of the base line BL transmitting the (n)th scan4 signal Sc(n) and the portion of the gate line GL transmitting the (n)th scansignal Sc(n) function as bottom and top gate electrodes, respectively, of the sixth transistor T.

1 150 152 154 1 2 1 1 1 2 A portion of the base line BL transmitting the (n)th scan1 signal Sc(n), the second buffer layer, the second semiconductor layer, the second gate insulating layerand a portion of the gate line GL transmitting the (n)th scan1 signal Sc(n) constitute the second transistor Tof a double gate type. The portion of the base line BL transmitting the (n)th scan1 signal Sc(n) and the portion of the gate line GL transmitting the (n)th scansignal Sc(n) function as bottom and top gate electrodes, respectively, of the second transistor T.

110 Reduction of a width of an initialization period in the display devicewill be illustrated with reference to a drawing.

7 FIG. is a view showing a plurality of signals of one frame of a display device according to a first implementation of the present disclosure.

7 FIG. 1 110 1 1 2 2 2 2 3 3 4 4 In, during a first period TPas a reset period of one frame F of the display deviceaccording to a first implementation of the present disclosure, the (n)th emission signal Em(n), the (n)th scansignal Sc(n), the (n)th odd scansignal Sco(n) and the (n)th even scansignal Sce(n) of the odd and even horizontal pixel lines have a logic high voltage Vh (e.g., a voltage sufficient to place a transistor to which it is applied into an ON state), and the (n)th scansignal Sc(n) and the (n)th scansignal Sc(n) of the odd and even horizontal pixel lines have a logic low voltage Vl (e.g., a voltage sufficient to place a transistor to which it is applied into an OFF state).

1 2 7 8 3 4 5 6 1 3 2 8 1 2 4 7 As a result, the first, second, seventh and eighth transistors T, T, Tand Tare turned on, and the third, fourth, fifth and sixth transistors T, T, Tand Tare turned off. The stress signal Vobs is applied to the first, third and second nodes N, Nand Nthrough the eighth, first and second transistors T, Tand T, and the anode reset signal Var is applied to the fourth node Nthrough the seventh transistor T.

1 1 2 3 4 During the first period TP, the first, second, third and fourth nodes N, N, Nand Nof the odd and even horizontal pixel lines are reset to prevent a hysteresis phenomenon due to a previous frame.

2 1 2 2 2 2 3 3 4 4 During a second period TPas an initialization period, the (n)th emission signal Em(n), the (n)th scan1 signal Sc(n), the (n)th odd scansignal Sco(n), the (n)th even scansignal Sce(n), the (n)th scansignal Sc(n) and the scansignal Sc(n) of the odd and even horizontal pixel lines have a logic high voltage Vh.

1 2 6 3 4 5 7 8 2 3 1 6 2 1 As a result, the first, second and sixth transistors T, Tand Tare turned on, and the third, fourth, fifth, seventh and eighth transistors T, T, T, Tand Tare turned off. The initial signal Vin is applied to the second, third and first nodes N, Nand Nthrough the sixth, second and first transistors T, Tand T.

2 2 3 1 During the second period TP, the second, third and first nodes N, Nand Nof the odd and even horizontal pixel lines are reset to be initialized.

2 1 1 1 As such, the second period TP, which is an initialization period, is included within the period of the logic high voltage Vh of the (n)th scansignal Sc(n), and therefore can have a relatively small first width w.

3 1 1 2 2 3 3 2 2 4 4 During a third period TPas a sampling period, the (n)th emission signal Em(n), the (n)th scansignal Sc(n), the (n)th even scansignal Sce(n) and the (n)th scansignal Sc(n) of the odd and even horizontal pixel lines have a logic high voltage Vh, and the (n)th odd scansignal Sco(n) and the (n)th scansignal Sc(n) of the odd and even horizontal pixel lines have a logic low voltage Vl.

1 2 3 3 4 5 6 7 8 2 3 1 2 As a result, the first and second transistors Tand Tof the odd and even horizontal pixel lines and the third transistor Tof the odd horizontal pixel line are turned on, and the third transistor Tof the even horizontal pixel line and the fourth, fifth, sixth, seventh and eighth transistors T, T, T, Tand Tof the odd and even horizontal pixel lines are turned off. The data signal Vda is applied to the second node Nthrough the third, first and second transistors T, Tand T.

3 2 1 1 During the third period TP, the data signal Vda is applied to the second node Nof the odd horizontal pixel line, and a sum (Vda+Vth) of the data signal Vda and the threshold voltage (Vth) of the first transistor Tis applied to the gate electrode of the first transistor Tand is stored in the storage capacitor Cs.

4 1 1 2 2 3 3 2 2 4 4 During a fourth period TPas a sampling period, the (n)th emission signal Em(n), the (n)th scansignal Sc(n), the (n)th odd scansignal Sco(n) and the (n)th scansignal Sc(n) of the odd and even horizontal pixel lines have a logic high voltage Vh, and the (n)th even scansignal Sce(n) and the (n)th scansignal Sc(n) of the odd and even horizontal pixel lines have a logic low voltage Vl.

1 2 3 3 4 5 6 7 8 2 3 1 2 As a result, the first and second transistors Tand Tof the odd and even horizontal pixel lines and the third transistor Tof the even horizontal pixel line are turned on, and the third transistor Tof the odd horizontal pixel line and the fourth, fifth, sixth, seventh and eighth transistors T, T, T, Tand Tof the odd and even horizontal pixel lines are turned off. The data signal Vda is applied to the second node Nthrough the third, first and second transistors T, Tand T.

4 2 1 1 During the fourth period TP, the data signal Vda is applied to the second node Nof the even horizontal pixel line, and a sum (Vda+Vth) of the data signal Vda and the threshold voltage (Vth) of the first transistor Tis applied to the gate electrode of the first transistor Tand is stored in the storage capacitor Cs.

5 2 2 2 2 1 1 3 3 4 During a fifth period TPas a reset period, the (n)th emission signal Em(n), the (n)th odd scansignal Sco(n) and the (n)th even scansignal Sce(n) of the odd and even horizontal pixel lines have a logic high voltage Vh, and the (n)th scansignal Sc(n), the (n)th scansignal Sc(n) and the (n)th scan4 signal Sc(n) of the odd and even horizontal pixel lines have a logic low voltage Vl.

1 7 8 2 3 4 5 6 1 3 8 1 4 7 As a result, the first, seventh and eighth transistors T, Tand Tof the odd and even horizontal pixel lines are turned on, and the second, third, fourth, fifth and sixth transistors T, T, T, Tand Tof the odd and even horizontal pixel lines are turned off. The stress signal Vobs is applied to the first and third nodes Nand Nthrough the eighth and first transistors Tand T, and the anode reset signal Var is applied to the fourth node Nthrough the seventh transistor T.

5 1 3 4 During the fifth period TP, the first, third and fourth nodes N, Nand Nof the odd and even horizontal pixel lines are reset to prevent a hysteresis phenomenon due to a previous timing.

6 2 2 2 2 3 3 1 1 4 4 During a sixth period TPas an emission period, the (n)th odd scansignal Sco(n), the (n)th even scansignal Sce(n) and the (n)th scansignal Sc(n) of the odd and even horizontal pixel lines have a logic high voltage Vh, and the (n)th emission signal Em(n), the scansignal Sc(n) and the (n)th scansignal Sc(n) of the odd and even horizontal pixel lines have a logic low voltage Vl.

1 4 5 2 3 6 7 8 4 4 1 5 1 1 As a result, the first, fourth and fifth transistors T, Tand Tof the odd and even horizontal pixel lines are turned on, and the second, third, sixth, seventh and eighth transistors T, T, T, Tand Tof the odd and even horizontal pixel lines are turned off. The high level signal Vdd is applied to the fourth node Nthrough the fourth, first and fifth transistors T, Tand T. The threshold voltage (Vth) is compensated in the turned-on first transistor T, and a current corresponding to the data signal Vda flows through the turned-on first transistor T.

6 During the sixth period TP, the light emitting diode De emits a light corresponding to the data signal Vda of the present frame.

1 4 4 110 2 4 4 2 2 A first width wof the period of the logic high voltage Vh of the (n)th scansignal Sc(n) of the display deviceaccording to a first implementation of the present disclosure is smaller than a second width wof a period of the logic high voltage Vh of the (n)th scansignal Sc(n) of a display device according to a comparison example. As a result, the second node Nis charged to the same voltage even when the second transistor Tof a sampling transistor has a different mobility.

8 FIG.A 8 FIG.B is a view showing a second node voltage of a display device according to a comparison example, andis a view showing a second node voltage of a display device according to a first implementation of the present disclosure.

8 FIG.A 4 4 2 6 1 2 6 2 2 6 2 2 2 4 4 In, the period of the logic high voltage Vh of the (n)th scansignal Sc(n) of the display device according to a comparison example has a relatively larger second width w, and therefore the sixth transistor Tis turned on during a relatively long period. As a result, in both of a case G(solid curve) where the second and sixth transistors Tand Thave a relatively high mobility and a case G(dashed curve) where the second and sixth transistors Tand Thave a relatively low mobility, a second node voltage Vnof the second node Nis saturated during the width wperiod of the logic high voltage Vh of the (n)th scansignal Sc(n) to be charged to the initial signal Vin.

3 4 2 2 2 2 3 1 2 6 2 1 2 2 6 2 2 1 Next, during the third and fourth periods TPand TPof the logic low voltage Vl of the (n)th odd scansignal Sco(n) and the (n)th even scansignal Sce(n), the third transistor Tis turned on. In the case G(where the second and sixth transistors Tand Thave relatively high mobility), due to the relatively high charging speed, the second node voltage Vn(solid curve) quickly rises to a first voltage Vhigher than the initial signal Vin. However, in a case G(where the second and sixth transistors Tand Thave relatively low mobility), due to the relatively low charging speed, the second node voltage Vn(dashed curve) more slowly rises a second voltage Vthat is lower than the first voltage V.

3 4 2 2 6 Accordingly, in the display device according to a comparison example, during the third and fourth periods TPand TPof a sampling period, the threshold voltage (Vth) stored in the storage capacitor Cs connected to the second node Ncan have different magnitudes due to a mobility deviation of the second and sixth transistors Tand T. This results in a threshold voltage difference across different regions of the display panel. Therefore, deterioration such as a local luminance deviation occurs and a display quality is reduced.

8 FIG.B 2 4 110 1 6 1 2 6 2 2 6 2 2 1 4 4 In, by contrast, the second period TPof the logic high voltage Vh of the (n)th scan4 signal Sc(n) of the display deviceaccording to a first implementation of the present disclosure has a relatively small first width w, and therefore the sixth transistor Tis turned on during a relatively short period. As explained below, the result is that in both of the case G(where the second and sixth transistors Tand Thave relatively high mobility) and the case G(where the second and sixth transistors Tand Thave relatively low mobility), the second node voltage Vnof the second node Nis not saturated during the smaller first width wperiod of the logic high voltage Vh of the (n)th scansignal Sc(n).

8 FIG.B 1 2 6 2 2 3 2 2 2 4 4 2 2 6 2 2 4 3 2 2 2 4 4 Specifically, as shown in, in the case G(where the second and sixth transistors Tand Thave relatively high mobility), despite the relatively high charging speed, the smaller first width w1 can ensure that the second node voltage Vn(solid curve) of the second node Nis only charged to a third voltage Vhigher than the initial signal Vin. Therefore, the second node voltage Vnof the second node Nis not saturated during the second period TPof the logic high voltage Vh of the (n)th scansignal Sc(n). Also, in the case G(where the second and sixth transistors Tand Thave relatively low mobility), the relatively low charging speed ensures that the second node voltage Vn(dashed curve) of the second node Nis charged to a fourth voltage Vhigher than the third voltage V(and also higher than the initial signal Vin). Therefore, again, the second node voltage Vnof the second node Nis not saturated during the second period TPof the logic high voltage Vh of the (n)th scansignal Sc(n).

2 3 4 2 2 2 2 1 2 6 2 3 5 2 2 6 2 4 5 2 6 1 2 2 2 5 The resulting benefits of the above-described non-saturation in the second period TPare shown next, namely during the third and fourth periods TPand TP(in which the (n)th odd scansignal Sco(n) and the (n)th even scansignal Sce(n) are each a logic low voltage Vl). Specifically, in the case G(where the second and sixth transistors Tand Thave relatively high mobility) the second node voltage Vn(solid curve) rises quickly from the third voltage Vto a fifth voltage Vdue to a relatively high charging speed. In the case G(where the second and sixth transistors Tand Thave relatively low mobility) the second node voltage Vn(dashed curve) rises more slowly from the fourth voltage Vto the same fifth voltage Vdue to a relatively low charging speed. Therefore, regardless of a mobility deviation of the second and sixth transistors Tand T(e.g., regardless of case Gor G), the second node voltage Vnof second node Ncan have the same magnitude (fifth voltage V).

110 3 4 2 2 6 128 Accordingly, in the display deviceaccording to a first implementation of the present disclosure, during the third and fourth periods TPand TPof a sampling period, the threshold voltage (Vth) stored in the storage capacitor Cs connected to the second node Nhas the same magnitude regardless of a mobility deviation of the second and sixth transistors Tand T. This can help reduce a threshold voltage difference across different regions of the display panel. Therefore, deterioration such as a local luminance deviation is prevented and a display quality is improved.

110 2 2 2 6 1 2 2 6 In the display deviceaccording to a first implementation of the present disclosure, during the second period TPwhich is an initialization period, the second node voltage Vnis not saturated regardless of the mobility deviation by regions of the second and sixth transistors Tand T. This can be achieved by determining the first width was a relatively small value, during which the second node voltage Vnis charged to different voltages according to the mobility by regions of the second and sixth transistors Tand T.

1 2 6 10 2 2 6 2 2 6 In addition or as an alternative to using a smaller first width, in some implementations, non-saturation can also be ensured by using a lower value of the initial signal Vin. For example, during the second period TP, by determining the initial signal Vin as a relatively low voltage (e.g., about -V to about -V), the second node voltage Vnmay be charged to different voltages according to the mobility by regions of the second and sixth transistors Tand T. As such, the second node voltage Vnmay not be saturated regardless of the mobility deviation by regions of the second and sixth transistors Tand T.

1 1 2 2 In some implementations, the voltage of the scansignal Sc(n) may increase due to a coupling of the scansignal Sc(n).

9 FIG. is a circuit diagram showing a subpixel of a display device according to a second implementation of the present disclosure. Detailed description of parts that are the same as those of the first implementation will be omitted.

9 FIG. 1 8 1 8 1 8 In, each of first to fourth subpixels SP1 to SP4 of a display device according to a second implementation of the present disclosure includes first to eighth transistors Tto T, a storage capacitor Cs, a coupling capacitor Cc and a light emitting diode De. At least one of the first to eighth transistors Tto Tmay be an oxide semiconductor thin film transistor, and the others of the first to eighth transistors Tto Tmay be low temperature polycrystalline silicon thin film transistor.

1 8 1 1 2 2 1 1 1 2 1 A connection structure and an operation of the first to eighth transistors Tto T, the storage capacitor Cs and the light emitting diode De of the second implementation are the same as those of the first implementation except that the coupling capacitor Cc is connected between a scansignal Sc(n) and an odd scansignal Sco(n-) or between a scansignal Sc(n) and an even scansignal Sc2e(n-).

1 2 The coupling capacitor Cc may be formed due to an overlapping of an output line of a scanblock and a carry line in an even scanblock of a first gate driving unit.

10 FIG. 11 FIG. is a view showing a first gate driving unit and a display panel of a display device according to a second implementation of the present disclosure, andis a cross-sectional view showing an output line and a carry line of a first gate driving unit of a display device according to a second implementation of the present disclosure. Detailed description of parts that are the same as those of the first implementation will be omitted.

10 FIG. 124 128 1 1 1 1 1 1 2 2 1 2 2 1 2 1 2 2 1 3 3 1 3 3 In, a first gate driving unitin a non-display area NDA of a display panelof a display device according to a second implementation of the present disclosure includes an (n-)th scan1 block Bsc(n-), an (n)th scanblock Bsc(n), an (n-)th odd scanblock Bsco(n-), an (n)th odd scanblock Bsco(n), an (n-)th even scanblock Bsc2e(n-), an (n)th even scanblock Bsce(n), an (n-)th scanblock Bsc(n-) and an (n)th scanblock Bsc(n).

1 1 1 1 1 1 1 1 1 1 1 1 1 1 The (n-)th scan1 block Bsc(n-1) generates an (n-)th scansignal Sc(n-) and supplies the (n-)th scansignal Sc(n-) to odd and even horizontal pixel lines HLo(n-) and HLe(n-) of an (n-)th horizontal pixel line pair HLP(n-) in a display area DA through an output line OL.

1 1 1 1 1 1 1 The (n)th scanblock Bsc(n) generates an (n)th scan1 signal Sc(n) and supplies the (n)th scansignal Sc(n) to the odd and even horizontal pixel lines HLo(n-) and HLe(n-) of an (n)th horizontal pixel line pair HLP(n) in the display area DA through an output line OL.

1 2 2 1 1 2 2 1 1 2 2 1 1 1 1 1 2 2 1 1 2 2 1 The (n-)th odd scanblock Bsco(n-) generates an (n-)th odd scansignal Sco(n-), supplies the (n-)th odd scansignal Sco(n-) to the odd horizontal pixel line HLo(n-) of the (n-)th horizontal pixel line pair HLP(n-) in the display area DA through an output line OL, and supplies the (n-)th odd scansignal Sco(n-) to an (n-)th even scanblock Bsce(n-) of a next stage in the non-display area NDA through a carry line CL.

1 2 2 1 1 2 2 1 1 2 2 1 1 1 1 1 2 2 1 2 2 The (n-)th even scanblock Bsce(n-) generates an (n-)th even scansignal Sce(n-), supplies the (n-)th even scansignal Sce(n-) to the even horizontal pixel line HLe(n-) of the (n-)th horizontal pixel line pair HLP(n-) in the display area DA through an output line OL, and supplies the (n-)th even scansignal Sce(n-) to an (n)th odd scanblock Bsco(n) of a next stage in the non-display area NDA through a carry line CL.

2 2 2 2 2 2 2 2 2 2 The (n)th odd scanblock Bsco(n) generates an (n)th odd scansignal Sco(n), supplies the (n)th odd scansignal Sco(n) to the odd horizontal pixel line HLo(n) of the (n)th horizontal pixel line pair HLP(n) in the display area DA through an output line OL, and supplies the (n)th odd scansignal Sco(n) to an (n)th even scanblock Bsce(n) of a next stage in the non-display area NDA through a carry line CL.

2 2 2 2 2 2 2 2 1 2 2 1 The (n)th even scanblock Bsce(n) generates an (n)th even scansignal Sce(n), supplies the (n)th even scansignal Sce(n) to the even horizontal pixel line HLe(n) of the (n)th horizontal pixel line pair HLP(n) in the display area DA through an output line OL, and supplies the (n)th even scansignal Sce(n) to an (n+)th odd scanblock Bsco(n+) of a next stage in the non-display area NDA through a carry line CL.

1 2 2 1 2 1 1 1 1 1 The carry line CL of the (n-)th even scanblock Bsce(n-) transmitting the (n-1)th even scan2 signal Sce(n-) and the output line OL of the (n)th scanblock Bsc(n) transmitting the (n)th scansignal Sc(n) overlap each other in the non-display area NDA to form the coupling capacitor Cc.

1 1 1 2 2 1 1 1 1 2 2 1 10 FIG. Although the output line OL of the (n)th scanblock Bsc(n) can overlap the carry line CL of the (n-)th even scanblock Bsce(n-) in a second implementation of, the output line OL of the (n)th scanblock Bsc(n) may overlap the carry line CL of the (n-)th odd scanblock Bsco(n-) in another implementation.

11 FIG. 134 138 144 130 1 2 2 1 144 In, a first buffer layer, a first gate insulating layerand a first interlayer insulating layerare sequentially disposed in the non-display area NDA on a substrate, and the carry line CL transmitting the (n-)th even scansignal Sce(n-) is disposed on the first interlayer insulating layer.

150 154 1 2 2 1 1 1 154 158 1 1 A second buffer layerand a second gate insulating layerare sequentially disposed on the carry line CL transmitting the (n-)th even scansignal Sce(n-), the output line OL transmitting the (n)th scansignal Sc(n) is disposed on the second gate insulating layer, and a second interlayer insulating layeris disposed on the output line OL transmitting the (n)th scansignal Sc(n).

1 1 1 2 2 1 154 150 The output line transmitting the (n)th scansignal Sc(n) overlaps the carry line CL transmitting the (n-)th even scansignal Sce(n-) with the second gate insulating layerand the second buffer layerinterposed therebetween to form the coupling capacitor Cc.

1 1 1 2 2 1 A voltage of the (n)th scansignal Sc(n) increases due to a coupling of the (n-)th even scansignal Sce(n-) through the coupling capacitor Cc.

12 FIG. 1 2 is a view showing a scansignal and a scansignal of a display device according to a second implementation of the present disclosure. Detailed description of parts that are the same as those of the first implementation will be omitted.

12 FIG. 1 1 4 1 2 2 1 1 1 1 2 2 1 1 1 1 2 2 1 In, a period of a logic high voltage Vh of the (n)th scansignal Sc(n) overlaps a fourth period TPof a logic low voltage Vl of the (n-)th even scansignal Sce(n-). The period of a logic high voltage Vh of the (n)th scansignal Sc(n) has a voltage variation at a falling timing FT and a rising timing RT of the (n-)th even scansignal Sce(n-) through the coupling capacitor Cc between the output line OL of the (n)th scansignal Sc(n) and the carry line CL of the (n-)th even scansignal Sce(n-).

1 1 1 2 1 1 2 2 1 6 2 2 The voltage of the (n)th scansignal Sc(n) decreases from the logic high voltage Vh at the falling timing FT of the (n-)th even scan2 signal Sce(n-) and increases again at the rising timing RT of the (n-)th even scansignal Sce(n-) to become a sixth voltage Vgreater than the logic high voltage Vh. Since a relatively high voltage is applied to the gate electrode of the second transistor T, an on current of the second transistor Tincreases and a mobility of the second transistor is compensated.

1 2 1 2 2 124 126 In the display device according to a second implementation of the present disclosure, the voltage of the scansignal increases and the on current of the second transistor Tof a sampling transistor increases by forming the coupling capacitor Cc between the output line OL of the scan1 signal Scand the carry line CL of the scansignal Scin the first and second gate driving unitsand. As a result, a threshold voltage difference by regions in the display panel is minimized, deterioration such as a local luminance deviation is prevented, and a display quality is improved.

In another implementation, a coupling capacitor may be disposed in a subpixel.

13 FIG. is a view showing a subpixel of a display device according to a third implementation of the present disclosure. Detailed description of parts that are the same as those of the first and second implementations will be omitted.

13 FIG. 1 4 1 8 1 8 1 8 In, each of first to fourth subpixels SPto SPof a display device according to a third implementation of the present disclosure includes first to eighth transistors Tto T, a storage capacitor Cs, a coupling capacitor Cc and a light emitting diode De. At least one of the first to eighth transistors Tto Tmay be an oxide semiconductor thin film transistor, and the others of the first to eighth transistors Tto Tmay be low temperature polycrystalline silicon thin film transistor.

1 8 6 1 2 1 1 1 2 2 1 A connection structure and an operation of the first to eighth transistors Tto T, the storage capacitor Cs and the light emitting diode De of the third implementation are the same as those of the first implementation except that the sixth transistor Thas a single gate type where a gate electrode is disposed on a semiconductor layer to form a channel region at an upper portion of the semiconductor layer and the coupling capacitor Cc is connected between a scan1 signal Sc(n) and an odd scan2 signal Sco(n-) or between a scansignal Sc(n) and an even scansignal Sce(n-).

6 2 4 4 2 When the sixth transistor Thas a single gate type, the channel region is formed only at the upper portion of the semiconductor layer, and the on current decreases. As a result, during a second period TPof a logic high voltage Vh of an (n)th scansignal Sc(n), a second node Nis charged up due to an initial signal Vin with a relatively low charging speed.

2 2 2 2 6 3 4 Similarly to the first implementation, a second node voltage Vnof the second node Nis not saturated and is charged to a voltage higher than the initial voltage Vin, and a threshold voltage (Vth) stored in the storage capacitor Cs connected to the second node Nhas the same magnitude regardless of a mobility deviation of the second and sixth transistors Tand Tby regions during third and fourth periods TPand TP. Accordingly, a threshold voltage difference by regions in the display panel is minimized, deterioration such as a local luminance deviation is prevented, and a display quality is improved.

1 1 2 2 1 4 The coupling capacitor Cc may be formed due to an overlapping of a gate line GL of a scansignal Scand a base line BL of a scansignal Scin each subpixel SPto SP.

14 FIG. 15 FIG. 14 FIG. 16 FIG. 14 FIG. is a plan view showing first, second and sixth transistors of a display device according to a third implementation of the present disclosure,is a cross-sectional view taken along a line XV-XV of, andis a cross-sectional view taken along a line XVI-XVI of. Detailed description of parts that are the same as those of the first and second implementations will be omitted.

14 FIG. 1 4 1 2 2 1 1 2 2 1 4 4 1 1 136 152 136 152 In, in each of the first to fourth subpixels SPto SPof the display device according to a third implementation of the present disclosure, a base line BL transmitting the (n-)th odd scansignal Sco(n-) or the (n-)th even scansignal Sce(n-), a gate line GL transmitting the (n)th scansignal Sc(n), and base and gate lines BL and GL transmitting the (n)th scansignal Sc(n) are sequentially disposed along a horizontal direction, and a first semiconductor layerand a second semiconductor layerare sequentially disposed along a vertical direction. The first semiconductor layermay be bent along the horizontal direction to be connected to the second semiconductor layer.

4 4 152 6 1 1 152 2 The gate line GL transmitting the (n)th scansignal Sc(n) cross the second semiconductor layerto form the sixth transistor T, and the base and gate lines BL and GL transmitting the (n)th scansignal Sc(n) cross the second semiconductor layerto form the second transistor T.

1 136 2 1 1 6 4 4 The first transistor Tincludes a portion of the first semiconductor layer, the second transistor Tincludes a portion of the base and gate lines BL and GL transmitting the (n)th scansignal Sc(n), and the sixth transistor Tincludes a portion of the gate line GL transmitting the (n)th scansignal Sc(n).

1 2 2 1 1 2 2 1 1 1 2 1 2 2 1 1 1 The base line BL transmitting the (n-)th odd scansignal Sco(n-) or the (n-)th even scansignal Sce(n-) is bent along the vertical direction to form a bent portion BP, and the gate line GL transmitting the (n)th scansignal Sc(n) protrudes along the vertical direction to form a protruding portion PP. The bent portion BP of the base line BL of the (n-1)th odd scansignal Sc2o(n-) or the (n-1)th even scansignal Sce(n-) and the protruding portion PP of the gate line GL of the (n)th scansignal Sc(n) overlap each other to form the coupling capacitor Cc.

15 FIG. 134 138 144 1 4 130 1 2 2 1 1 2 2 1 4 4 144 In, the first buffer layer, the first gate insulating layerand the first interlayer insulating layerare sequentially disposed in each of the first to fourth subpixels SPto SPof the display area DA on the substrate, and the base line BL transmitting the (n-)th odd scansignal Sco(n-) or the (n-)th even scansignal Sce(n-) and the base line BL transmitting the (n)th scansignal Sc(n) are spaced apart from each other on the first interlayer insulating layer.

150 154 1 2 2 1 1 2 2 1 1 1 The second buffer layerand the second gate insulating layerare sequentially disposed on the base line BL transmitting the (n-)th odd scansignal Sco(n-) or the (n-)th even scansignal Sce(n-) and the base line BL transmitting the (n)th scansignal Sc(n).

4 4 1 1 154 158 4 4 1 1 The gate line GL transmitting the (n)th scansignal Sc(n) and the gate line GL transmitting the (n)th scansignal Sc(n) are spaced apart from each other on the second gate insulating layer, and the second interlayer insulating layeris disposed on the gate line GL transmitting the (n)th scansignal Sc(n) and the gate line GL transmitting the (n)th scansignal Sc(n).

1 1 1 2 2 1 2 2 1 154 150 1 1 1 2 2 1 2 2 1 The protruding portion PP of the gate line GL transmitting the (n)th scansignal Sc(n) overlaps the bent portion BP of the base line BL transmitting the (n-)th odd scansignal Sco(n-1) or the (n-)th even scansignal Sce(n-) with the second gate insulating layerand the second buffer layerinterposed therebetween to form the coupling capacitor Cc. A voltage of the (n)th scansignal Sc(n) increases due to a coupling of the (n-)th odd scansignal Sco(n-1) or the (n-)th even scansignal Sce(n-) through the coupling capacitor Cc.

16 FIG. 134 138 144 1 4 130 1 2 2 1 1 2 2 1 1 1 144 In, the first buffer layer, the first gate insulating layerand the first interlayer insulating layerare sequentially disposed in each of the first to fourth subpixels SPto SPof the display area DA on the substrate, and the base line BL transmitting the (n-)th odd scansignal Sco(n-) or the (n-)th even scansignal Sce(n-) and the base line BL transmitting the (n)th scansignal Sc(n) are spaced apart from each other on the first interlayer insulating layer.

150 1 2 2 1 1 2 2 1 1 1 152 150 The second buffer layeris disposed on the base line BL transmitting the (n-)th odd scansignal Sco(n-) or the (n-)th even scansignal Sce(n-) and the base line BL transmitting the (n)th scansignal Sc(n), and the second semiconductor layeris disposed on the second buffer layer.

154 152 4 4 1 1 154 158 4 4 1 The second gate insulating layeris disposed on the second semiconductor layer, the gate line GL transmitting the (n)th scansignal Sc(n) and the gate line GL transmitting the (n)th scansignal Sc(n) are spaced apart from each other on the second gate insulating layer, and the second interlayer insulating layeris disposed on the gate line GL transmitting the (n)th scansignal Sc(n) and the gate line GL transmitting the (n)th scan1 signal Sc(n).

152 154 4 4 6 4 4 6 The second semiconductor layer, the second gate insulating layerand a portion of the gate line GL transmitting the scansignal Sc(n) constitute the sixth transistor Tof a single gate type. The portion of the gate line GL transmitting the scansignal Sc(n) functions as a top gate electrode of the sixth transistor T.

1 1 150 152 154 1 1 2 1 1 1 2 A portion of the base line BL transmitting the (n)th scansignal Sc(n), the second buffer layer, the second semiconductor layer, the second gate insulating layerand a portion of the gate line GL transmitting the (n)th scansignal Sc(n) constitute the second transistor Tof a double gate type. The portion of the base line BL transmitting the (n)th scan1 signal Sc(n) and the portion of the gate line GL transmitting the (n)th scansignal Sc(n) function as bottom and top gate electrodes, respectively, of the second transistor T.

1 2 1 1 2 2 1 4 In the display device according to a third implementation of the present disclosure, the voltage of the scansignal increases and the on current of the second transistor Tof a sampling transistor increases by forming the coupling capacitor Cc between the gate line GL of the scansignal Scand the base line BL of the scansignal Scin each of the first to fourth subpixels SPto SP. As a result, a threshold voltage difference by regions in the display panel is minimized, deterioration such as a local luminance deviation is prevented, and a display quality is improved.

It will be apparent to those skilled in the art that various modifications and variation may be made in the present disclosure without departing from the scope of the disclosure. Thus, it is intended that the present disclosure cover the modifications and variations of this disclosure provided they come within the scope of the appended claims and their equivalents.