Semiconductor Memory Device and Manufacturing Method Therefor

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2024-229452, filed Dec. 25, 2024, the entire contents of which are incorporated herein by reference.

Embodiments described herein relate generally to a semiconductor memory device and a manufacturing method therefor.

A semiconductor memory device such as a NAND flash memory has a memory cell array in which a plurality of memory cells are disposed three-dimensionally. Such a memory cell array includes a plurality of electrode films functioning as word lines and a plurality of insulating films. These electrode films and insulating films are alternately stacked. Each electrode film is formed by replacing a sacrificial film from a stacked body of a plurality of sacrificial films and a plurality of insulating films with a conductive material. When the sacrificial film is removed in such a replacement process, the stacked body can bend under its own weight.

Embodiments provide a semiconductor memory device and a manufacturing method therefor which are capable of curb depression of a stacked body when a sacrificial film is replaced with a conductive material from a stacked body of a plurality of sacrificial films and a plurality of insulating films.

In general, according to one embodiment, a semiconductor memory device comprises: a plurality of first electrode films arranged in a first direction; a plurality of first insulating films arranged in the first direction; a plurality of second insulating films arranged in the first direction; a first stacked region in which the first electrode films and the first insulating films are alternately stacked in the first direction; a second stacked region disposed adjacent to the first stacked region in a second direction that is perpendicular to the first direction and in which the first insulating films and the second insulating films are alternately stacked in the first direction; a third stacked structure extending from the first stacked structure in the second direction and in which the first electrode films and the first insulating films are alternately stacked in the first direction; a first columnar body including a semiconductor layer that penetrates the first electrode films and the first insulating films in the first stacked region and forms a plurality of memory cells at intersections with the first electrode films; a plurality of contacts extending in the first direction in the second stacked region, each of the contacts reaching, in the first direction, a level of a corresponding one of the first electrode films; and a plurality of connection layers electrically connecting the contacts and the corresponding first electrode films.

Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. The embodiments described below do not limit the present disclosure. In the specification and the drawings, the same elements are given the same reference numerals.

1 FIG. is a cross-sectional view of a semiconductor memory device according to a first embodiment.

1 2 The semiconductor memory device of the present embodiment is, for example, a NAND flash memory having a memory cell array in which memory cells are arranged three-dimensionally. The semiconductor memory device of the present embodiment is manufactured by bonding an array wafer including an array chipand a circuit wafer including a circuit chipat a bonding surface S.

1 11 12 11 12 The array chipincludes a memory cell arrayincluding a plurality of memory cells and an interlayer insulating filmbelow the memory cell array. The interlayer insulating filmis, for example, a stacked body including a silicon oxide film (for example, a SiO2 film) containing silicon and oxygen and other insulating films.

2 1 2 13 12 14 13 13 14 The circuit chipis provided below the array chip. The circuit chipincludes an interlayer insulating filmbelow the interlayer insulating film, and a substratebelow the interlayer insulating film. The interlayer insulating filmis, for example, a stacked body including a silicon oxide film (for example, a SiO2 film) containing silicon and oxygen and other insulating films. The substrateis, for example, a semiconductor substrate such as a Si (silicon) substrate.

1 FIG. 14 14 shows an X-direction and a Y-direction parallel to the surface of the substrateand perpendicular to each other, and a Z-direction perpendicular to the surface of the substrate. The X-direction, the Y-direction, and the Z-direction intersect each other. In this specification, a +Z-direction is defined as upward, and a −Z-direction is defined as downward. The −Z-direction may or may not coincide with the direction of gravity.

1 11 1 11 23 The array chipincludes a plurality of word lines WL, a source-side selected line SGS, and a drain-side selected line SGD as a plurality of electrode films in the memory cell array. The source-side selected line SGS is disposed above these word lines WL, and the drain-side selected line SGD is disposed below these word lines WL. The array chipincludes a cell region Rmc in which the memory cell arrayis provided, and a word line hook-up region (hereinafter also referred to as a WLHU region) Rwlhu in which word line contactsare provided.

23 24 23 Each of the word lines WL is connected to each of the plurality of word line contacts, and is electrically connected to each of a plurality of word line wiringsvia the plurality of word line contacts(hereinafter, also referred to as word line contacts WLC).

25 11 A plurality of columnar bodies CL that penetrate the plurality of word lines WL, the source-side selected lines SGS, and the drain-side selected lines SGD are electrically connected to bit lines BL through via plugs, and are also electrically connected to source lines SL. The columnar bodies CL penetrate the stacked body of the memory cell arrayin the Z-direction, and form a plurality of memory cells MC at the intersections with the word lines WL. The source lines SL are provided above the source-side selected lines SGS, and the bit lines BL are provided below the drain-side selected lines SGD.

1 FIG. Only the electrode film in the uppermost layer inmay be the source-side selected line SGS, but the plurality of electrode films on the uppermost side may be the source-side selected lines SGS. The number of electrode films serving as the source-side selected lines SGS may be any number. Similarly, only the electrode film at the lowermost position may be the drain-side selected line SGD, but a plurality of electrode films on the lowermost side may be the drain-side selected lines SGD. The number of electrode films serving as the drain-side selected lines SGD may be any number.

1 41 47 42 45 46 43 44 48 The array chipfurther includes metal padsand, via plugs,, and, wiring layersand, and a passivation insulating film.

41 37 2 41 2 11 41 37 11 42 41 43 42 44 43 44 45 44 46 45 The metal padis bonded to a metal padof the circuit chip. The metal padis, for example, a metal layer containing Cu (copper). A complementary metal oxide semiconductor (CMOS) circuit of the circuit chipis electrically connected to the memory cell arrayvia the metal padsand, and the like, and controls the operation of the memory cell array. The via plugis provided on the metal pad. The wiring layeris provided on the via plugand includes a plurality of wirings. The wiring layeris provided on the wiring layerand includes a plurality of wirings. The bit line BL is formed in the same layer as the wiring layer. The via plugis provided on the wiring layer. The via plugis provided on the via plug.

47 46 12 47 48 47 12 48 47 47 The metal padis provided on the via plugand the interlayer insulating film. The metal padis, for example, a metal layer containing Al (aluminum) and functions as an external connection pad (for example, a bonding pad). The passivation insulating filmis provided on the metal padand the interlayer insulating film. The passivation insulating filmis, for example, a stacked body including a silicon oxide film (for example, a SiO2 film) containing silicon and oxygen and a silicon nitride film (for example, a SiN film) containing silicon and nitrogen, and exposes a portion of the upper surface of the metal pad. The metal padcan be connected to a mounting substrate or other devices by a bonding wiring, a solder ball, a metal bump, or the like.

2 31 32 33 34 35 36 37 The circuit chipincludes a transistor, a contact plug, a wiring layer, a wiring layer, a wiring layer, a via plug, and the metal pad.

31 31 14 31 31 14 14 a b a The transistorincludes a gate insulating filmprovided on the substrate, a gate electrodeprovided on the gate insulating film, a source region (not shown) provided in the substrate, and a drain region (not shown) provided in the substrate.

32 31 31 33 32 34 33 35 34 36 35 37 36 37 2 1 31 1 37 b The contact plugis provided on the gate electrode, the source region, and the drain region of the transistor. The wiring layeris provided on the contact plugand includes a plurality of wirings. The wiring layeris provided on the wiring layerand includes a plurality of wirings. The wiring layeris provided on the wiring layerand includes a plurality of wirings. The via plugis provided on the wiring layer. The metal padis provided on the via plug. The metal padis, for example, a metal layer including a Cu layer. The circuit chipincludes a CMOS circuit that controls the operation of the array chip. The CMOS circuit includes the transistorsand the like, and is electrically connected to the array chipvia the metal pad.

2 FIG. 2 FIG. 11 is an enlarged cross-sectional view of the memory cell arrayaccording to the first embodiment.shows one columnar body CL.

11 51 51 51 51 51 51 51 51 51 51 a b a a a a a b b 2 FIG. The memory cell arrayincludes a stacked bodyincluding electrode filmsand insulating filmsstacked alternately in the Z-direction. The electrode filmfunctions as, for example, the word line WL, the source-side selected line SGS, or the drain-side selected line SGD. In, the electrode filmat the uppermost position functions as the source-side selected line SGS, the electrode filmat the lowermost position functions as the drain-side selected line SGD, and the other electrode filmsfunction as the word lines WL. The word line WL functions as a gate electrode of the memory cell MC. The electrode filmis, for example, a metal layer containing W, or Mo(tungsten, or molybdenum). The insulating filmis, for example, a silicon oxide film (for example, a SiO2 film) containing silicon and oxygen. The insulating filmis an example of a first insulating film.

51 51 52 53 52 54 53 55 54 56 55 The columnar body CL penetrates the stacked bodyin the Z-direction and has a columnar shape. The columnar body CL is provided in a memory hole MH that penetrates the stacked bodyin the Z-direction. The columnar body CL includes a block insulating filmprovided on the inner surface of the memory hole MH, a charge storage layerprovided on the inner surface of the block insulating film, a tunnel insulating filmprovided on the inner surface of the charge storage layer, a channel semiconductor layerprovided on the inner surface of the tunnel insulating film, and a core insulating filmprovided on the inner surface of the channel semiconductor layer. The columnar body CL forms the memory cell MC at an intersection with the word line WL, forms a source-side select transistor at an intersection with the source-side selected line SGS, and forms a drain-side select transistor at an intersection with the drain-side selected line SGD. The memory cell MC is also referred to as a cell transistor.

52 53 53 54 55 55 56 55 The block insulating filmis, for example, a silicon oxide film (for example, a SiO2 film) containing silicon and oxygen. The charge storage layercan store charges according to the logic of data. The charge storage layeris, for example, an insulating film such as a silicon nitride film (for example, a SiN film) containing silicon and nitrogen. The tunnel insulating filmis, for example, a silicon oxide film (for example, a SiO2 film) containing silicon and oxygen or a silicon nitride film (for example, a SiON film) containing silicon and nitrogen. The channel semiconductor layerfunctions as a channel of the memory cell MC. The channel semiconductor layeris, for example, a film containing silicon (for example, a polysilicon layer). The core insulating filmis, for example, a silicon oxide film (for example, a SiO2 film) containing silicon and oxygen. The channel semiconductor layeris an example of a semiconductor layer.

3 6 FIGS.to 1 2 are cross-sectional views of a manufacturing process from bonding of an array wafer Wand a circuit wafer Wthrough completion of the semiconductor memory device according to the first embodiment.

3 FIG. 3 FIG. 1 FIG. 3 FIG. 1 1 2 2 1 1 1 2 1 2 1 shows the array wafer Wincluding a plurality of array chipsand the circuit wafer Wincluding a plurality of circuit chips. In, the orientation of the array wafer Win the Z-direction is opposite to the orientation of the array chipin the Z-direction in. By bonding the array wafer Wand the circuit wafer Wtogether, the array chipand the circuit chipare electrically connected.shows the array wafer Wbefore the orientation is reversed for bonding.

3 FIG. 11 12 41 45 15 1 31 13 37 14 2 14 15 a In the present embodiment, as shown in, the memory cell array, an interlayer insulating film, the metal pads, the via plugs, and the like are formed on a substrateof the array wafer W. Separately from this, the transistor, the interlayer insulating film, the metal pads, and the like are formed on the substrateof the circuit wafer W. The substratesandare, for example, semiconductor substrates such as silicon substrates.

4 FIG. 1 2 1 1 2 2 12 13 a Next, as shown in, the array wafer Wand the circuit wafer Ware bonded together so that an upper surface Sof the array wafer Wfaces an upper surface Sof the circuit wafer W. Thereby, the interlayer insulating filmand the interlayer insulating filmare bonded at the bonding surface S.

1 2 41 37 1 2 12 13 a Next, the array wafer Wand the circuit wafer Ware annealed. Thereby, the metal padand the metal padare bonded together. In this manner, the array wafer Wand the circuit wafer Ware bonded together so that the interlayer insulating filmsandare sandwiched therebetween.

5 FIG. 15 12 45 a Next, as shown in, the substrateis removed by chemical mechanical polishing (CMP) or wet etching. Thereby, the interlayer insulating film, the columnar body CL, the via plug, and the like are exposed.

6 FIG. 12 12 12 a b a Next, as shown in, the source line SL is formed on the interlayer insulating filmand the columnar body CL, and an interlayer insulating filmis formed on the interlayer insulating filmvia the source line SL.

46 12 45 47 12 46 b b Next, the via plugpenetrating the interlayer insulating filmis formed on the via plug, and the metal padis formed on the interlayer insulating filmand the via plug.

48 12 47 48 47 b Next, the passivation insulating filmis formed on the interlayer insulating filmand the metal pad, and the passivation insulating filmis processed to expose a portion of the metal pad.

1 2 1 FIG. Thereafter, the array wafer Wand the circuit wafer Ware cut into a plurality of chips. In this manner, the semiconductor memory device shown inis manufactured.

1 FIG. 12 13 41 37 41 37 41 37 shows a boundary surface between the interlayer insulating filmand the interlayer insulating film, and a boundary surface (bonding surface S) between the metal padand the metal pad, but these boundary surfaces are generally not observed after the above-described annealing. However, the positions where these boundary surfaces exist can be recognized from, for example, inclinations of the side surface of the metal padand the side surface of the metal padand a positional deviation between the side surface of the metal padand the side surface of the metal pad.

7 FIG. 8 FIG. 7 FIG. 8 FIG. 7 FIG. 8 FIG. 7 FIG. 8 FIG. 7 FIG. 8 FIG. 7 FIG. 8 FIG. 7 FIG. 8 FIG. 7 FIG. 8 FIG. 7 FIG. 11 11 11 is a plan view of the memory cell arrayaccording to the first embodiment.is a cross-sectional view of the memory cell arrayaccording to the first embodiment.shows an end of the memory cell array. Line A-A inindicates a cross section taken along line A-A in. Line B-B inindicates a cross section taken along line B-B in. Line C-C inindicates a cross section taken along line C-C in. Line D-D inindicates a cross section taken along line D-D in. Line E-E inindicates a cross section taken along line E-E in. Line F-F inindicates a cross section taken along line F-F in. Line G-G inindicates a cross section taken along line G-G in.

7 FIG. 11 As shown in, the memory cell arrayhas the cell region Rmc and the WLHU region Rwlhu.

51 1 51 51 1 51 51 51 1 51 1 8 FIG. 7 FIG. a b A first stacked body_is provided in the cell region Rmc of the stacked body. As shown in, the first stacked body_is formed by alternately stacking the electrode filmsand the insulating filmsin the Z-direction. As shown in, the first stacked body_is provided with a plurality of columnar bodies CL. In addition, the first stacked body_is provided with a plurality of slits ST_CELL.

51 1 51 1 51 1 51 1 8 FIG. 7 FIG. The slits ST_CELL penetrate the first stacked body_in the Z-direction as shown inand extend in the X-direction as shown in. The slits ST_CELL divide the first stacked body_into a plurality of blocks BLK. The portion of the first stacked body_sandwiched between two slits ST_CELL is referred to as the block BLK. The block BLK is, for example, a unit of data erasure. The slit ST_CELL electrically separates the first stacked body_for each block BLK.

An inner wall of the slit ST_CELL is covered with an insulating film such as a silicon oxide film, and a conductive material is further embedded inside the insulating film. The conductive material is connected to the source line SL and can function as a source wiring. When it is not used as a source line, the slit ST_CELL may be filled with an insulating film such as a silicon oxide film (for example, SiO2 film) containing silicon and oxygen.

51 51 2 51 3 The WLHU region Rwlhu of the stacked bodyis provided adjacent to the cell region Rmc. A second stacked body_and a third stacked body_are provided in the WLHU region Rwlhu.

8 FIG. 7 FIG. 51 2 51 51 51 2 51 1 51 2 51 3 51 2 b c As shown in, the second stacked body_is formed by alternately stacking the insulating films(for example, silicon oxide films) and insulating films(for example, silicon nitride films) in the Z-direction. As shown in, the second stacked body_is adjacent to the first stacked body_with the slit ST_WLC sandwiched therebetween. In addition, the second stacked body_is adjacent to the third stacked body_. The second stacked body_is provided with a plurality of word line contacts WLC.

8 FIG. 7 FIG. 51 1 51 2 51 1 51 2 51 1 51 2 51 51 2 51 51 1 51 3 c a As shown in, the slit ST_WLC penetrates the first or second stacked body_or_in the Z-direction between the first stacked body_and the second stacked body_. As shown in, the slit ST_WLC extends intermittently in the Y-direction in the X-Y plane. The slit ST_WLC is filled with an insulating film (for example, a silicon oxide film). Thereby, the first stacked body_and the second stacked body_are physically separated from each other, and the insulating filmof the second stacked body_in the WLHU region Rwlhu is prevented from being replaced with the conductive material of the electrode film. On the other hand, the slit ST_WLC has an opening OP for connecting a portion of the first stacked body_in the cell region Rmc to the third stacked body_in the WLHU region Rwlhu for each block BLK.

8 FIG. 7 FIG. 51 3 51 51 51 3 51 1 51 1 51 1 51 51 51 3 51 1 51 3 51 51 1 51 3 51 51 1 51 3 51 51 3 a b a b b c a As shown in, the third stacked body_is formed by alternately stacking the electrode films(for example, tungsten, molybdenum) and the insulating films(for example, silicon oxide films) in the Z-direction. As shown in, the third stacked body_is connected to the first stacked body_from the end of the first stacked body_through the opening OP, and extends in the +X-direction from the end of the first stacked body_in the X-Y plane. The electrode filmsand the insulating filmsof the third stacked body_are continuously connected to those of the first stacked body_in each layer. Furthermore, a dummy columnar body DMC is provided at the end of the third stacked body_on the cell region Rmc side. The dummy columnar body DMC is formed at the same time as the columnar body CL in the first stacked body, but does not function as a memory cell. The dummy columnar body DMC prevents the insulating filmat the connection between the first stacked body_and the third stacked body_from bending due to its own weight when the insulating filmof the first and third stacked bodies_and_is replaced with the conductive material of the electrode film. Furthermore, the third stacked body_is provided with a slit ST_LWI. The dummy columnar body DMC may be disposed around the slit ST_LWI to prevent bending.

8 FIG. 7 FIG. 51 3 51 3 51 3 As shown in, the slit ST_LWI penetrates the third stacked body_in the Z-direction in the third stacked body_. As shown in, the slit ST_LWI extends in the X-direction along the extension direction of the third stacked body_in the X-Y plane. The inner wall of the slit ST_LWI is covered with an insulating film such as a silicon oxide film, and a conductive material is further embedded inside the insulating film. Thereby, the slit ST_LWI can be formed at the same time as the slit ST_CELL. However, the conductive material does not need to be connected to the source line SL. Thus, alternatively, the slit ST_LWI may be filled with an insulating film such as a silicon oxide film.

7 FIG. 8 FIG. 51 2 51 a As shown in, the plurality of word line contacts WLC extend in the Z-direction in the second stacked body_. As shown in, the plurality of word line contacts WLC are provided to the depth of each of the plurality of electrode films(that is, word lines WL).

26 The word line contact WLC is embedded inside a spacer(for example, silicon oxide film) provided on the inner wall of the contact hole. For example, tungsten is used for the word line contact WLC.

7 FIG. 8 FIG. 51 51 1 51 3 51 27 51 51 26 51 a a d a a c. For example, in the cross section taken along line D-D in, as shown in, a word line contact WLCd extends to the electrode filmwhich is the second layer from the bottom of the first or third stacked body_or_, and is not provided below that in the −Z-direction. The word line contact WLCd is electrically connected to the electrode filmwhich is the second layer from the bottom via a connect layer. The word line contact WLCd is electrically insulated from the electrode filmsother than the electrode filmwhich is the second layer from the bottom by the spacerand the insulating film

7 FIG. 8 FIG. 51 51 1 51 3 51 27 51 51 26 51 a a e a a c. In the cross section taken along line E-E in, as shown in, a word line contact WLCe extends to the electrode filmwhich is the third layer from the bottom of the first or third stacked body_or_, and is not provided below that in the −Z-direction. The word line contact WLCe is electrically connected to the electrode filmwhich is the third layer from the bottom via a connect layer. The word line contact WLCe is electrically insulated from the electrode filmsother than the electrode filmwhich is the third layer from the bottom by the spacerand the insulating film

7 FIG. 8 FIG. 51 51 1 51 3 51 27 51 51 26 51 a a f a a c. In the cross section taken along line F-F in, as shown in, a word line contact WLCf extends to the electrode filmwhich is the fourth layer from the bottom of the first or third stacked body_or_, and is not provided below that in the −Z-direction. The word line contact WLCf is electrically connected to the electrode filmwhich is the fourth layer from the bottom via a connect layer. The word line contact WLCf is electrically insulated from the electrode filmsother than the electrode filmwhich is the fourth layer from the bottom by the spacerand the insulating film

7 FIG. 8 FIG. 51 51 1 51 3 51 27 51 51 26 51 a a g a a c. In the cross section taken along line G-G in, as shown in, a word line contact WLCg extends to the electrode filmwhich is the fifth layer from the bottom of the first or third stacked body_or_, and is not provided below that in the −Z-direction. The word line contact WLCg is electrically connected to the electrode filmwhich is the fifth layer from the bottom via a connect layer. The word line contact WLCg is electrically insulated from the electrode filmsother than the electrode filmwhich is the fifth layer from the bottom by the spacerand the insulating film

51 51 a a. Although not shown in the drawing, the other word line contacts WLC are also provided to their respective depths in the other electrode films, and are electrically connected to the corresponding electrode films

51 27 a In this manner, each word line contact WLC is electrically connected to the corresponding electrode filmvia one connect layer.

27 51 27 51 27 27 a c The plurality of connect layersare provided between the plurality of word line contacts WLC and the plurality of corresponding electrode films, and electrically connect them. The connect layeris formed by isotropically etching the second insulating filmfrom the bottom of each word line contact WLC. Thus, the connect layersspread substantially evenly from the bottom of each word line contact WLC to its periphery. The connect layeris made of a conductive material such as tungsten or molybdenum.

27 51 51 1 51 3 27 51 d a d a For example, the connect layeris provided between the word line contact WLCd and the electrode filmwhich is the second layer from the bottom of the first or third stacked body_or_, and electrically connects them. The connect layeris not provided in any layer other than the electrode filmwhich is the second layer from the bottom.

27 51 51 1 51 3 27 51 e a e a The connect layeris provided between the word line contact WLCe and the electrode filmwhich is the third layer from the bottom of the first or third stacked body_or_, and electrically connects them. The connect layeris not provided in any layer other than the electrode filmwhich is the third layer from the bottom.

27 51 51 1 51 3 27 51 f a f a The connect layeris provided between the word line contact WLCf and the electrode filmwhich is the fourth layer from the bottom of the first or third stacked body_or_, and electrically connects them. The connect layeris not provided in any layer other than the electrode filmwhich is the fourth layer from the bottom.

27 51 51 1 51 3 27 51 g a g a The connect layeris provided between the word line contact WLCg and the electrode filmwhich is the fifth layer from the bottom of the first or third stacked body_or_, and electrically connects them. The connect layeris not provided in any layer other than the electrode filmwhich is the fifth layer from the bottom.

8 FIG. 57 58 51 1 51 3 57 58 57 58 As shown in, interlayer insulating filmsandare provided on the first to third stacked bodies_to_. For example, insulating films (for example, silicon oxide films) are used for the interlayer insulating filmsand. The slits ST_CELL, ST_WLC, and ST_LWI and the word line contacts WLC extend to penetrate the interlayer insulating filmsandin the Z-direction.

51 51 2 51 51 3 27 a a In this manner, according to the first embodiment, the plurality of word line contacts WLC are provided to the depth of each of the plurality of electrode filmsin the second stacked body_, and are electrically connected to the electrode filmcorresponding to each of the third stacked bodies_via the connect layer.

51 51 1 51 51 3 51 51 1 51 51 3 51 51 51 1 51 3 a a b b a a The plurality of electrode filmsof the first stacked body_respectively correspond to and are electrically connected to the plurality of electrode filmsof the third stacked body_. In addition, the plurality of insulating filmsof the first stacked body_respectively correspond to the plurality of insulating filmsof the third stacked body_, and electrically separate the electrode filmsadjacent to each other in the Z-direction. Thereby, the plurality of word line contacts WLC can be electrically connected to the plurality of electrode filmsof the first and third stacked bodies_and_, respectively, while maintaining an electrical insulation state of each other.

51 2 51 51 51 51 2 51 51 1 51 3 51 51 2 51 51 1 51 3 51 27 51 27 b c b b c a a a Meanwhile, the second stacked body_includes first and second insulating filmsand. The plurality of first insulating filmsof the second stacked body_correspond to the plurality of first insulating filmsof the first and third stacked bodies_and_, respectively. The plurality of second insulating filmsof the second stacked body_correspond to the plurality of electrode filmsof the first and third stacked bodies_and_, respectively. Thus, in the WLHU region Rwlhu, the plurality of word line contacts WLC are electrically isolated from the electrode filmsand the connect layersother than the electrode filmsand the connect layerscorresponding to them.

51 a Thereby, voltages can be applied separately from the word line contacts WLC to the electrode films(i.e., the word lines WL).

51 51 1 51 3 51 51 51 2 51 c a c b Further, in a manufacturing process to be described below, when the second insulating filmsof the first and third stacked bodies_and_are replaced with the electrode films, the second insulating filmof the second stacked body_is left without being replaced. Thereby, it is possible to prevent the first insulating filmfrom bending or being depressed due to its own weight without the need to provide a support pillar in the WLHU region Rwlhu.

7 FIG. In, one block BLK is provided with one opening OP and one slit ST_LWI. However, one block BLK may be provided with a plurality of openings OP and a plurality of slits ST_LWI. In this case, word line contacts WLC may be provided around each slit ST_LWI.

Next, a manufacturing method for the semiconductor memory device according to the present embodiment will be described.

9 31 FIGS.to 9 FIG. 13 FIG. 18 FIG. 20 FIG. 23 FIG. 25 FIG. 27 FIG. 10 12 FIGS.to 14 17 FIGS.to 19 FIG. 21 FIG. 22 FIG. 24 FIG. 26 FIG. 28 31 FIGS.to 11 11 are diagrams of a manufacturing method for the semiconductor memory device according to the first embodiment.,,,,,, andshow the plane of the memory cell array.,,,,,,, andshow the cross section of the memory cell array.

9 FIG. 10 FIG. 7 FIG. 10 FIG. The cross sections taken along lines A-A, B-B, C-C, and D-D in the plan views ofand the like are respectively shown as A-A, B-B, C-C, and D-D in the cross sections ofand the like. Structures corresponding to the cross sections taken along lines E-E, F-F, and G-G inare not shown inand the like.

10 FIG. 51 51 15 51 57 51 b c As shown in, the first insulating films(for example, silicon oxide films) and the second insulating films(for example, silicon nitride films) are alternately stacked on the substratein the Z-direction to form the stacked body. Furthermore, the interlayer insulating film(for example, a silicon oxide film) is deposited on the stacked body.

9 FIG. 10 FIG. 51 51 51 51 1 51 3 51 51 c a c b c. Next, a slit hole (trench) H_ST_WLC of the slit ST_WLC and a contact hole H_WLC of the word line contact WLC are formed using lithography and etching techniques. The slit hole H_ST_WLC is provided between the cell region Rmc and the WLHU region Rwlhu. As shown in, the slit hole H_ST_WLC has the opening OP so as to connect a portion of the cell region Rmc to the WLHU region Rwlhu while separating the cell region Rmc from the WLHU region Rwlhu. As shown in, the contact hole H_WLC is formed in the WLHU region Rwlhu to the second insulating filmcorresponding to the depth of the electrode filmto which it is electrically connected. The plurality of contact holes H_WLC are formed to the second insulating filmshaving different depths. The first stacked body_and the third stacked body_are each include a stacked body including a plurality of first insulating filmsand a plurality of second insulating films

11 FIG. 26 1 26 1 26 51 51 57 Next, as shown in, the spacer(for example, a silicon oxide film) is formed on the inner wall of each of the slit hole H_ST_WLC and the contact hole H_WLC. Next, a sacrificial film SACis embedded inside the spacerin each of the slit hole H_ST_WLC and the contact hole H_WLC. The sacrificial film SACis made of a material (for example, polysilicon, carbon) that can be etched with respect to the spacerand the stacked body. Next, the stacked bodyis covered with the silicon oxide filmso that the upper ends of the slit hole H_ST_WLC and the contact hole H_WLC are not exposed to the outside.

57 1 12 FIG. Next, the interlayer insulating filmon the slit hole H_ST_WLC is removed using lithography and etching techniques, the sacrificial film SACin the slit hole H_ST_WLC is selectively removed, and an insulating film (for example, a silicon oxide film) is embedded in the slit hole H_ST_WLC. Thereby, the slit ST_WLC is formed as shown in.

13 FIG. 2 FIG. 51 51 52 53 54 55 56 Next, as shown in, a plurality of memory holes MH are formed to penetrate the stacked bodyin the Z-direction in the cell region Rmc of the stacked body. Next, the block insulating film, the charge storage layer, the tunnel insulating film, the channel semiconductor layer, and the core insulating filmshown inare formed on the inner wall of the memory hole MH in this order. Thereby, the columnar body CL is formed in the memory hole MH.

51 52 53 54 55 56 51 b At the same time as when the memory hole MH is formed, a dummy hole DMH is formed near the opening OP in the WLHU region Rwlhu. The dummy hole DMH also penetrates the stacked bodyin the Z-direction. In addition, at the same time when the columnar body CL is formed, the block insulating film, the charge storage layer, the tunnel insulating film, the channel semiconductor layer, and the core insulating filmare formed on the inner wall of the dummy hole DMH in this order. Thereby, the dummy columnar body DMC is formed in the dummy hole DMH. The dummy columnar body DMC is a columnar body having the same structure as the columnar body CL, but does not function as a memory cell. The dummy columnar body DMC is provided to support the first insulating filmnear the opening OP in a replacement process to be described below.

13 14 FIGS.and 51 51 Next, as shown in, the slit hole H_ST_CELL for the slit ST_CELL and the slit hole H_ST_LWI for the slit ST_LWI are formed using lithography and etching techniques. The slit hole H_ST_CELL penetrates the cell region Rmc of the stacked bodyin the Z-direction and extends in the X-direction in the X-Y plane. The slit hole H_ST_LWI penetrates the WLHU region Rwlhu of the stacked bodyin the Z-direction and extends in the X-direction in the X-Y plane.

58 57 58 15 FIG. Next, the insulating filmis deposited on the insulating filmunder poor coverage conditions using a plasma chemical vapor deposition (CVD) method or the like. As shown in, the insulating filmis formed to close the openings of the slit holes H_ST_CELL and H_ST_WLI without filling them.

57 58 1 Next, the insulating filmsandon the contact holes H_WLC are removed using lithography and etching techniques to expose the surface of the sacrificial film SAC.

16 FIG. 1 26 26 26 51 c Next, as shown in, the sacrificial film SACin the contact hole H_WLC is selectively removed using a wet etching method, an ashing method or the like, and the spacerat the bottom of the contact hole H_WLC is removed by anisotropic etching. Thereby, the spacerat the bottom is removed while leaving the spaceron the sidewall of each contact hole H_WLC, and the second insulating filmis exposed at the bottom.

17 FIG. 58 Next, as shown in, the insulating filmon the slit hole H_ST_LWI is removed using lithography and etching techniques.

18 19 FIGS.and 18 FIG. 19 FIG. 51 51 51 51 51 51 27 51 27 c c c c c Next, as shown in, the second insulating filmof the stacked bodyin the WLHU region Rwlhu is isotropically etched through the contact hole H_WLC and the slit hole H_ST_LWI using wet etching or chemical dry etching (CDE) method. Thereby, the second insulating filmis recessed in the X-Y plane. As shown by arrows in, the second insulating filmsof the stacked bodyare recessed through the slit hole H_ST_LWI to form a recess region RCS. At this time, the second insulating filmexposed at the bottom of the contact hole H_WLC is etched from the contact hole H_WLC side and is also etched from the slit hole H_ST_LWI side. That is, as shown by arrows Ain, the second insulating filmexposed at the bottom of the contact hole H_WLC is etched from both the contact hole H_WLC side and the slit hole H_ST_LWI side. Thereby, the contact hole H_WLC and the slit hole H_ST_LWI communicate with each other via a cavity H.

26 51 51 51 c c c. The inner wall of the contact hole H_WLC other than the bottom is protected by the spacer. Thus, the second insulating filmis not exposed at the inner wall of the contact hole H_WLC and is not etched. Thus, the contact hole H_WLC and the slit hole H_ST_LWI communicate with each other in the layer of the second insulating filmexposed at the bottom of the contact hole H_WLC, but do not communicate with each other in the other layers of the second insulating film

19 FIG. 18 FIG. 27 27 27 51 51 27 51 51 27 51 51 27 51 51 d g. d c e c f c g c Although not shown in, the same is true for the other contact holes H_WLC. For example, in, for the sake of convenience, four contact holes are indicated as H_WLCd to H_WLCg, and four corresponding cavities are indicated as Hto HThe contact hole H_WLCd communicates with the slit hole H_ST_LWI via the cavity Hin the second insulating filmwhich is the second layer from the bottom of the stacked body. The contact hole H_WLCe communicates with the slit hole H_ST_LWI via the cavity Hin the second insulating filmwhich is the third layer from the bottom of the stacked body. The contact hole H_WLCf communicates with the slit hole H_ST_LWI via the cavity Hin the second insulating filmwhich is the fourth layer from the bottom of the stacked body. The contact hole H_WLCg communicates with the slit hole H_ST_LWI via the cavity Hin the second insulating filmwhich is the fifth layer from the bottom of the stacked body.

51 51 27 51 c c c In this manner, the contact hole H_WLC and the slit hole H_ST_LWI communicate with each other in the second insulating filmshaving different depths and exposed at the bottom of each contact hole H_WLC, but do not communicate with each other in the second insulating filmsof the other layers. Thereby, the plurality of contact holes H_WLC communicate with the slit holes H_ST_LWI via the cavities Hin the second insulating filmsof different layers.

20 21 FIGS.and 2 2 26 51 Next, as shown in, a sacrificial film SACis formed in the contact hole H_WLC and the slit hole H_ST_LWI. The sacrificial film SACis made of a material (for example, polysilicon, carbon) that can be selectively etched with respect to the spacerand the stacked body.

58 22 FIG. Next, the interlayer insulating filmon the slit hole H_ST_CELL is removed using lithography and etching techniques, as shown in.

23 24 FIGS.and 23 FIG. 51 51 51 51 c c c Next, as shown in, the second insulating filmof the stacked bodyin the cell region Rmc is isotropically etched through the slit hole H_ST_CELL by using wet etching or a CDE method. Thereby, as shown in, the plurality of second insulating filmsin the cell region Rmc are removed in the X-Y plane through the slit holes H_ST_CELL. In the cell region Rmc, the second insulating filmaround the columnar body CL is removed.

51 51 2 c c 23 FIG. The etching of the second insulating filmis stopped at the slit ST_WLC. However, the etching of the second insulating filmproceeds from the opening OP toward the WLHU region Rwlhu and reaches the slit hole H_ST_LWI. Thereby, as shown in, the slit hole H_ST_CELL communicates with the slit hole H_ST_LWI and the contact hole H_WLC through the opening OP. At this time, the slit hole H_ST_LWI and the contact hole H_WLC are filled with the sacrificial film SAC.

24 FIG. 51 51 51 51 51 c b b c As shown in, a space SP is formed at a location where the second insulating filmis provided. At this time, in the cell region Rmc, the columnar bodies CL support the first insulating film, and thus the first insulating filmcan be prevented from bending or being depressed. Further, in the WLHU region Rwlhu, no support pillar is provided except for the dummy columnar body DMC. However, in the WLHU region Rwlhu other than the vicinity of the slit hole H_ST_LWI and the contact hole H_WLC, the second insulating filmis left, and no space SP is formed. Thus, in the WLHU region Rwlhu, even when there is no support pillar, the stacked bodycan be prevented from bending or being depressed.

25 26 FIGS.and 2 51 c. Next, as shown in, the sacrificial film SACis selectively removed using a wet etching method, an ashing method, or the like. Thereby, the slit hole H_ST_CELL communicates with the slit hole H_ST_LWI through the space SP in each layer formed by removing the plurality of second insulating films

51 51 51 51 1 51 3 51 51 51 2 51 51 51 1 51 3 51 51 b a b b a b c c a Next, a thin block insulating film (for example, an aluminum oxide film) (not shown) is formed on the inner wall of the space SP formed between the first insulating filmsthrough the contact hole H_WLC, the slit hole H_ST_CELL, and the slit hole H_ST_LWI. Furthermore, a titanium nitride film (not shown) is formed inside the block insulating film, and a conductive material is embedded therein. For example, tungsten, molybdenum, and the like are used as the conductive material. Thereby, the electrode filmis formed between the first insulating filmsadjacent to each other in the Z-direction. The first and third stacked bodies_and_are stacked bodies including a plurality of first insulating filmsand a plurality of electrode films. The second stacked body_is a stacked body including a plurality of first insulating filmsand a plurality of second insulating films. In this manner, in the first and third stacked bodies_and_, the second insulating filmis replaced with the electrode film(hereinafter referred to as a replacement process).

51 51 a a 27 28 FIGS.and Next, the material of the electrode filmformed on the inner walls of the contact hole H_WLC, the slit hole H_ST_CELL, and the slit hole H_ST_LWI is etched by a wet etching method to remove a short-circuit path between the electrode filmsadjacent to each other in the Z-direction, thereby obtaining the structure shown in.

3 3 58 58 3 3 29 FIG. Next, the contact hole H_WLC, the slit hole H_ST_CELL, and the slit hole H_ST_LWI are filled with a sacrificial film SACsuch as polysilicon or carbon. Next, the upper portion of the sacrificial film SACis removed by an etch-back method using CMP or RIE, and then the interlayer insulating filmis deposited on the surface thereof. Thereafter, the interlayer insulating filmon the slit hole H_ST_CELL and the slit hole H_ST_LWI is removed using a lithography technique, and the sacrificial film SACin the slit hole H_ST_CELL and the slit hole H_ST_LWI is selectively removed by a wet etching method, an ashing method, or the like. At this time, the sacrificial film SACis left in the contact hole H_WLC, thereby obtaining the structure shown in.

30 FIG. 26 Next, as shown in, the spaceris formed on the inner wall of the slit hole H_ST_CELL and the slit hole H_ST_LWI.

58 3 3 31 FIG. Next, the interlayer insulating filmon the contact hole H_WLC is removed using lithography and etching techniques to expose the sacrificial film SAC. Next, the sacrificial film SACis removed using a wet etching method, an ashing method, or the like as shown in.

7 8 FIGS.and Next, a conductive material is embedded in the contact hole H_WLC, the slit hole H_ST_CELL, and the slit hole H_ST_LWI. Thereby, the structure shown inis obtained.

58 3 6 FIGS.to Thereafter, a multilayer wiring layer (not shown) and the like are formed on the interlayer insulating film, and the semiconductor memory device according to the present embodiment is completed through the processes described with reference to.

51 51 1 51 3 51 51 51 2 51 c a c b According to the manufacturing method of the present embodiment, when the second insulating filmsof the first and third stacked bodies_and_are replaced with the electrode films, the second insulating filmof the second stacked body_is left without being replaced. Thereby, it is possible to prevent the first insulating filmfrom bending or being depressed due to its own weight in the WLHU region Rwlhu without the need to provide a support pillar.

32 FIG. 11 is a plan view of the memory cell arrayaccording to a second embodiment. In the second embodiment, slits ST_CELL, ST_WLC, and ST_LWI are formed using a plurality of holes H_ST_CELL, H_ST_WLC, and H_ST_LWI arranged in the X-direction. Thus, the slits ST_CELL, ST_WLC, and ST_LWI each extend in the arrangement direction of the plurality of holes (H_ST_CELL, H_ST_WLC, and H_ST_LWI). The slits ST_CELL and ST_WLC are formed by connecting the plurality of holes with an insulating film by filling the periphery of the plurality of holes (H_ST_CELL and H_ST_WLC) with an insulating film such as a silicon oxide film. The slit ST_LWI is formed by connecting the plurality of holes with a conductive material by filling the periphery of the plurality of holes (H_ST_LWI) with a conductive material such as tungsten.

51 1 51 51 51 1 c b For example, the slit ST_CELL includes a plurality of holes H_ST_CELL that penetrate the first stacked body_in the Z-direction and are arranged in the X-direction. The slit ST_CELL is formed by selectively removing a second insulating filmbetween first insulating filmsadjacent to each other in the Z-direction through the plurality of holes H_ST_CELL, and filling an insulating film such as a silicon oxide film. Thereby, the slit ST_CELL is formed to connect the holes H_ST_CELL adjacent to each other in the X-direction with the insulating film. Thus, the slit ST_CELL extends in the X-direction in which the plurality of holes H_ST_CELL are arranged, and electrically separates the first stacked body_for each block BLK.

51 2 Furthermore, the slit ST_CELL also extends to the second stacked body_in the WLHU region Rwlhu from between the adjacent blocks BLK in the X-direction, and separates word line contacts WLC adjacent to each other in the Y-direction.

51 51 1 51 2 51 b b The slit ST_WLC includes a plurality of holes H_ST_WLC penetrating the plurality of first insulating filmsbetween the first stacked body_and the second stacked body_in the Z-direction and arranged in the Y-direction. The slit ST_WLC fills an insulating film, such as a silicon oxide film, between the first insulating filmsadjacent to each other in the Z-direction via the plurality of holes H_ST_WLC. Thereby, the slit ST_WLC is formed to connect the holes H_ST_WLC adjacent to each other in the Y-direction with the insulating film. Thus, the slit ST_WLC extends in the Y-direction in which the plurality of holes H_ST_WLC are arranged, and separates the cell region Rmc from the WLHU region Rwlhu.

The slit ST_WLC has the opening OP as in the first embodiment, and the cell region Rmc and the WLHU region Rwlhu communicate with each other at the opening OP.

51 3 51 51 51 51 1 51 c b a a The slit ST_LWI includes a plurality of holes H_ST_LWI that penetrate the third stacked body_in the Z-direction and are arranged in the X-direction. The slit ST_LWI is formed by selectively removing the second insulating filmbetween the first insulating filmsadjacent to each other in the Z-direction through the plurality of holes H_ST_LWI and filling with a conductive material such as tungsten. Thereby, the slit ST_LWI is formed to connect the holes H_ST_LWI adjacent to each other in the X-direction with a conductive material. Thus, the slit ST_LWI extends in the X-direction in which the plurality of holes H_ST_LWI are arranged, and electrically connects an electrode filmof the first stacked body_and the word line contact WLC. The electrode filmof the slit ST_LWI functions as a path for connection to the word line contact WLC through the opening OP.

26 51 3 51 51 3 a The spaceris provided on the inner walls of the plurality of holes H_ST_LWI, and the holes H_ST_LWI themselves are electrically insulated from the third stacked body_. Thus, electrode filmsadjacent to each other in the Z-direction of the third stacked body_are electrically separated from each other.

2 2 2 2 51 2 2 51 51 2 2 2 2 2 c b Furthermore, in the second embodiment, a slit ST_WLCis provided. The slit ST_WLCextends in the Y-direction from the slit ST_CELL to the slit ST_LWI between the plurality of word line contacts WLC adjacent to each other in the X-direction. The slit ST_WLCincludes a plurality of holes H_ST_WLCthat penetrate the second stacked body_in the Z-direction and are arranged in the Y-direction. The slit ST_WLCis formed by selectively removing the second insulating filmbetween the first insulating filmsvia the plurality of holes H_ST_WLCand filling with an insulating film such as a silicon oxide film. Thereby, the slit ST_WLCis formed to connect the holes H_ST_WLCadjacent to each other in the Y-direction with the insulating film. Thus, the slit ST_WLCextends in the Y-direction in which the plurality of holes H_ST_WLCare arranged, and separates the word line contacts WLC adjacent to each other in the X-direction.

51 1 51 1 26 26 51 51 1 51 c a. A plurality of holes H_REP are provided on both sides of the slit ST_CELL in the cell region Rmc and are arranged in the X-direction. The holes H_REP penetrate the slit ST_CELL or the first stacked body_in the Z-direction at a boundary portion between the slit ST_CELL and the first stacked body_. The spaceris provided on the inner wall of the hole H_REP, and a conductive material is provided inside the spacer. The hole H_REP is used when replacing the second insulating filmof the first stacked body_with the electrode film

51 3 51 2 51 3 51 2 51 3 51 51 3 51 51 3 51 b c a A plurality of dummy columnar bodies DMC are provided on both sides of the third stacked body_in the WLHU region Rwlhu and are arranged in the X-direction. The dummy columnar body DMC penetrates the second stacked body_or the third stacked body_in the Z-direction at a boundary portion between the second stacked body_and the third stacked body_. The dummy columnar body DMC has the same configuration as the columnar body CL, but does not function as the memory cell MC. The dummy columnar body DMC is used as a support for the first insulating filmof the third stacked body_when the second insulating filmof the third stacked body_is replaced with the electrode film. The dummy columnar body DMC may not be necessarily provided.

51 2 51 51 51 3 27 51 3 51 51 51 1 a a a a The plurality of word line contacts WLC extend through the second stacked body_in the Z-direction, and are provided to the depth of each of the plurality of electrode films(that is, the word lines WL). The word line contacts WLC are electrically connected to one of the electrode filmsof the third stacked body_via a connect layerprovided at the bottom of each of the word line contacts. The third stacked body_has a plurality of electrode filmsextending through the WLHU region Rwlhu in the X-direction, and is electrically connected to the plurality of electrode filmsof the first stacked body_at the opening OP. Thus, the voltage of each word line WL can be controlled via each word line contact WLC.

The other configurations in the second embodiment may be the same as those in the first embodiment. Thus, in the second embodiment, it is possible to obtain the same effects as those in the first embodiment.

Next, a manufacturing method for the semiconductor memory device according to the second embodiment will be described.

33 39 FIGS.to 51 51 51 b c are plan views of a manufacturing method for the semiconductor memory device according to the second embodiment. As in the first embodiment, the stacked bodyis formed by stacking the plurality of first insulating films(for example, silicon oxide films) and the plurality of second insulating films(for example, silicon nitride films).

33 FIG. 51 51 51 1 c Next, as shown in, contact holes H_WLC for the word line contacts WLC are formed in the stacked body. The plurality of contact holes H_WLC are formed to different depths in the WLHU region Rwlhu so as to reach respective one of the plurality of second insulating filmsof the stacked body. Next, the contact holes H_WLC are filled with the sacrificial film SAC(for example, polysilicon or carbon).

34 FIG. 51 2 51 2 1 Next, as shown in, a plurality of memory holes MH are formed in the cell region Rmc. The memory holes MH are formed to penetrate the stacked body. At the same time, holes H_REP, H_ST_CELL, H_ST_WLC, H_ST_WLC, and DMH are also formed to penetrate the stacked body. The memory holes MH and the holes H_REP, H_ST_CELL, H_ST_WLC, H_ST_WLC, and DMH are also filled with the sacrificial film SAC.

58 51 58 2 1 Next, the interlayer insulating filmis deposited on the surface of the stacked body, the silicon oxide filmon the holes H_ST_CELL, H_ST_WLC, and H_ST_WLCis removed using lithography and etching techniques, and the sacrificial film SACis selectively removed using a wet etching method, an ashing method, or the like.

51 51 2 2 51 c c Next, a portion of each of the plurality of second insulating filmsof the stacked bodyis isotropically etched through the holes H_ST_CELL, H_ST_WLC, and H_ST_WLCby using a wet etching method. Thereby, the holes H_ST_CELL, H_ST_WLC, and H_ST_WLCcommunicate with each other in a space after the second insulating filmsare removed.

51 2 2 51 c b 35 FIG. Next, a fourth insulating film is embedded in the space after the second insulating filmsare removed through the holes H_ST_CELL, H_ST_WLC, and H_ST_WLC. For the fourth insulating film, an insulating material such as a silicon oxide film is used. Thereby, as shown in, the slits ST_CELL, ST_WLC, and ST_WLCare configured with a stacked body of the first insulating filmand the fourth insulating film.

58 51 58 1 Next, the interlayer insulating filmis deposited on the surface of the stacked body, the interlayer insulating filmon the memory hole MH and the dummy hole DMH is removed using lithography and etching techniques, and the internal sacrificial film SACis selectively removed using a wet etching method, an ashing method, or the like.

36 FIG. Next, as shown in, the columnar body CL is formed in the memory hole MH, and the dummy columnar body DMC is formed in the dummy hole DMH. The columnar body CL and the dummy columnar body DMC have the same configurations as those in the first embodiment, and are formed in the same process.

58 51 58 1 Next, the interlayer insulating filmis deposited on the surface of the stacked body, the interlayer insulating filmon the hole H_REP is removed using lithography and etching techniques, and the internal sacrificial film SACis selectively removed using a wet etching method, an ashing method, or the like.

51 51 51 51 c c b c 37 FIG. Next, the second insulating filmin the cell region Rmc is isotropically etched through the hole H_REP using a wet etching method. Thereby, as shown in, the second insulating filmaround the columnar body CL in the cell region Rmc is removed, and the space SP is formed between the first insulating films. The space SP extends to the vicinity of the opening OP. The second insulating filmin the WLHU region Rwlhu is left.

58 51 58 1 Next, the interlayer insulating filmis deposited on the surface of the stacked body, the interlayer insulating filmon the contact hole H_WLC is removed using lithography and etching techniques, and the internal sacrificial film SACis selectively removed using a wet etching method, an ashing method, or the like.

26 26 26 26 51 c Next, the spacer(for example, a silicon oxide film) is formed on the inner wall of the contact hole H_WLC. Next, the spacerat the bottom of the contact hole H_WLC is removed by anisotropic etching. Thereby, the spacerat the bottom is removed while leaving the spaceron the side wall of the contact hole H_WLC, and the second insulating filmis exposed at the bottom.

51 51 51 2 51 2 c c c 38 FIG. The second insulating filmof the stacked bodyin the WLHU region Rwlhu is isotropically etched from the bottom of the contact hole H_WLC through the contact hole H_WLC using a wet etching method or a CDE method. Thereby, as shown in, the second insulating filmis etched in the X-Y plane from the bottom of the contact hole H_WLC toward the slits ST_CELL, ST_WLC, and ST_WLC. The space SP is formed at a location where the second insulating filmis etched. The slits ST_CELL, ST_WLC, and ST_WLCfunction as etching stoppers.

51 51 51 26 c c 38 FIG. Here, the plurality of contact holes H_WLC are formed to different depths in the WLHU region Rwlhu so as to reach respective one of the plurality of second insulating filmsof the stacked body. Thus, the plurality of contact holes H_WLC form the space SP in a plurality of layers having different heights. The second insulating filmother than the bottom of the contact hole H_WLC is not etched because it is covered with the spacer. In, only one space SP formed at the bottom of one contact hole H_WL is shown.

58 51 58 1 Next, the interlayer insulating filmis deposited on the surface of the stacked body, the interlayer insulating filmon the plurality of holes H_ST_LWI is removed using lithography and etching techniques, and the internal sacrificial film SACis selectively removed using a wet etching method, an ashing method, or the like.

51 51 51 51 51 51 c c c b 39 FIG. Next, the second insulating filmof the stacked bodyin the WLHU region Rwlhu is isotropically etched through the plurality of holes H_ST_LWI by using a wet etching method or a CDE method. The plurality of holes H_ST_LWI communicate with each other in the X-direction in the space SP after the second insulating filmis removed. Thereby, as shown in, the space SP is continuously connected from the opening OP in the arrangement direction (i.e., X-direction) of the plurality of holes H_ST_LWI. In addition, the space SP from the holes H_ST_LWI communicates with the space SP from each contact hole H_WLC. The space SP from the hole H_ST_LWI is formed by etching the second insulating filmof each layer of the stacked body. At this time, the dummy columnar body DMC functions as a support pillar so that the first insulating filmbetween the contact hole H_WLC and the hole H_ST_LWI does not bend.

The space SP communicates with the hole H_ST_LWI of the WLHU region Rwlhu through the opening OP from the cell region Rmc. Furthermore, the space SP communicates with the corresponding contact hole H_WLC from the hole H_ST_LWI through the space SP of each layer.

51 51 51 51 1 51 3 51 51 51 2 51 51 51 1 51 3 51 51 b a b b a b c c a. Next, a thin block insulating film (for example, an aluminum oxide film) (not shown) is formed on the inner wall of the space SP formed between the first insulating filmsthrough the hole H_REP, the hole H_ST_LWI, and the contact hole H_WLC. Furthermore, a titanium nitride film (not shown) is formed inside the block insulating film, and a conductive material is further embedded therein. For example, tungsten, molybdenum, and the like are used as the conductive material. Thereby, the electrode filmis formed between the first insulating filmsadjacent to each other in the Z-direction. The first and third stacked bodies_and_are stacked bodies including a plurality of first insulating filmsand a plurality of electrode films. The second stacked body_is a stacked body including a plurality of first insulating filmsand a plurality of second insulating films. In this manner, in the first and third stacked bodies_and_, the second insulating filmis replaced with the electrode film

51 51 a a Next, the material of the electrode filmformed on the inner walls of the hole H_REP, the hole H_ST_LWI, and the contact hole H_WLC is etched by a wet etching method to remove a short-circuit path between the electrode filmsadjacent to each other in the Z-direction.

3 3 58 58 3 3 26 26 32 FIG. Next, the hole H_REP, the hole H_ST_LWI, and the contact hole H_WLC are filled with the sacrificial film SAC(for example, polysilicon or carbon). Next, the upper portion of the sacrificial film SACis removed by an etch-back method using CMP or RIE, and then the interlayer insulating filmis deposited on the surface thereof. Thereafter, the interlayer insulating filmon the holes H_REP and H_ST_LWI is removed using a lithography technique, and the sacrificial film SACin the holes H_REP and H_ST_LWI is selectively removed by a wet etching method, an ashing method, or the like. At this time, the sacrificial film SACis left in the contact hole H_WLC. Next, the spacer(for example, a silicon oxide film) is formed on the inner walls of the hole H_REP and the hole H_ST_LWI. Thereafter, a conductive material is further embedded inside the spacer. Thereby, the structure shown inis obtained.

3 6 FIGS.to Thereafter, a multi-layer wiring layer (not shown) is formed, and the semiconductor memory device according to the second embodiment is completed through the processes described with reference to.

2 2 51 51 51 c a b According to the second embodiment, slits ST_CELL, ST_LWI, ST_WLC, and ST_WLCare formed in the arrangement direction of the holes H_ST_CELL, H_ST_LWI, H_ST_WLC, and H_ST_WLC. Thereby, a region in the WLHU region Rwlhu where the second insulating filmis replaced with the electrode filmis limited, making it difficult for the first insulating filmto bend in the replacement process. Thus, it is not necessary to provide a support pillar in the WLHU region Rwlhu. That is, in the second embodiment, it is possible to obtain the same effects as in the first embodiment.

51 b According to the second embodiment, the hole H_ST_CELL used to form the slit ST_CELL is provided separately from the hole H_REP used in the replacement process. Thus, the slit ST_CELL can be formed to extend not only to the cell region Rmc but also to the WLHU region Rwlhu. Thereby, the first insulating filmis even less likely to bend during the replacement process.

2 51 51 b c According to the second embodiment, in the WLHU region Rwlhu, the slit ST_WLCis provided between word line contacts WLC adjacent to each other in the X-direction. Thereby, the first insulating filmis even less likely to bend during the replacement process, and the second insulating filmthat is etched through each contact hole H_WLC is limited, making it possible to curb a short circuit between the adjacent word line contacts WLC.

One block BLK has one opening OP and one slit ST_LWI. However, one block BLK may have a plurality of openings OP and a plurality of slits ST_LWI. In this case, the word line contacts WLC may be provided around each slit ST_LWI.

40 FIG. 41 FIG. 40 FIG. 42 FIG. 40 FIG. 40 FIG. 41 42 FIGS.and 41 41 42 42 is a plan view of a semiconductor memory device according to a third embodiment.is a cross-sectional view taken along line A-Ain.is a cross-sectional view taken along line B-Bin.shows a plane at a height level indicated by dashed lines in.

51 2 51 2 1 8 1 8 1 8 51 2 57 57 51 2 51 1 8 51 1 8 27 57 40 FIG. 41 42 FIGS.and a a In the third embodiment, the second stacked body_is processed in a stepped shape in the WLHU region Rwlhu. For example, the second stacked body_has steps STPto STPas shown in. The steps STPto STPdescend in order in the −Z-direction. Above the steps STPto STPof the second stacked body_, the interlayer insulating filmis provided as shown in. The plurality of word line contacts WLC penetrate the interlayer insulating filmprovided on the second stacked body_in the Z-direction to the depths of corresponding electrode films. The plurality of word line contacts WLC correspond to the steps STPto STP, respectively, and are electrically connected to the plurality of electrode filmsdirectly under the steps STPto STPvia the connect layer. Thus, the plurality of word line contacts WLC extend to different depths in the interlayer insulating film.

51 2 51 2 1 3 5 7 2 4 6 8 51 2 1 2 3 4 5 6 7 8 The second stacked body_is processed in a stepped shape in both the X and Y-directions. Thus, the second stacked body_descends in a stepwise manner like the steps STP, STP, STP, and STP, and also descends in a stepwise manner like the steps STP, STP, STP, and STPin the X-direction. Furthermore, the second stacked body_descends like the steps STPand STP, descends like the steps STPand STP, descends like the steps STPand STP, and also descends like the steps STPand STPin the Y-direction.

51 3 51 51 51 1 51 51 51 3 51 3 b a a a The slit ST_LWI includes the plurality of holes H_ST_LWI that penetrate the third stacked body_in the Z-direction and are arranged in the X-direction. The slit ST_LWI is formed by filling a conductive material such as tungsten between first insulating filmsadjacent to each other in the Z-direction through the plurality of holes H_ST_LWI. Thus, the slit ST_LWI is formed to connect the holes H_ST_LWI adjacent to each other in the X-direction with a conductive material. Thus, the slit ST_LWI extends in the X-direction in which the plurality of holes H_ST_LWI are arranged, and electrically connects an electrode filmof the first stacked body_and the word line contact WLC. The electrode filmof the slit ST_LWI functions as a path for connection to the word line contact WLC through the opening OP. That is, the slit ST_LWI (the electrode filmof the third stacked body_) can function in the same manner as in the second embodiment. In addition, the third stacked body_can be formed in the same manner as in the second embodiment using the holes H_ST_LWI.

27 51 51 3 27 27 51 3 57 57 57 27 51 2 a The plurality of word line contacts WLC are connected to the connect layersprovided at the bottoms thereof, and are electrically connected to the corresponding electrode filmsof the third stacked body_through the connect layers. The configurations and formation methods of the word line contact WLC and the connect layermay be the same as those in the second embodiment. However, the hole H_ST_LWI is provided to penetrate the third stacked body_below the interlayer insulating film, but is not provided in the interlayer insulating film. On the other hand, the word line contact WLC is provided to penetrate the interlayer insulating filmto the depth of the connect layer, but is not formed inside the second stacked body_.

41 42 FIGS.and 57 27 5 27 51 27 a For example, as shown in, a word line contact WLCa is formed to penetrate the interlayer insulating filmto the connect layercorresponding to the step STP. The connect layercorresponding to the word line contact WLCa is connected to the electrode film(that is, the word line WL) provided at the same height as the connect layer. Thereby, the word line contact WLCa can control the voltage of the corresponding word line WL.

41 FIG. 57 27 6 27 51 27 a A word line contact WLCb inis formed to penetrate the interlayer insulating filmto the connect layercorresponding to the step STPwhich is one step below the word line contact WLCa. The connect layercorresponding to the word line contact WLCb is connected to the electrode filmprovided at the same height as the connect layer. Thereby, the word line contact WLCb can control the voltage of the corresponding word line WL.

42 FIG. 57 27 7 27 51 27 a A word line contact WLCc inis formed to penetrate the interlayer insulating filmto the connect layercorresponding to the step STPwhich is one step below the word line contact WLCb. The connect layercorresponding to the word line contact WLCc is connected to the electrode filmprovided at the same height as the connect layer. Thereby, the word line contact WLCc can control the voltage of the corresponding word line WL.

1 4 8 Similarly, for the other steps STPto STPand STP, the word line contacts WLC are electrically connected to the corresponding word lines WL. Thereby, the plurality of word line contacts WLC can control the voltages of the corresponding word lines WL.

51 2 57 The third embodiment differs from the second embodiment in that the second stacked body_is processed in a stepped shape in the WLHU region Rwlhu, and the interlayer insulating filmis provided thereon. However, the configurations in the third embodiment substantially correspond to the configurations in the second embodiment. Thus, in the third embodiment, a support pillar is not necessary in the WLHU region Rwlhu, and the same effects as in the second embodiment can be obtained. In addition, a manufacturing method according to the third embodiment can be understood by referring to the manufacturing method according to the second embodiment. Thus, the description of the manufacturing method according to the third embodiment is omitted here.

One block BLK has one opening OP and one slit ST_LWI. However, one block BLK may have a plurality of openings OP and a plurality of slits ST_LWI. In this case, word line contacts WLC may be provided around each slit ST_LWI.

43 44 FIGS.and 44 FIG. 43 FIG. 45 FIG. 44 FIG. 46 FIG. 44 FIG. 44 FIG. 45 46 FIGS.and 45 45 46 46 are plan views of a semiconductor memory device according to a fourth embodiment.shows an enlarged plane of a portion of the structure shown in.is a cross-sectional view taken along line A-Ain.is a cross-sectional view taken along line B-Bin.shows a plane at a height level indicated by dashed lines in.

43 FIG. 11 As shown in, in the fourth embodiment, a WLHU region Rwlhu is provided between a plurality of cell regions Rmc adjacent to each other in the X-direction, and is shared by memory cell arrays.

51 2 51 2 In the fourth embodiment, the WLHU region Rwlhu includes a step portion STP and a bridge portion BRG. The step portion STP is the second stacked body_that is processed in a stepped shape so as to descend from a central portion of the WLHU region Rwlhu toward the cell regions Rmc on both sides. The bridge portion BRG is the second stacked body_that is not processed in a stepped shape and is left to the uppermost layer and connects the plurality of adjacent cell regions Rmc.

11 51 3 51 51 51 3 a a In the fourth embodiment, the word line contact WLC is connected to the slit ST_LWI provided in the bridge portion BRG via the slit ST_LWI provided in the step portion STP. The slit ST_LWI is also provided in the bridge portion BRG, and branches out in the ±X-direction in the bridge portion BRG to be connected to a plurality of adjacent memory cell arrays. The slit ST_LWI includes the hole H_ST_LWI and the third stacked body_provided around the hole H_ST_LWI. The word line contact WLC is electrically connected to the electrode film(i.e., word line WL) of the cell region Rmc via the electrode filmof the third stacked body_.

44 FIG. 45 46 FIGS.and 51 2 1 6 1 6 57 1 6 51 2 57 51 2 51 1 6 51 1 6 27 57 a a For example, as shown in, the second stacked body_has steps STPto STP. The steps STPto STPdescend in order in the −Z-direction. As shown in, the interlayer insulating filmis provided above the steps STPto STPof the second stacked body_. The plurality of word line contacts WLC penetrate the interlayer insulating filmprovided on the second stacked body_in the Z-direction to the depths of the corresponding electrode films. The plurality of word line contacts WLC correspond to the steps STPto STP, respectively, and are electrically connected to the plurality of electrode filmsdirectly under the steps STPto STPvia the connect layer. Thus, the plurality of word line contacts WLC extend to different depths in the interlayer insulating film.

51 2 51 2 1 3 5 2 4 6 51 2 1 2 3 4 5 6 The second stacked body_is processed in a stepped shape in both the X and Y-directions. Thus, the second stacked body_descends in a stepwise manner like the steps STP, STP, and STPin the X-direction, and also descends in a stepwise manner like steps STP, STP, and STP. Furthermore, the second stacked body_descends like the steps STPand STP, descends like the steps STPand STP, and descends like the steps STPand STPin the Y-direction.

51 51 1 51 a a The slit ST_LWI has the same configuration as that in the third embodiment. The slit ST_LWI extends in the X-direction in which the plurality of holes H_ST_LWI are arranged, and electrically connects the electrode filmof the first stacked body_and the word line contact WLC. The electrode filmof the slit ST_LWI functions as a path for connection to the word line contact WLC through the opening OP.

51 2 51 2 51 1 In the fourth embodiment, the slit ST_LWI is provided across the step portion STP, the second stacked body_in the central portion of the WLHU region Rwlhu, and the second stacked body_of the bridge portion BRG. Furthermore, the slit ST_LWI branches out toward the plurality of cell regions Rmc adjacent to each other in the X-direction in the bridge portion BRG, and is connected to both the first stacked bodies_at the openings OP in the plurality of cell regions Rmc. Thereby, the word line contact WLC is electrically connected in common to the corresponding word lines WL in the plurality of adjacent cell regions Rmc.

27 51 51 3 27 27 51 3 57 57 57 27 51 2 a The plurality of word line contacts WLC are connected to the connect layersprovided at the bottoms thereof, and are electrically connected to the corresponding electrode filmsof the third stacked body_through the connect layers. The configurations and formation methods of the word line contact WLC and the connect layermay be the same as those in the second embodiment. However, the hole H_ST_LWI is provided to penetrate the third stacked body_below the interlayer insulating film, but is not provided in the interlayer insulating film. On the other hand, the word line contact WLC is provided to penetrate the interlayer insulating filmto the depth of the connect layer, but is not formed inside the second stacked body_.

45 46 FIGS.and 57 27 3 27 51 27 a For example, as shown in, the word line contact WLCa is formed to penetrate the interlayer insulating filmto the connect layercorresponding to the step STP. The connect layercorresponding to the word line contact WLCa is connected to the electrode film(that is, the word line WL) provided at the same height as the connect layer. Thereby, the word line contact WLCa can control the voltage of the corresponding word line WL.

45 FIG. 57 27 4 27 51 27 a The word line contact WLCb inis formed to penetrate the interlayer insulating filmto the connect layercorresponding to the step STPwhich is one step below the word line contact WLCa. The connect layercorresponding to the word line contact WLCb is connected to the electrode filmprovided at the same height as the connect layer. Thereby, the word line contact WLCb can control the voltage of the corresponding word line WL.

46 FIG. 57 27 5 27 51 27 a The word line contact WLCc inis formed to penetrate the interlayer insulating filmto the connect layercorresponding to the step STPwhich is one step below the word line contact WLCb. The connect layercorresponding to the word line contact WLCc is connected to the electrode filmprovided at the same height as the connect layer. Thereby, the word line contact WLCc can control the voltage of the corresponding word line WL.

1 2 6 27 51 11 a Similarly, for the other steps STP, STP, and STP, the word line contacts WLC are electrically connected to the corresponding word lines WL. That is, the plurality of connect layerselectrically connect the plurality of word line contacts WLC to the plurality of electrode filmsin the adjacent memory cell arrays. Thereby, the plurality of word line contacts WLC can separately control the voltages of the corresponding word lines WL.

The fourth embodiment differs from the third embodiment in the arrangement of the WLHU region Rwlhu, the configuration of the step portion STP, and the configuration of the bridge portion BRG. Thus, the fourth embodiment differs from the third embodiment in the path of the slit ST_LWI that electrically connects the word line contact WLC and the word line WL. However, the other configurations in the fourth embodiment correspond to the configurations in the third embodiment. Thus, also in the fourth embodiment, a support pillar is not necessary in the WLHU region Rwlhu, and the same effects as in the second embodiment can be obtained. Similarly to the third embodiment, a manufacturing method according to the fourth embodiment can be understood by referring to the manufacturing method according to the second embodiment. Thus, the description of the manufacturing method according to the fourth embodiment is omitted here.

While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the disclosure. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the disclosure. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the disclosure.