Dual-Output Switched-Capacitor Power Converter

This application is a continuation of U.S. application Ser. No. 18/909,851, for “DUAL-OUTPUT SWITCHED-CAPACITOR POWER CONVERTER,” filed on Oct. 8, 2024, which is a continuation of U.S. application Ser. No. 17/838,080, for “DUAL-OUTPUT SWITCHED-CAPACITOR POWER CONVERTER,” filed on Jun. 10, 2022, now U.S. Pat. No. 12,136,879, issued Nov. 5, 2024, which claims priority to U.S. provisional patent application Ser. No. 63/210,886, for “DUAL-OUTPUT SWITCHED-CAPACITOR POWER CONVERTER” filed on Jun. 15, 2021 which are all hereby incorporated by reference in their entirety for all purposes.

The described embodiments relate generally to power converters, and more particularly, the present embodiments relate to power converter circuits that employ switched-capacitor circuits.

A wide variety of electronic devices are available for consumers today. Many of these devices have integrated circuits that are powered by regulated low voltage DC power sources. These low voltage power sources are often generated by dedicated power converter circuits that use a higher voltage input from a battery or another power source. In some applications, the dedicated power converter circuit can be one of the largest power dissipating components of the electronic device and can sometimes consume more space than the integrated circuit that it powers. As electronic devices become more sophisticated and more compact, more efficient power converter circuits are called for.

In some embodiments, a circuit is disclosed. The circuit includes a power input terminal, a first output terminal and a second output terminal, a plurality of capacitors coupled to the power input terminal, the first output terminal and the second output terminal, a plurality of switches coupled to the plurality of capacitors and arranged to repetitively cycle the plurality of capacitors between a first configuration and a second configuration to generate a first output voltage at the first output terminal and a second output voltage at the second output terminal. The circuit is arranged to limit a maximum voltage applied to each of the plurality of capacitors to a fraction of a voltage at the power input terminal.

In some embodiments, the circuit is further arranged to limit a maximum voltage applied to each of the plurality of switches to the fraction of a voltage at the power input terminal.

In some embodiments, a value of the fraction is ⅓ or less.

In some embodiments, the circuit is further arranged to limit a maximum voltage swing at a bottom plate or at a top plate of each of the plurality of capacitors to a second fraction of the voltage at the power input terminal.

In some embodiments, the second output voltage has a value that is lower than the first output voltage.

In some embodiments, the plurality of switches are further arranged to connect at least one capacitor from the plurality of capacitors between the first output terminal and the second output terminal such that a current from the first output terminal is circulated to the second output terminal.

In some embodiments, the circuit further includes a wide-band voltage divider.

In some embodiments, the wide-band voltage divider is arranged to provide the first and second output voltages during a start-up time period.

In some embodiments, the wide-band voltage divider is arranged to reduce low-frequency and high-frequency variations in voltage values in the first and second output voltages.

In some embodiments, each of the plurality of switches is a metal-oxide-semiconductor field effect transistor (MOSFET).

In some embodiments, each of the plurality of capacitors is a metal-oxide-semiconductor capacitor.

In some embodiments, each of the plurality of capacitors is a MOSFET capacitor.

In some embodiments, a circuit is disclosed. The circuit includes a power input terminal, a first output terminal and a second output terminal, a plurality of capacitors coupled to the power input terminal, the first output terminal and the second output terminal, a plurality of switches coupled to the plurality of capacitors and arranged to repetitively cycle the plurality of capacitors between a first configuration and a second configuration to generate a first output voltage at the first output terminal and a second output voltage at the second output terminal. The circuit is arranged to limit a maximum voltage applied to each of the plurality of switches to a fraction of a voltage at the power input terminal.

In some embodiments, the circuit is further arranged to limit a maximum voltage applied to each of the plurality of capacitors to the fraction of a voltage at the power input terminal.

In some embodiments, a value of the fraction is ⅓ or less.

In some embodiments, the second output voltage has a value that is lower than the first output voltage.

In some embodiments, the circuit further includes a wide-band voltage divider.

In some embodiments, a circuit is disclosed. The circuit includes a power input terminal, a first output terminal and a second output terminal, a plurality of capacitors coupled to the power input terminal, the first output terminal and the second output terminal, a plurality of switches coupled to the plurality of capacitors and arranged to repetitively cycle the plurality of capacitors between a first configuration and a second configuration to generate a first output voltage at the first output terminal and a second output voltage at the second output terminal. The circuit is arranged to limit a maximum voltage applied to each of the plurality of switches and to each of the plurality of capacitors to a fraction of a voltage at the power input terminal.

In some embodiments, the circuit is further arranged to limit a maximum voltage swing at a bottom plate or at a top plate of each of the plurality of capacitors to a second fraction of the voltage at the power input terminal.

In some embodiments, each of the plurality of switches is a metal-oxide-semiconductor field effect transistor (MOSFET).

Circuits and related techniques disclosed herein relate generally to power converters. More specifically, circuits, devices and related techniques disclosed herein relate to switched-capacitor power converters circuits that have multiple power outputs. In some embodiments, the power converter circuit employs a set of switches that control the charging and discharging of two or more flying capacitors. The set of switches can control the two or more flying capacitors such that the two or more flying capacitors can be selectively charged by a power source in a first time interval and then be selectively coupled to a load in a second time interval. In various embodiments, the power converter circuit can generate two or more output power sources simultaneously to support system-on-chip architectures.

Embodiments of the disclosed power converter circuit architecture can enable operation of the power converter circuit with relatively low voltage stresses across both the set of switches and the two or more capacitors. In this way, switches and capacitors employed in the disclosed power converter circuits can use switches and/or transistors that have relatively small size and use relatively thin oxide. In some embodiments, the disclosed power converter circuits can have lower power loss and higher operating efficiencies. In various embodiments, a dual-output switched-capacitor power converter circuit can have relatively low voltage variations at its outputs by recirculating currents from a high-side output power supply to a low-side output power supply and vice versa.

In some embodiments, the power converter circuits may employ an architecture that enables circulation of current from one output power supply to the other output power supply. This can result in conservation of charge and reduce power losses, while allowing for relatively low voltage variations at the output terminals. Further, the circulating currents can allow the use of a single circuit to generate multiple output power supplies, eliminating a need for multiple independent power converter circuits. In various embodiments, a dual-output switched-capacitor power converter can be utilized in applications that use high-efficiency and extremely fast-response on-chip direct-current to direct-current (DC-DC) converters. These applications can include, but are not limited to, on-chip auxiliary supply rails for drivers of switching regulators and multiple supply voltages for system-on-chip applications. Various inventive embodiments are described herein, including methods, processes, systems, devices, and the like.

Several illustrative embodiments will now be described with respect to the accompanying drawings, which form a part hereof. The ensuing description provides embodiment(s) only and is not intended to limit the scope, applicability, or configuration of the disclosure. Rather, the ensuing description of the embodiment(s) will provide those skilled in the art with an enabling description for implementing one or more embodiments. It is understood that various changes may be made in the function and arrangement of elements without departing from the spirit and scope of this disclosure. In the following description, for the purposes of explanation, specific details are set forth in order to provide a thorough understanding of certain inventive embodiments. However, it will be apparent that various embodiments may be practiced without these specific details. The figures and description are not intended to be restrictive. The word “example” or “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any embodiment or design described herein as “exemplary” or “example” is not necessarily to be construed as preferred or advantageous over other embodiments or designs.

1 FIG. 1 FIG. 100 100 110 112 126 128 154 156 100 114 124 114 124 100 102 104 106 108 116 118 120 122 130 132 134 136 102 104 106 108 170 116 118 120 122 175 130 132 134 136 180 in illustrates a dual-output switched-capacitor power converter circuitaccording to an embodiment of the disclosure. As shown in, circuitcan include four capacitors,,andconnected between an input terminal (V)and ground. Circuitcan also include a first output terminaland a second the second output terminal. The first output terminalmay also be referred to as high-side output terminal. The second output terminalmay also be referred to as low-side output terminal. Circuitcan also include switches,,,,,,,,,and. Switches,,andcan form a first switching matrix, switches,,andcan form a second switching matrixand switches,,andcan form a third switching matrix.

100 119 121 123 125 102 108 116 122 130 136 123 104 106 118 120 132 134 125 114 124 138 142 146 140 144 148 114 124 100 100 114 124 in in in Circuitcan also include a first clock generatorand second clock generator, that generate a first clockand a second clock. Switches,,,,andcan be controlled by the first clock, while switches,,,,andcan be controlled by the second clock. The first clock and the second clock are non-overlapping clocks and typical frequencies may vary from 10 KHZ to 100 MHZ. At the first output terminaland at the second output terminal, resistors,and, and capacitors,, andcan form a wide-band voltage divider configured to set an output voltage at the first output terminalto ⅔ of Vand at the second output terminalto ⅓ of Vduring start-up time period of circuit. A start-up time period can be defined as a time interval prior to the steady state operation of circuit. During a relatively fast start-up period, Vmay rise at a relatively fast rate. As appreciated by one of ordinary skill in the art having the benefit of this disclosure, a value of a voltage at the output terminalsandcan be set to any suitable value as appropriate for specific applications.

100 100 100 100 In some embodiments, circuitcan include a power input terminal, a first output terminal and a second output terminal, a plurality of capacitors coupled to the power input terminal, the first output terminal and the second output terminal, a plurality of switches coupled to the plurality of capacitors and arranged to repetitively cycle the plurality of capacitors between a first configuration and a second configuration to generate a first output voltage at the first output terminal and a second output voltage at the second output terminal. Circuitmay be arranged to limit a maximum voltage applied to each of the plurality of capacitors to a fraction of a voltage at the power input terminal. In various embodiments, circuitmay be arranged to limit a maximum voltage applied to each of the plurality of switches to a fraction of a voltage at the power input terminal. In some embodiments, circuitmay be arranged to limit a maximum voltage applied to each of the plurality of switches and each of the plurality of capacitors to a fraction of a voltage at the power input terminal.

100 138 142 146 114 124 140 144 148 114 124 138 142 146 140 144 148 114 124 100 150 152 114 124 100 in in in in During a relatively slow start-up of circuit, resistors,andmay be used to generate an output voltage at the first output terminalequal ⅔ of Vand at the second output terminalto ⅓ of V. For relatively fast start-up, capacitors,, andmay be utilized to generate an output voltage at the first output terminalequal ⅔ of Vand at the second output terminalto ⅓ of V. Thus, during start-up, resistors,andcan be used to reduce low frequency voltage variations, while capacitors,, andcan used to reduce high frequency voltage variations. In this way, a stable voltage is generated at the output terminalsand. In some embodiments, the voltage variations at the first and second output terminals can be reduced to less than 100 mV for an input voltage at the input terminal of 3.3 V, while in other embodiments the voltage variations may be reduced to less than 10 mV and yet in other embodiments the voltage variations can be reduced to less than 1 mV. Circuitcan include output loads which are depicted as current loadsandconnected to the output terminalsand, respectively. The detailed operation of circuitwill be described in greater detail below.

2 2 FIGS.A andB 2 FIG.A 100 200 200 110 112 126 128 114 124 110 112 126 128 in in in in in in Turning now to, equivalent circuits of steady state operation of circuitare illustrated.shows an equivalent circuitA where the first clock is at a high state and a second clock is at a low state. As can be seen in circuitA, there is a capacitor divider formed by capacitors,,and. Thus, an output voltage at the first output terminalcan be ⅔ of Vand ⅓ of Vat the second output terminal. Each of capacitors,,and, also referred to as flying capacitors, are charged to ⅓ of V. Thus, the voltage stress on each flying capacitor and each switch can be ⅓ of V. For example, if V=3 V, then the voltage stress on each flying capacitor and each switch is 1 V. This can allow the implementation of capacitors and switches using thin-oxide metal-oxide-semiconductor field effect transistors (MOSFET) or metal-oxide-semiconductor (MOS) capacitors in modern short-channel fabrication processes. This implementation can minimize the die area used to generate ⅓ and ⅔ conversion ratios at the same time. As appreciated by one of ordinary skill in the art having the benefit of this disclosure, the value for Vcan be set to any suitable value as appropriate for specific applications. Further, a value of conversion ratios can be set to any suitable value as appropriate for specific applications.

2 FIG.B 200 200 112 110 128 126 114 124 102 104 106 108 116 118 120 122 130 132 134 136 100 114 124 100 in in in in in in in in in in in in 2 shows an equivalent circuitB where the second clock is at a high state and the first clock is at a low state. As can be seen in circuitB, there is a capacitor divider formed by capacitors,,and. Thus, an output voltage at the first output terminalcan be ⅔ of Vand ⅓ of Vat the second output terminal. In this way, the switching capacitors see only a stress voltage of ⅓ of V. Similarly, the voltage stress on switches,,,,,,,,,,andcan be ⅓ of V. As a result, there can be relatively low power loss in the disclosed switched-capacitor power converter because a power loss resulted from parasitic capacitance of switches is C×V; further, because a value for V is ⅓ of Vthe converter can benefit from a reduction of power loss. Circuitcan allow for efficiencies of, for example, 88% at load currents of 5 mA pull-up at the higher voltage at the first output terminaland 5 mA pull-down at the lower voltage output at the second output terminal. As appreciated by one of ordinary skill in the art having the benefit of this disclosure, the value of achievable efficiencies and load currents can vary. Further, circuitcan allow voltage swings at bottom or top plates of each flying capacitor to be ⅓ of V. This low voltage swing can reduce the power loss from the parasitic capacitance at the bottom plates of the flying capacitors. Additionally, a voltage swing at each switch can be between ⅓ of Vand DC levels, for example, between ground to V/3, or between V/3 to 2*V/3, or 2*V/3 to V. Some embodiments may employ drivers and level shifter circuits to control the switches.

3 3 FIGS.A andB 3 FIG.A 100 100 114 124 300 302 114 304 124 Turning now to, a circulating current feature of circuitis illustrated. The circulating current feature of circuitcan enable reduction of voltage variations when there are pull-up loads at the first output terminaland pull-down loads at the second output terminal. Furthermore, the circulating current can eliminate a need for two independent power converter circuits.shows an equivalent circuitA where the first clock is at a high state and the second clock is at a low state, and where a pull-up load resistoris connected to a higher voltage at the first output terminaland a pull-down load resistoris connected to a lower voltage at the second output terminal.

300 302 114 304 124 114 124 114 124 114 124 114 124 124 310 312 124 124 310 312 114 320 310 114 114 320 310 3 FIG.A CircuitA can include a pull-up load resistorconnected at the first output terminaland a pull-down load resistorconnected at the second output terminal. In some embodiments, flying capacitors can be connected between the output terminalsand, thus creating a path for the current flow between output terminalsandas illustrated in. Consequently, there can be cross-regulation between the first output terminaland the second output terminalthat can be useful to reduce output voltage variations at the output terminals. This cross-regulation can balance a strength at the first output terminaland the second output terminalstrength, thus reducing the dropout voltage and reducing power loss at each output terminal. For example, a current flowing out at the second output terminalcan be supplied by currentsand. This can minimize the voltage variations at the second output terminalbecause an output current at the second output terminalcan be supplied partially by currentand partially by current. In some embodiments, the voltage variations at the first and second output terminals can be reduced to less than 100 mV for an input voltage at the input terminal of 3.3 V, while in other embodiments the voltage variations may be reduced to less than 10 mV and yet in other embodiments the voltage variations can be reduced to less than 1 mV. In various embodiments, a current flowing out at the first output terminalcan be supplied by currentsand. This can minimize the voltage variations at the first output terminalbecause an output current at the first output terminalcan be supplied partially by currentand partially by current.

3 FIG.B 3 FIG.B 300 302 114 304 124 114 124 114 124 shows an equivalent circuitB where the second clock is at a high state and the first clock is at a low state, and where a pull-up load resistoris connected to a higher voltage at the first output terminaland a pull-down load resistoris connected to a lower voltage the second output terminal. In some embodiments, flying capacitors can be connected between the two outputs terminalsand, thus creating a path for the current flow between output terminalsandas illustrated in. Consequently, there can be cross-regulation between a high-side output terminal and a low-side output terminal that can be useful to reduce output voltage variations at the output terminals.

114 124 124 314 316 124 124 314 316 114 322 314 114 114 322 314 This cross-regulation can balance a strength at the first output terminaland the second output terminalstrength, thus reducing the dropout voltage and reducing power loss at each output terminal. For example, a current flowing out at the second output terminalcan be supplied by currentsand. This can minimize the voltage variations at the second output terminalbecause an output current at the second output terminalcan be supplied partially by currentand partially by current. As another example, a current flowing out at the first output terminalcan be supplied by currentsand. This can minimize the voltage variations at the first output terminalbecause an output current at the first output terminalcan be supplied partially by currentand partially by current.

Although dual-output switched-capacitor power converter circuits are described and illustrated herein with respect to one particular configuration of switched-capacitor power converter circuits, embodiments of the disclosure are suitable for use with other configurations of switched-capacitor power converters. For example, multiple-output switched-capacitor power converter circuits can employ embodiments of the disclosure to generate various other output voltages at output terminals.

In the foregoing specification, embodiments of the disclosure have been described with reference to numerous specific details that can vary from implementation to implementation. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense. The sole and exclusive indicator of the scope of the disclosure, and what is intended by the applicants to be the scope of the disclosure, is the literal and equivalent scope of the set of claims that issue from this application, in the specific form in which such claims issue, including any subsequent correction. The specific details of particular embodiments can be combined in any suitable manner without departing from the spirit and scope of embodiments of the disclosure.

Additionally, spatially relative terms, such as “bottom or “top” and the like can be used to describe an element and/or feature's relationship to another element(s) and/or feature(s) as, for example, illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and/or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as a “bottom” surface can then be oriented “above” other elements or features. The device can be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

Terms “and,” “or,” and “an/or,” as used herein, may include a variety of meanings that also is expected to depend at least in part upon the context in which such terms are used. Typically, “or” if used to associate a list, such as A, B, or C, is intended to mean A, B, and C, here used in the inclusive sense, as well as A, B, or C, here used in the exclusive sense. In addition, the term “one or more” as used herein may be used to describe any feature, structure, or characteristic in the singular or may be used to describe some combination of features, structures, or characteristics. However, it should be noted that this is merely an illustrative example and claimed subject matter is not limited to this example. Furthermore, the term “at least one of” if used to associate a list, such as A, B, or C, can be interpreted to mean any combination of A, B, and/or C, such as A, B, C, AB, AC, BC, AA, AAB, ABC, AABBCCC, etc.

Reference throughout this specification to “one example,” “an example,” “certain examples,” or “exemplary implementation” means that a particular feature, structure, or characteristic described in connection with the feature and/or example may be included in at least one feature and/or example of claimed subject matter. Thus, the appearances of the phrase “in one example,” “an example,” “in certain examples,” “in certain implementations,” or other like phrases in various places throughout this specification are not necessarily all referring to the same feature, example, and/or limitation. Furthermore, the particular features, structures, or characteristics may be combined in one or more examples and/or features.

In the preceding detailed description, numerous specific details have been set forth to provide a thorough understanding of claimed subject matter. However, it will be understood by those skilled in the art that claimed subject matter may be practiced without these specific details. In other instances, methods and apparatuses that would be known by one of ordinary skill have not been described in detail so as not to obscure claimed subject matter. Therefore, it is intended that claimed subject matter not be limited to the particular examples disclosed, but that such claimed subject matter may also include all aspects falling within the scope of appended claims, and equivalents thereof.