Display Panel and Display Device

This application claims the priority of Chinese Patent Application No. 202411982714.7, filed on Dec. 30, 2024, the content of which is incorporated herein by reference in its entirety.

The present disclosure generally relates to the field of display technology and, more particularly, relates to a display panel and a display device.

Electrostatic protection is one of the main research topics in the display field. Static electricity may damage components in a display panel and affect the display performance of the display panel. How to provide reliable electrostatic protection in the display panel is a technical problem that technicians in this field need to solve urgently.

One aspect of the present disclosure provides a display panel. The display panel includes: The display panel includes first line segments, second line segments, and pixel circuits. At least one end of one first line segment is a cut-off end. Two ends of one second line segment are non-cut-off ends. One second line segment is electrically connected to one corresponding pixel circuit. The display panel has a first area and a second area. The first area is located on a side of the second area close to an edge of the display panel. The pixel circuits are disposed in the second area; and the first line segments are located in the first area.

Another aspect of the present disclosure provides a display device. The display device includes a display panel. The display panel includes: The display panel includes first line segments, second line segments, and pixel circuits. At least one end of one first line segment is a cut-off end. Two ends of one second line segment are non-cut-off ends. One second line segment is electrically connected to one corresponding pixel circuit. The display panel has a first area and a second area. The first area is located on a side of the second area close to an edge of the display panel. The pixel circuits are disposed in the second area; and the first line segments are located in the first area.

Other aspects or embodiments of the present disclosure can be understood by those skilled in the art in light of the description, the claims, and the drawings of the present disclosure.

Reference will now be made in detail to exemplary embodiments of the disclosure, which are illustrated in the accompanying drawings. Hereinafter, embodiments consistent with the disclosure will be described with reference to drawings. In the drawings, the shape and size may be exaggerated, distorted, or simplified for clarity. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts, and a detailed description thereof may be omitted. Further, in the present disclosure, the disclosed embodiments and the features of the disclosed embodiments may be combined under conditions without conflicts. It is apparent that the described embodiments are some but not all of the embodiments of the present disclosure. Based on the disclosed embodiments, persons of ordinary skill in the art may derive other embodiments consistent with the present disclosure, all of which are within the scope of the present disclosure.

Moreover, the present disclosure is described with reference to schematic diagrams. For the convenience of descriptions of the embodiments, the cross-sectional views illustrating the device structures may not follow the common proportion and may be partially exaggerated. Besides, those schematic diagrams are merely examples, and not intended to limit the scope of the disclosure. Furthermore, a three-dimensional (3D) size including length, width, and depth should be considered during practical fabrication.

In the present disclosure, terms such as “center”, “longitudinal”, “lateral”, “length”, “width”, “thickness”, “up”, “down”, “front”, “back”, “left”, “right”, “vertical”, “horizontal”, “top”, “bottom”, “inside”, “outside”, “clockwise”, “counterclockwise”, “axial”, “radial”, “circumferential”, etc., indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present disclosure.

In the present disclosure, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship between these entities or operations or order. Moreover, the terms “including”, “comprising” or any other variants thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device that includes a series of elements includes not only those elements, but also those that are not explicitly listed or also include elements inherent to this process, method, article or equipment. If there are no more restrictions, the elements defined by the sentence “including . . . ” do not exclude the existence of other same elements in the process, method, article, or equipment that includes the elements.

It should be understood that when describing the structure of a component, when a layer or region is referred to as being “on” or “above” another layer or another region, the layer or region may be directly on the other layer or region, or indirectly on the other layer or region, for example, layers/components between the layer or region and another layer or another region. And, for example, when the component is reversed, the layer or region may be “below” or “under” the other layer or region. In the present disclosure, the term “electrical connection” refers to that two components are directly electrically connected with each other, or the two components are electrically connected via one or more other components.

In the present disclosure, unless otherwise clearly specified and limited, the terms “installed”, “connected”, “fixed” and the like appear, should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integrated connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For those skilled in the art, the specific meanings of the above terms in the present disclosure can be understood according to the specific circumstances.

In the present disclosure, when an element is referred to as being “fixed to” or “disposed on” another element, it may be directly on the other element or there may be an intermediate element. When an element is considered to be “connected to” another element, it may be directly connected to the other element or there may be an intermediate element at the same time. If present, the terms “vertical”, “horizontal”, “upper”, “lower”, “left”, “right” and similar expressions are for illustrative purposes only and are not intended to be the only embodiment.

1 FIG. 1 2 10 1 1 1 2 2 2 10 The present disclosure provides a display panel. In one embodiment shown inwhich is a top view of a display panel provided by the present embodiment, the display panel may include first line segments D, second line segments D, and pixel circuits. For one first line segment D, one end of the first line segment Dmay be a cut-off end, and another end of the first line segment Dmay be connected to one corresponding second line segment D. For one the second line segment D, two ends may be non-cut-off ends, and the second line segment Dmay be electrically connected to one corresponding pixel circuit.

1 FIG. 1 1 1 2 1 2 1 2 1 1 1 1 2 1 1 2 1 1 As shown in, the display panel may also include first signal lines S, and one first signal line Smay include first line segments Dand second line segments D. That is, the first line segments Dand the second line segments Dmay be two portions of segments in the first signal line S, the second line segments Dare the middle segments of the first signal line S, and the first line segments Dare segments at two ends of the first signal line S. The first line segments Dand the second line segments Dmay be connected. For one first line segment D, one end of the first line segment Daway from one corresponding second line segment Dmay be the cut-off end, and the cut-off end of the first line segment Dmay be also the cut-off end of the corresponding first signal line S.

2 10 1 2 1 1 10 1 10 Since the second line segment Dis electrically connected to the corresponding pixel circuitand the first line segment Dis connected to the corresponding second line segment D, the first signal line Sand the first line segment Dmay also be electrically connected to the corresponding pixel circuit. The first signal line Smay be used to transmit a signal to the corresponding pixel circuit.

2 FIG. 2 FIG. 20 10 20 10 20 shows a partial top view schematic diagram of a display panel consistent with the present disclosure. As shown in, in one embodiment, the display panel may include light-emitting elements, and one pixel circuitmay be electrically connected to one corresponding light-emitting elementaccordingly. The pixel circuitmay be used to drive the light-emitting diodeto emit light.

20 100 100 10 100 100 200 200 20 200 200 100 200 2 FIG. 2 FIG. Optionally, in one embodiment, the light-emitting elementmay be an organic light-emitting diode (OLED), or a micro light-emitting diode such as a sub-millimeter light-emitting diode (Mini-LED) or a micro light-emitting diode (Micro-LED). As shown in, the display panel may include pixel circuit groups, and one pixel circuit groupmay include at least two pixel circuits. The pixel circuit groupsmay be arranged in a row along a first direction X, and multiple rows of pixel circuit groupsmay be arranged along a second direction Y. The first direction X and the second direction Y may intersect, and the first direction X and the second direction Y may be parallel to the plane where the display panel is located. Correspondingly, as shown in, the display panel may also include light-emitting element groups, one light-emitting element groupmay include at least two light-emitting elements, the light-emitting element groupsmay be also arranged in a row along the first direction X, and multiple rows of light-emitting element groupsmay also be arranged along the second direction Y. The pixel circuit groupsand the light-emitting element groupsmay be electrically connected accordingly.

2 FIG. 2 FIG. 20 21 22 23 21 22 23 200 21 22 23 100 11 21 12 22 13 23 As shown in, the light-emitting elementsmay include first light-emitting elements, second light-emitting elementsand third light-emitting elements. The first light-emitting elementsmay be used to emit red light, the second light-emitting elementsmay be used to emit green light, and the third light-emitting elementsmay be used to emit blue light. One light-emitting element groupmay include one first light-emitting element, one second light-emitting elementand one third light-emitting element. Correspondingly, as shown in, one pixel circuit groupmay include a first pixel circuitfor driving the first light-emitting elementto emit light, a second pixel circuitfor driving the second light-emitting elementto emit light, and a third pixel circuitfor driving the third light-emitting elementto emit light.

10 20 30 30 10 To enable the pixel circuitsto drive the light-emitting elementsto emit light, the display panel may also include driving circuits, and one driving circuitmay be used to provide a driving signal to one corresponding pixel circuit.

3 FIG. 3 FIG. 30 30 30 10 1 30 30 shows a schematic top view of an existing display panel. As shown in, the display panel includes a display area AA and a non-display area NA at least partially surrounding the display area AA. The driving circuitsare located in the non-display area NA, and the driving circuitsare located on at least one side of the display area AA along the first direction X. The driving circuitsprovides a driving signal to each row of pixel circuitsthrough a signal line Sextending along the first direction X. It can be seen that the driving circuitsoccupies the left frame area and/or the right frame area of the display panel. With the continuous development of display technology, narrow frame display, extremely narrow frame display and borderless display have gradually become mainstream displays. Based on this, at least one driving circuitmay be disposed in the display area AA to achieve a narrow frame, an extremely narrow frame or even a borderless design.

1 FIG. 2 FIG. 2 FIG. 10 20 30 30 10 10 20 10 20 100 200 100 200 As shown inand, in the display panel provided by some embodiments of the present disclosure, the display area AA may include not only the pixel circuitsand the light-emitting elements, but also at least one driving circuit. Further, to arrange the at least one driving circuitin the display area AA, considering that the pixel circuitsneeds to have a certain distance from the frame of the display panel, as shown in, in the edge area of the display area AA, the pixel circuitand the corresponding electrically connected light-emitting elementmay not overlap in the direction perpendicular to the plane where the display panel is located, and, in the middle area of the display area AA, the pixel circuitand the corresponding electrically connected light-emitting elementmay at least partially overlap in the direction perpendicular to the plane where the display panel is located. In other words, in the edge area of the display area AA, the pixel circuit groupand the corresponding electrically connected light-emitting element groupmay not overlap in the direction perpendicular to the plane where the display panel is located, and, in the middle area of the display area AA, the pixel circuit groupand the corresponding electrically connected light-emitting element groupmay at least partially overlap in the direction perpendicular to the plane where the display panel is located, such that a display panel with a narrow frame, an extremely narrow frame or even no frame is realized.

1 FIG. 30 31 31 10 31 100 As shown in, the driving circuitmay include shift register circuitsin a multi-stage cascade arrangement. Optionally, the shift register circuitsmay be located between different columns of pixel circuits, or in other words, the shift register circuitsmay be located between different columns of pixel circuit groups.

4 FIG. 4 FIG. 31 10 31 100 shows a top view of another display panel provided by an embodiment of the present disclosure. As shown in, in another embodiment, the shift register circuitsmay be located between different rows of pixel circuits, or in other words, the shift register circuitsmay be located between different rows of pixel circuit groups.

5 FIG. 1 FIG. 5 FIG. 5 FIG. 10 30 30 1 2 3 1 1 1 10 1 2 2 2 10 2 3 10 1 2 1 2 1 2 1 10 For better understanding,shows a schematic diagram of an electrical connection relationship between the pixel circuitsand the driving circuitsin the CC′ area of the display panel shown in. As shown in, one driving circuitmay include a scanning circuit STV, a scanning circuit STVand a light-emitting control circuit STV. The scanning circuit STVmay include a shift register circuit Scanarranged in a multi-stage cascade, and the shift register circuit Scanis electrically connected to one corresponding pixel circuitthrough a scanning signal line SNextending along a first direction X; the scanning circuit STVincludes a shift register circuit Scanarranged in a multi-stage cascade, and the shift register circuit Scanmay be electrically connected to one corresponding pixel circuitthrough a scanning signal line SNextending along the first direction X. The light-emitting control circuit STVmay include a shift register circuit Emit arranged in a multi-stage cascade, and the shift register circuit Emit may be electrically connected to the corresponding pixel circuitthrough a light-emitting control signal line EM extending along the first direction X. Further, as shown in, the display panel may further include a reference voltage signal line Vrefand a reference voltage signal line Vref. The reference voltage signal line Vrefmay extend along a first direction X, the reference voltage signal line Vrefmay extend along the second direction Y. The reference voltage signal line Vrefand the reference voltage signal line Vrefmay be electrically connected, and the reference voltage signal line Vrefmay be electrically connected to the pixel circuit.

6 FIG. 6 FIG. 6 FIG. 10 10 1 2 3 4 5 6 7 10 1 2 1 10 20 20 shows a schematic diagram of a circuit structure of one pixel circuit. As shown in, in one embodiment, the pixel circuitmay be a 7T1C structure, and may include a first light emission control transistor T, a data writing transistor T, a driving transistor T, a compensation transistor T, a gate reset transistor T, a second light emission control transistor T, an anode reset transistor T, and a storage capacitor Cst. The signal lines electrically connected to the pixel circuitmay include a scanning signal line SN, a scanning signal line SN, a light emission control signal line EM, a reference voltage signal line Vref, a data signal line data, and a power supply voltage line PVDD. The pixel circuitmay be electrically connected to one electrode of the light-emitting element, and the other electrode of the light-emitting elementmay be electrically connected to the power supply voltage line PVEE. The electrical connection relationship between the transistors in the 7T1C pixel circuit and the electrical connection relationship between the transistors and the signal lines are shown inand will not be described in detail.

10 6 FIG. The pixel circuitshown inis only used as an example to illustrate the present disclosure, and does not limit the scope of the present disclosure. In practical applications, pixel circuits of other circuit structures may be selected based on demand.

1 FIG. 3 FIG. 3 FIG. 4 FIG. 30 30 10 30 30 30 30 10 Comparingand, and comparingand, it may be seen that, in the existing display panel, since the driving circuitsare located on at least one side of the display area AA along the first direction X, the signal lines electrically connecting the driving circuitsand each row of pixel circuitsextending along the first direction X are cut off at the driving circuits, that is, there are no cut-off ends. After the driving circuitsare set in the display area AA, since the driving circuitsare located in the display area AA, the two ends of the signal line electrically connecting the driving circuitsand each row of pixel circuitsextending along the first direction X may become cut-off ends.

1 FIG. 4 FIG. 1 Optionally, as shown inand, the first signal line Smay extend along the first direction X.

5 FIG. 6 FIG. 1 31 1 30 10 1 1 10 1 1 2 10 2 1 10 Further optionally, as shown inand, in one embodiment, the first signal line Smay be electrically connected to the shift register circuit, that is, the first signal line Smay be a functional signal line electrically connecting the driving circuitand the corresponding pixel circuit. For example, the first signal line Smay be a scanning signal line SNelectrically connecting the pixel circuitand the shift register circuit Scan. For another example, the first signal line Smay also be a scanning signal line SNelectrically connecting the pixel circuitand the shift register circuit Scan. For another example, the first signal line Smay also be a light-emitting control signal line EM electrically connecting the pixel circuitand the shift register circuit Emit.

1 FIG. 4 FIG. 5 FIG. 1 1 1 1 As shown in,and, the reference voltage line Vrefmay also extend along the first direction X, and two ends of the reference voltage line Vrefmay also be cut-off ends. Therefore, further alternatively, the first signal line Smay also be a reference voltage line Vrefextending along the first direction X.

5 FIG. 1 2 1 2 10 1 It should be noted that, as shown in, for the reference voltage line Vrefextending along the first direction X, the reference voltage line Vrefextending along the second direction Y may also need to be electrically connected to the reference voltage line Vrefextending along the first direction X, and the reference voltage line Vrefextending along the second direction Y may be electrically connected to the pixel circuitthrough the reference voltage line Vrefextending along the first direction X.

5 FIG. 2 2 1 2 2 10 1 10 1 1 2 2 That is, as shown in, the display panel may also include a second signal line S, the second signal line Smay extend along the second direction Y, the first signal line Sand the second signal line Smay be electrically connected, and the second signal line Smay be electrically connected to the pixel circuitthrough the first signal line Sto provide a signal to the pixel circuit. For example, the first signal line Smay be the reference voltage line Vrefextending in the first direction X, and the second signal line Smay be the reference voltage line Vrefextending in the second direction Y.

1 2 1 The signal line including the first signal line Sand the second signal line Smay be referred to as a direct driving signal line, and the first signal line Smay also be a portion of the direct driving signal line extending along the first direction X. It should be noted that the direct driving signal line is not limited to the reference voltage line. For example, the light-emitting control signal line Emit may also be set as a direct driving signal line.

1 FIG. 4 FIG. 1 2 1 2 1 2 2 Through the above analysis, it may be understood that, as shown inand, the display area AA of the display panel may include a first area Aand a second area A. The first area Amay be located on a side of the second area Aclose to the edge of the display panel. For example, the first area Amay be located on a side of the second area Aclose to the edge of the display panel along the first direction X. The second area Amay

10 2 30 1 1 1 2 include a pixel circuit. The second area Amay also include at least one driving circuit. The first signal line Smay extend along the first direction X. The first signal line Smay include a first line segment Dand a second line segment Dconnected to each other. The

2 1 2 1 1 1 1 1 2 1 1 1 second line segment Dof the first signal line Smay be located in the second area A, and the first line segment Dof the first signal line Smay be located in the first area A. In the first signal line S, the end of the first line segment Daway from the second line segment Dmay be the cut-off end, and the cut-off end of the first line segment Dmay be the cut-off end of the first signal line S. Therefore, electrostatic charge may be accumulated through the cut-off end of the first line segment Dlocated in the edge area of the display panel, to prevent static electricity from damaging the components in the edge area close to the display panel and perform reliable electrostatic protection in the display panel.

1 1 1 10 10 1 FIG. 4 FIG. The ability of the cut-off end of the first signal line Sto accumulate electrostatic charge may be relatively limited. The cut-off end of the first signal line Smay be in a long-line cut-off state, and the carrying capacity of the electrostatic charge may be relatively large. When the cut-off end of the first signal line Sis electrostatically released, it may be possible to cause electrostatic damage to the transistor devices in the pixel circuitsclose to the edge of the display panel along the first direction X (for example, the transistor devices in the pixel circuitson the leftmost and rightmost sides ofand), and these transistor devices may be susceptible to threshold shift or characteristic failure under the influence of static electricity, which may cause abnormal display of the corresponding pixels.

1 10 1 Also, the ability of the cut-off end of the first signal line Sto accumulate electrostatic charge may be improved to protect the transistor devices in the pixel circuitsclose to the edge of the display panel along the first direction X from electrostatic damage and improve the reliability of electrostatic protection of the cut-off end of the first signal line S.

7 FIG. 7 FIG. 1 1 1 1 1 1 Optionally, in some embodiments shown inwhich is a partial top view schematic diagram of another display panel, in a direction perpendicular to the extension direction of the first signal line S(such as the second direction Y in), the width of the cut-off end of the first signal line Smay be larger than the width of other portions of the first signal line Sexcept the cut-off end. In other words, by increasing the width of the cut-off end of the first signal line Sin the direction perpendicular to the extension direction of the first signal line S, the ability of the cut-off end of the first signal line Sto accumulate electrostatic charge may be improved.

7 FIG. 1 1 1 As shown in, in one embodiment, the cut-off end of the first signal line Smay be in an arc shape. With such a setting, the cut-off end of the first signal line Dmay be relatively smooth, which may reduce the tip discharge and further improve the ability of the cut-off end of the first signal line Sto accumulate electrostatic charge.

8 FIG. 7 FIG. 8 FIG. 1 1 1 1 In one embodiment shown inwhich is an enlarged schematic diagram of the KK′ region in, in the direction perpendicular to the extension direction of the first signal line S(such as the second direction Y in), the width W of the cut-off end of the first signal line Sand the width a of the other portions of the first signal line Sexcept the cut-off end may satisfy: W≥2a. With such a setting, the ability of the cut-off end of the first signal line Sto accumulate electrostatic charge may be further improved.

1 1 1 1 In addition to increasing the width of the cut-off end of the first signal line Sin the direction perpendicular to the extension direction of the first signal line Sto improve the ability of the cut-off end of the first signal line Sto accumulate electrostatic charge, the cut-off end of the first signal line Smay also be designed as a divergent structure.

9 FIG. 9 FIG. 10 1 1 11 12 12 11 11 2 1 1 1 In one embodiment shown inwhich is a partial top view schematic diagram of another display panel and FIGfurther showing an enlarged schematic diagram of the KK′ region in, in the first signal line S, the first line segment Dmay include a main body Dand a bifurcated portion Dextending in different directions. The bifurcated portion Dmay be connected to the main body D, and the main body Dmay be connected to the second line segment D. In this way, the cut-off end of the first signal line Smay be a plurality of bifurcated structures, which may increase the path for the cut-off end of the first signal line Sto accumulate electrostatic charges, thereby improving the ability of the cut-off end of the first signal line Sto accumulate electrostatic charges.

8 FIG. 10 FIG. 1 1 1 Comparingand, it may be understood that, compared with designing the cut-off end of the first signal line Sas a plurality of bifurcated structures, designing the cut-off end of the first signal line Sas an arc shape may make the cut-off end of the first signal line Soccupy a smaller space.

11 FIG. 12 FIG. 1 2 3 In one embodiment shown inwhich is a schematic diagram of a partial cross-sectional structure of a display panel andwhich is a schematic diagram of a partial cross-sectional structure of another display panel, the display panel may include a substrate sub, an active layer py located on one side of the substrate sub, and a multi-layer metal layer located on the side of the active layer py away from the substrate sub. The multi-layer metal layer may include a metal layer M, a metal layer MC, a metal layer M, a metal layer M, and a metal layer RE arranged in a direction away from the substrate sub. Different metal layers, and the metal layer and the active layer may be isolated by insulating layers.

11 FIG. 12 FIG. 10 30 1 2 10 1 2 1 1 20 10 10 20 As shown inand, the pixel circuitsand the driving circuitsmay be located on the substrate sub, mainly distributed in the active layer py and some metal layers (such as the metal layer M, metal layer MC and metal layer M). The signal lines electrically connected to the pixel circuitssuch as the scanning signal lines SN, scanning signal lines SNand the reference voltage signal lines Vrefmay be located in some metal layers (such as the metal layer Mand metal layer MC). The light-emitting elementsmay be located on the side of the pixel circuitsaway from the substrate sub, and the pixel circuitsmay drive the light-emitting elementsto emit light.

11 FIG. 12 FIG. 1 As shown inand, the first signal line Smay be located in a metal layer among the multiple metal layers.

1 30 10 1 1 2 1 1 11 FIG. As known from the foregoing, the first signal line Smay be a functional signal line electrically connecting the driving circuitand the corresponding pixel circuit. For example, the first signal line Smay be a scanning signal line SN, a scanning signal line SNor a light-emitting control signal line EM. Optionally, as shown in, the first signal line Smay be located in the metal layer M.

1 1 1 1 12 FIG. As known from the foregoing, the first signal line Smay also be a portion of the direct driving signal line extending along the first direction X. For example, the first signal line Smay be a reference voltage line Vrefextending along the first direction X. Optionally, as shown in, the first signal line Smay be located in the metal layer MC.

1 1 1 1 10 In the display panel, the signal lines extending along the first direction X may be mostly located in the metal layer Mor the metal layer MC. When the metal layer Mor the metal layer MC is prepared, since the upper metal layer is not formed, the cut-off end of the first signal line Sextending along the first direction X located in the metal layer Mor the metal layer MC may be likely to carry a large amount of static electricity, which is likely to cause electrostatic damage to the pixel circuitnear the edge of the display panel along the first direction X.

1 1 1 1 1 1 10 1 In addition to increasing the width of the cut-off end of the first signal line Sin the direction perpendicular to the extension direction of the first signal line Sand designing the cut-off end of the first signal line Sas a divergent structure to improve the ability of the cut-off end of the first signal line Sto accumulate electrostatic charges, in the second aspect, a sacrificial structure for releasing static electricity may be set at the cut-off end of the first signal line S. Therefore, the static electricity is preferentially released at the sacrificial structure when the electrostatic charge accumulated at the cut-off end of the first signal line Sis too much, thereby protecting the transistor devices in the pixel circuitnear the edge of the display panel along the first direction X from electrostatic damage, and improving the reliability of electrostatic protection at the cut-off end of the first signal line S.

11 FIG. 12 FIG. 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Optionally, in some embodiments of the present disclosure, as shown inand, the display panel may further include a first conductive portion B, and the first conductive portion Band the first signal line Smay be arranged in different layers. In a direction Z perpendicular to the plane where the display panel is located, the first conductive portion Band the first line segment Din the first signal line Smay at least partially overlap, and an insulating layer may be disposed between the first conductive portion Band the first line segment Din the first signal line S. With such a configuration, when too much electrostatic charge is accumulated at the cut-off end of the first signal line S, the insulating layer between the first conductive portion Band the first line segment Din the first signal line Smay be broken down, and the electrostatic charge may be discharged to the first conductive portion B.

13 FIG. 14 FIG. 13 FIG. 1 1 1 1 1 1 1 1 1 1 1 10 1 1 10 1 10 1 1 1 1 1 1 In some embodiments shown inwhich illustrates a partial top view schematic diagram of another display panel andwhich is an enlarged schematic diagram of the KK′ area in, in the direction perpendicular to the plane where the display panel is located, the cut-off end of the first signal line Smay not overlap with the first conductive portion B. In the direction perpendicular to the plane where the display panel is located, the first conductive portion Bmay at least partially overlap with the first line segment Din the first signal line S, and the cut-off end of the first signal line S(that is, the cut-off end of the first line segment D) may not overlap with the first conductive portion B. That is, the first conductive portion Bmay be located on the inner side of the cut-off end of the first signal line S, and the first conductive portion Bmay be located on the side of the pixel circuitclose to the edge of the cut-off end of the first signal line S. Therefore, when too much electrostatic charge is accumulated at the cut-off end of the first signal line Sand may be discharged toward the pixel circuitclose to the edge, the electrostatic charge may be discharged to the first conductive portion Bfirst, which may more effectively protect the transistor devices in the pixel circuitclose to the edge of the display panel along the first direction X from electrostatic damage. Further, in the direction perpendicular to the plane where the display panel is located, the cut-off end of the first signal line Smay not overlap with the first conductive portion B, and the ability of the cut-off end of the first signal line Sto accumulate electrostatic charge may be fully utilized. That is to say, such a configuration may make the cut-off end of the first signal line Saccumulate enough electrostatic charge within the electrostatic bearing range, and then release the electrostatic charge to the first conductive portion B, further improving the reliability of electrostatic protection of the cut-off end of the first signal line S.

1 1 1 1 10 1 Optionally, in some other embodiments, in the direction perpendicular to the plane where the display panel is located, the cut-off end of the first signal line Smay also overlap with the first conductive portion Bat least partially, such that the charge may also be electrostatically released to the first conductive portion Bafter the electrostatic charge accumulated at the cut-off end of the first signal line Sexceeds a certain degree, thereby protecting the transistor devices in the pixel circuitclose to the edge of the display panel along the first direction X from electrostatic damage, and improving the reliability of electrostatic protection of the cut-off end of the first signal line S.

11 FIG. 12 FIG. 1 1 1 1 1 1 1 1 1 1 Optionally, in some embodiments, as shown inand, the first conductive portion Bmay be located between the metal layer where the first signal line Sis located and the base substrate sub. In this way, the first conductive portion Bmay be first formed on the base substrate sub, and then the first signal line Smay be formed on the side of the first conductive portion Baway from the base substrate sub, such that the charge may be released to the first conductive portion Bwhen a large amount of electrostatic charge is accumulated at the cut-off end of the first signal line Sduring the preparation of the metal layer where the first signal line Sis located, thereby improving the preparation yield of the display panel. Also, during the use of the display panel, the electrostatic charge accumulated at the cut-off end of the first signal line Smay also be released to the first conductive portion B.

1 1 1 1 Optionally, in some other embodiments, the first conductive portion Bmay also be located on a side of the metal layer where the first signal line Sis located away from the substrate sub. In this way, during the use of the display panel, the electrostatic charge accumulated at the cut-off end of the first signal line Smay be released to the first conductive portion B.

1 1 1 1 1 11 FIG. 12 FIG. On the basis that the first conductive portion Bmay be located between the metal layer where the first signal line Sis located and the substrate sub, considering that the first signal line Smay be located in the metal layer Mor the metal layer MC, optionally, in some embodiments, as shown inand, the first conductive portion Bmay be located in the active layer py.

15 FIG. 1 11 11 11 1 In one embodiment shown inwhich is an enlarged schematic diagram of a local edge area of a display panel along the first direction X, the first conductive portion Bmay include at least one first sub-conductive portion B, and the first sub-conductive portion Bmay extend along the second direction Y. In the direction perpendicular to the plane where the display panel is located, the first sub-conductive portion Bmay overlap with the first line segment D.

1 1 11 11 11 11 10 1 It may be understood that, when the first line segment Din the first signal line Sperforms electrostatic discharge to the first sub-conductive portion Bthat overlaps in the direction perpendicular to the plane where the display panel is located, the corresponding first sub-conductive portion Bmay be actually electrostatically damaged, that is, the corresponding first sub-conductive portion Bmay be used as a sacrificial structure for electrostatic discharge. Therefore, by increasing the number of first sub-conductive portions B, the transistor devices in the pixel circuitnear the edge of the display panel may be further protected from electrostatic damage, thereby improving the reliability of electrostatic protection at the cut-off end of the first signal line S.

16 FIG. 16 FIG. 1 11 11 1 11 11 1 11 10 1 In one embodiment inwhich shows an enlarged schematic diagram of a local edge area of another display panel provided in an embodiment of the present application along the first direction X, the first conductive portion Bmay include at least two first sub-conductive portions B, and the first sub-conductive portions Bmay be arranged along the first direction X. For example, in one embodiment, the first conductive portion Binmay include three first sub-conductive portions B, and the three first sub-conductive portions Bmay be arranged along the first direction X. In this way, when the cut-off end of the first signal line Saccumulates a large amount of electrostatic charge, the electrostatic charge may be discharged to the first sub-conductive portions Barranged along the first direction X in sequence, to further protect the transistor devices in the pixel circuitclose to the edge of the display panel along the first direction X from electrostatic damage and improve the reliability of electrostatic protection of the cut-off end of the first signal line S.

1 11 1 12 11 12 14 FIG. 17 FIG. On the basis that the first conductive portion Bincludes at least two first sub-conductive portions Barranged along the first direction X, as shown inandwhich is an enlarged schematic diagram of a local edge area of another display panel along the first direction X, the first conductive portion Bmay also include a second sub-conductive portion Bconnecting two adjacent first sub-conductive portions B, and the second sub-conductive portion Bmay extend along the first direction X.

14 FIG. 1 11 12 11 1 Optionally, as shown in, the first conductive portion Bmay include two first sub-conductive portions Band a second sub-conductive portion Bconnecting the two first sub-conductive portions B, such that the first conductive portion Bis U-shaped.

17 FIG. 18 FIG. 1 11 12 11 1 1 11 12 11 1 Alternatively, as shown in, the first conductive portion Bmay include three first sub-conductive portions Band two second sub-conductive portions Bconnecting any two adjacent first sub-conductive portions B, such that the first conductive portion Bis S-shaped. In addition, as shown inwhich is an enlarged schematic diagram of a local edge area of another display panel along the first direction X, when the first conductive portion Bincludes three first sub-conductive portions Band two second sub-conductive portions Bconnecting two adjacent first sub-conductive portions B, the first conductive portion Bmay also be M-shaped.

1 11 12 11 1 In some other embodiments, the first conductive portion Bmay also include more than three first sub-conductive portions Band multiple second sub-conductive portions Bconnecting two adjacent first sub-conductive portions B, and the first conductive portion Bmay be in other suitable shapes.

2 10 30 10 30 2 1 1 10 30 1 1 1 1 1 1 1 1 1 1 11 FIG. 12 FIG. From the above analysis, it may be seen that the second area Aof the display panel (the middle area of the display area AA) may include pixel circuitsand at least one driving circuit. The pixel circuitsand the driving circuitsmay both include multiple thin film transistors, that is, the second area Aof the display panel may include multiple thin film transistors. As shown inand, the multiple thin film transistors may include a first transistor TFT. The first transistor TFTmay be a thin film transistor in the pixel circuitor a thin film transistor in the driving circuit. The first transistor TFTmay include a channel region plocated in the active layer py. In the direction Z perpendicular to the plane where the display panel is located, the channel region pof the first transistor TFTmay overlap with the first signal line S. The portion of the first signal line Soverlapping with the channel region pof the first transistor TFTmay be the gate gof the first transistor TFT.

11 FIG. 12 FIG. 1 1 11 1 2 1 1 1 1 2 1 11 1 1 1 As shown inand, along the extension direction of the first signal line S, that is, along the first direction X, the width wof the first sub-conductive portion Boverlapping with the first signal line Sin the direction Z perpendicular to the plane where the display panel is located may be larger than the width wof the channel region pof the first transistor TFToverlapping with the first signal line Sin the direction Z perpendicular to the plane where the display panel is located, that is, w>w. In this way, when a large amount of electrostatic charge accumulates at the cut-off end of the first signal line S, the charge may be preferentially released to the first sub-conductive portions B, and may not be preferentially released to the first transistor TFTclose to the edge of the display panel along the first direction X, to better protect the first transistor TFTclose to the edge of the display panel along the first direction X from electrostatic damage, and improve the reliability of electrostatic protection at the cut-off end of the first signal line S.

2 1 1 1 1 11 1 In practical applications, the width wof the channel region pof the first transistor TFToverlapping with the first signal line Sin the direction Z perpendicular to the plane where the display panel is located may be less than or equal to 4 μm. In this case, the width wof the first sub-conductive portion Boverlapping with the first signal line Sin the direction Z perpendicular to the plane where the display panel is located may be set to be greater than or equal to 4 μm.

1 1 1 1 1 1 1 1 1 1 Optionally, in some embodiments, the shape of the first conductive portion Bmay be the same as the shape of the channel region pof the first transistor TFTclosest to the first conductive portion Balong the extension direction of the first signal line S(i.e., along the first direction X). For example, the shape of the channel region pof the first transistor TFTclosest to the first conductive portion Balong the extension direction of the first signal line S(i.e., along the first direction X) may be a rectangle, and the shape of the first conductive portion Bmay be a rectangle.

1 1 1 1 1 Optionally, in other embodiments, the shape of the first conductive portion Bmay be different from the shape of the channel region pof the first transistor TFTclosest to the first conductive portion Balong the extension direction of the first signal line S(i.e., along the first direction X).

7 FIG. 10 FIG. 13 FIG. 18 FIG. 1 1 2 1 1 1 1 1 1 For example, as shown intoandto, the first signal line Smay include multiple types of first signal lines, and the multiple types of first signal lines may include scan signal lines SN, scan signal lines SN, and reference voltage signal lines Vref. The first conductive portions Bof different types of first signal lines Sthat overlap in the direction perpendicular to the plane where the display panel is located may have the same shape. Thus, when preparing the first conductive portions Bof different types of first signal lines Sthat overlap in the direction perpendicular to the plane where the display panel is located, the same mask pattern may be used to simplify the layout design of the display panel. Moreover, as long as the shape design of the first conductive portion Bis sufficient to protect the transistor devices near the edge of the display panel along the first direction X from electrostatic damage, it may be fine.

14 FIG. 18 FIG. 1 1 2 1 1 1 1 1 1 As shown into, the first signal line Smay include multiple types of first signal lines, for example, a scanning signal line SN, a scanning signal line SN, a light-emitting control signal line EM and a reference voltage line Vref. The different types of first signal lines Smay be arranged along the second direction Y. Along the second direction Y, a distance H between the first conductive portions Bthat overlap with two adjacent types of first signal lines Sin the direction perpendicular to the plane where the display panel is located may satisfy: H≥5 μm. In this way, electrostatic breakdown may be prevented between the first conductive portions Bthat overlap with two adjacent types of first signal lines Sin the direction perpendicular to the plane where the display panel is located along the second direction Y.

10 1 1 2 1 6 FIG. In the above-mentioned embodiments, the circuit structure of the pixel circuitis mainly described by taking the circuit structure of 7T1C shown inas an example. In this case, the first signal line Smay be a scanning signal line SN, a scanning signal line SN, a light-emitting control signal line EM, or a reference voltage line Vref.

19 FIG. 19 FIG. 10 10 20 10 1 6 1 1 2 20 10 7 13 2 1 2 20 20 20 In some other embodiment shown inwhich is a schematic diagram of the circuit structure of another pixel circuit, the pixel circuitmay also be a 13T2C structure, and may include a pulse width module PWM controlled by pulse width modulation and an amplitude module PAM controlled by pulse amplitude modulation, to achieve the best performance of the light-emitting efficiency and viewing angle color deviation of the driven light-emitting element(such as a light-emitting diode). The pulse width module PWM in the pixel circuitmay include six thin film transistors (G-G) and a capacitor (C), and the signal lines electrically connected to the pulse width module PWM may include a scanning signal line SN-PWM, a scanning signal line SN-PWM, a light-emitting control signal line EM-PWM, a reference voltage signal line Vref-PWM, a data signal line data-PWM, a shutdown voltage signal line VDD-PWM, and a pulse width control voltage line Sweep. The pulse width module PWM may be used to control the light-emitting duration of the light-emitting element(such as a light-emitting diode). The amplitude module PA in the pixel circuitM may include seven thin film transistors (G-G) and a capacitor (C), and the signal lines electrically connected to the amplitude module PAM may include a scanning signal line SN-PWM, a scanning signal line SN-PWM, a light-emitting control signal line EM-PWM, a reference voltage signal line Vref-PWM, a data signal line data-PWM, and a power supply voltage line PVDD. The amplitude module PAM may be electrically connected to one electrode of the light-emitting element, and the other electrode of the light-emitting elementmay be electrically connected to the power supply voltage line PVEE. The amplitude module PAM may be used to control the light intensity of the light-emitting element(such as a light-emitting diode). The electrical connection relationship between the transistors in the 13T2C pixel circuit and the electrical connection relationship between the transistors and the signal lines may be as shown in, which will not be repeated.

10 19 FIG. It should be noted that the pixel circuitshown inis also only an example. In actual applications, pixel circuits with other circuit structures may be selected based on needs.

20 FIG. 30 11 12 21 22 11 11 11 10 1 12 12 12 10 2 21 21 21 10 1 22 22 22 10 2 In one embodiment shown inwhich is a schematic diagram of the electrical connection relationship of a local edge area of another display panel, the driving circuitmay include scanning circuits STV, STV, STVand STV. The scanning circuit STVmay include a multi-stage cascaded shift register circuit Scan, and the shift register circuit Scanmay be electrically connected to the amplitude module PAM in the pixel circuitthrough the scanning signal line SN-PAM extending along the first direction X. The scanning circuit STVmay include a multi-stage cascaded shift register circuit Scan, and the shift register circuit Sc anmay be electrically connected to the amplitude module PAM in the pixel circuitthrough the scanning signal line SN-PAM extending along the first direction X. The scanning circuit STVmay include a multi-stage cascaded shift register circuit Scan, and the shift register circuit Scanmay be electrically connected to the pulse width module PWM in the pixel circuitthrough the scanning signal line SN-PWM extending along the first direction X. The scanning circuit STVmay include a multi-stage cascaded shift register circuit Scan, and the shift register circuit Scanmay be electrically connected to the pulse width module PWM in the pixel circuitthrough the scanning signal line SN-PWM extending along the first direction X.

20 FIG. As shown in, the display panel may further include light-emitting control signal lines EM-PWN, EM-PAN and a pulse width control voltage line Sweep. The light-emitting control signal lines EM-PWN, EM-PAN and the pulse width control voltage line Sweep may all be direct driving signal lines, including a portion extending along the first direction X.

20 FIG. 1 30 10 1 1 2 1 1 2 1 1 As shown in, the first signal line Smay be a functional signal line electrically connected to the driving circuitand the pixel circuit, or may be a portion of the direct driving signal line extending along the first direction X. For example, the first signal line Smay be a scanning signal line SN-PWM, a scanning signal line SN-PWM, or a portion of the light-emitting control signal line EM-PWM and the pulse width control voltage line Sweep electrically connected to the pulse width module PWM. The first signal line Smay also be a portion of the scanning signal line SN-PAM, a scanning signal line SN-PAM and a light-emitting control signal line EM-PWN electrically connected to the amplitude module PAM along the first direction X. The designs of widening the cut-off end of the first signal line Sor designing it as a divergent structure and overlapping the first conductive portion Bin the direction perpendicular to the plane of the display panel introduced in the above-mentioned embodiments may be still all applicable and will not be repeated.

21 FIG. 21 FIG. 20 FIG. 100 100 10 10 10 1 2 1 2 1 2 10 1 2 10 In another embodiment shown inwhich is a schematic diagram of the layout structure of a local edge area of another display panel along the first direction X,shows a group of pixel circuit groups, and the pixel circuit groupmay include three pixel circuitsarranged along the first direction X. The circuit structure of the pixel circuitmay be as shown in, including a pulse width module PWM and an amplitude module PAM. The signal lines electrically connected to the pixel circuitand extending along the first direction X may include a reference voltage signal line Vref-PWM, a scanning signal line SN-PWM, a scanning signal line SN-PWM, a pulse width control voltage line Sweep, a light-emitting control signal line EM-PWM, a data signal line data-PAM, a reference voltage signal line Vref-PAM, a scanning signal line SN-PAM, a scanning signal line SN-PAM, and a light-emitting control signal line EM-PAM. The reference voltage signal line Vref-PWM, scanning signal line SN-PWM, scanning signal line SN-PWM, pulse width control voltage line Sweep and light-emitting control signal line EM-PWM may be electrically connected to the pulse width module PWM in the pixel circuit, and the data signal line data-PAM, reference voltage signal line Vref-PAM, scanning signal line SN-PAM, scanning signal line SN-PAM and light-emitting control signal line EM-PAM may be electrically connected to the amplitude module PAM in the pixel circuit.

20 FIG. 21 FIG. 1 1 2 1 2 1 1 1 1 1 As shown inand, the first signal lines Smay include multiple types of first signal lines, such as reference voltage signal lines Vref-PWM, scan signal lines SN-PWM, scan signal lines SN-PWM, pulse width control voltage lines Sweep, light-emitting control signal lines EM-PWM, data signal lines data-PAM, reference voltage signal lines Vref-PAM, scan signal lines SN-PAM, scan signal lines SN-PAM and light-emitting control signal line EM-PAM. Different types of first signal lines Smay be arranged along the second direction Y, and each type of first signal lines Smay adopt the design introduced in the aforementioned embodiments of widening the cut-off end of the first signal line Sor designing it as a divergent structure and overlapping the first conductive portion Bin the first signal line segment Din the direction perpendicular to the plane where the display panel is located.

20 FIG. 21 FIG. 1 10 1 1 1 For example, as shown inand, the cut-off ends of the different types of first signal lines Sextending along the first direction X electrically connected to the pixel circuitmay be a widened arc shape, and the first line segments Dof the different types of first signal lines Smay be provided with overlapping first conductive portions Bin the direction perpendicular to the plane where the display panel is located.

21 FIG. 1 1 As shown in, the multiple types of first signal lines Sin the display panel may include first-type first signal lines and second-type first signal lines, and the width of the first-type first signal lines along the second direction Y may be larger than the width of the second-type first signal lines along the second direction Y. The first conductive portions Bmay include first-type first conductive portions and second-type second conductive portions. In the direction perpendicular to the plane where the display panel is located, the first-type first conductive portions may overlap with the first-type first signal lines, and the second-type first conductive portions may overlap with the second-type first signal line. The area of the orthographic projection of the first-type first conductive portions perpendicular to the plane where the display panel is located may be larger than the area of the orthographic projection of the second-type first conductive portion perpendicular to the plane where the display panel is located.

21 FIG. 1 2 1 2 1 1 1 2 For example, as shown in, one first-type first signal line may be a light-emitting control signal line EM-PAM extending along the first direction X, and one second-type first signal line may be a reference voltage signal line Vref-PWM, a scan signal line SN-PWM, a scan signal line SN-PWM, a pulse width control voltage line Sweep, a light-emitting control signal line EM-PWM, a data signal line data-PAM, a reference voltage signal line Vref-PAM, a scan signal line SN-PAM or a scan signal line SN-PAM extending along the first direction X. The width of the light-emitting control signal line EM-PAM along the second direction Y may be larger than the width of the second-type first signal line such as the scan signal line SN-PAM along the second direction Y. In the direction perpendicular to the plane where the display panel is located, the area of the first conductive portion Boverlapping with the light-emitting control signal line EM-PAM may be larger than the area of the first conductive portion Boverlapping with the second-type first signal lines such as the scan signal line SN-PAM.

1 1 10 1 Therefore, for the first signal line Swith a larger width along the second direction Y, the area of the corresponding overlapping first conductive portion Bmay be larger, which may better protect the transistor devices in the pixel circuitclose to the edge of the display panel along the first direction X from electrostatic damage and improve the reliability of electrostatic protection of the cut-off end of the first signal line S.

10 1 Based on a similar design idea, in some other embodiments, it may also be set that the number of first-type first conductive portions overlapping with the first-type first signal lines to be larger than the number of second-type first conductive portions overlapping with the second-type first signal lines in the direction perpendicular to the plane where the display panel is located, to better protect the transistor devices in the pixel circuitclose to the edge of the display panel along the first direction X from electrostatic damage and improve the reliability of electrostatic protection of the cut-off end of the first signal line S.

1 1 1 1 2 1 1 2 21 FIG. Further, considering that the lines in the display panel are very dense, it may be possible to set the first conductive portions Bof some types of first signal lines Soverlapping in the direction perpendicular to the plane where the display panel is located and the first conductive portions Bof other types of first signal lines Soverlapping in the direction perpendicular to the plane where the display panel is located to be staggered along the second direction Y. For example, as shown in, in one embodiment, the first-type first signal lines may be the light-emitting control signal lines EM-PAM extending along a first direction X, and the second-type first signal lines may be the scanning signal lines SN-PAM extending along the first direction X. In the direction perpendicular to the plane where the display panel is located, the first-type first conductive portions overlap with the first-type first signal lines, and the second-type first conductive portions overlap with the second-type first signal lines. Along the second direction Y, the first conductive portions B(i.e., the first-type first conductive portions) of the light-emitting control signal lines EM-PAM overlapping in the direction perpendicular to the plane where the display panel is located and the first conductive portions B(i.e., the second-type first conductive portions) of the scanning signal lines SN-PAM overlapping in a direction perpendicular to the plane where the display panel is located may not overlap along the second direction Y.

22 FIG. 1 2 2 2 10 10 10 In some other embodiment shown inwhich is a top view schematic diagram of a display panel consistent with the present disclosure, the display panel may include a first area Aand a second area A. The second area Amay be a display area. The second area Amay include pixel circuits, and may also include data signal lines ND arranged along a first direction X and extending along a second direction Y. One data signal line ND may be electrically connected to one corresponding pixel circuit, and the data signal line ND may be used to provide a data signal to the corresponding pixel circuit. The first direction X and the second direction Y may intersect, and the first direction X and the second direction Y may be parallel to the plane where the display panel is located.

22 FIG. 1 2 1 2 1 As shown in, in the display panel, the first area Amay be located on the side of the second area Aclose to the edge of the display panel. For example, the first area Amay be located on the side of the second area Aalong the second direction Y. The first area Amay be a fan-out area.

22 FIG. 1 1 2 1 2 1 2 1 2 As shown in, the first area Amay include first line segments Dand second line segments D. That is, the first line segments Dand the second line segments Dmay be all located in the first area A. The multiple second line segments Dmay be arranged along the first direction X, and the first line segments Dmay be located on at least one side of the multiple second line segments Dalong the first direction X.

22 FIG. 3 1 2 2 3 1 1 11 2 11 2 2 11 2 2 As shown in, the display panel may also include a third area Alocated on the side of the first area Aaway from the second area A. The third area Amay be a pin area. The third area Amay include a plurality of pins P. The plurality of pins Pmay include a data pin P. One end of one second line segment Dmay be electrically connected to one corresponding data pin P, and the other end of the second line segment Dmay be electrically connected to the corresponding data signal line ND. That is, the second line segment Dmay be a fan-out routing, and the data pin Pmay be electrically connected to the data signal line ND through the second line segment Dto transmit the data signal to the data signal line ND. The two ends of the second line segment Dmay be non-cut-off ends.

22 FIG. 1 1 2 1 2 1 2 1 2 11 3 2 1 2 As shown in, in the first area A, the first line segments Dmay be provided on at least one side of the multiple second line segments Dalong the first direction X, and the extension direction of the first line segments Dmay be the same as the extension direction of the second line segments D. It should be noted that in the embodiments of the present disclosure, the extension direction of the first line segments Dmay be the same as the extension direction of the second line segments D, which means that the first line segments Dand the second line segments Dmay all be extended from the data pins Pof the third area Ato the direction of the data signal lines ND of the second area A, and it does not limit the first line segments Dand the second line segments Dto be completely parallel.

22 FIG. 1 1 1 2 1 11 3 2 1 2 As shown in, in the first area A, both ends of one first line segment Dmay be cut-off ends. That is, although the first line segments Dand the second line segments Dextend in the same direction, the first line segments Dmay be neither electrically connected to the data pins Pof the third area Anor to the data signal lines ND in the second area A, that is, the first line segments Dmay not be used to transmit data signals, but may be used to perform electrostatic protection on the second line segments Dthat transmits data signals.

1 2 1 1 1 2 1 Since the first line segments Dare located on one side of the multiple second line segments Dand both ends of one first line segment Dmay be non-cut-off ends, static electricity in and near the first area A(edge area) of the display panel may be accumulated at the cut-off ends of the first line segments D, preventing static electricity from damaging the second line segments Dused to transmit data signals in the first area A, that is, preventing static electricity from damaging the components near the edge area of the display panel and performing reliable electrostatic protection in the display panel.

1 1 3 12 12 22 FIG. The ability of the cut-off ends of the first line segments Dto accumulate electrostatic charge is relatively limited. As shown in, the display panel may include a first power voltage line PV, and the plurality of pins Pin the third area Amay include a first power pin P, and the first power pin Pmay be electrically connected to the first power voltage line PV.

10 10 2 10 6 FIG. 19 FIG. The first power supply voltage line PV may be a power supply voltage line PVDD. Thus, referring to the pixel circuitshown inand, the first power supply voltage line PV may be also electrically connected to the pixel circuitin the second area A, and the first power supply voltage line PV may be used to provide the first power supply voltage signal to the pixel circuit.

6 FIG. 19 FIG. 2 Alternatively, the first power supply voltage line PV may also be a power supply voltage line PVEE. Thus, as shown inand, the first power supply voltage line PV may also be electrically connected to the light-emitting element in the second area A.

2 10 2 The first power supply voltage line PV may include a first subordinate line located in the second area A. The first subordinate line may be electrically connected to the pixel circuitor to the light-emitting element. The first subordinate lines may be arranged in a grid in the second area A, or may be arranged on the entire surface, depending on the specific situation.

22 FIG. 1 2 1 1 1 2 1 2 2 12 2 12 1 As shown in, the first power supply voltage line PV may also include a first main body Vand a first extension portion Vlocated in the first area A. The first main body portion Vmay extend along the first direction X such that the first main body portion Vis electrically connected to the first subordinate line of the second area A. The first main body Vmay be electrically connected to the first extension portion V, and the first extension portion Vmay be electrically connected to the first power pin P. The first extension portion Vmay be fanned out from the first power pin Pto the first main body V, which may be an overall fan-out or a strip fan-out, depending on the specific situation.

23 FIG. 22 FIG. 23 FIG. 1 2 2 For better understanding,shows an enlarged schematic diagram of the layout structure of the EE′ area in. As shown in, one or more (such as two) first line segments Dmay be set on both sides of the multiple second line segments D(i.e., fan-out wiring) along the first direction X, for electrostatic protection of the second line segments Dtransmitting the data signal.

22 FIG. 23 FIG. 1 2 1 2 1 1 1 1 As shown inand, the first main body Vof the first power supply voltage line PV and the second line segment Dmay be arranged in different layers, and in the direction perpendicular to the plane where the display panel is located, the first main body Vand the second line segment Dmay at least partially overlap. The first main body Vof the first power supply voltage line PV and the first line segment Dmay be arranged in different layers, and in the direction perpendicular to the plane where the display panel is located, the first main body Vand the first line segment Dmay at least partially overlap.

22 FIG. 23 FIG. 1 1 2 1 2 1 1 1 2 1 1 2 1 As shown inand, in the direction perpendicular to the plane where the display panel is located, the cut-off end Jof the first line segment Dclose to the second area Amay be covered by the first main body V. Therefore, when the second line segment Dof the first area Ais subjected to static electricity, the cut-off end Jof the first line segment Dclose to the second area Amay accumulate static electricity. Once the static electricity accumulated at the cut-off end Jof the first line segment Dclose to the second area Ais released, a tip discharge occurs, which is likely to damage the first main body Vof the first power supply voltage line PV, destroy the transmission of the first power supply voltage line PV, and even cause a short circuit.

23 FIG. 1 2 1 2 1 2 1 2 1 2 As shown in, the metal layer where the first main body Vand the first extension portion Vof the first power supply voltage line PV are located may be located above the metal layer where the first line segment Dand the second line segment Dare located. To show the first line segment Dand the second line segment D, the first line segment Dand the second line segment Dare drawn above the first main body Vand the first extension portion Vof the first power supply voltage line PV.

22 FIG. 2 1 2 2 1 2 2 2 2 As shown in, since the driving integrated circuit IC in the display panel does not match the screen resolution, two groups of left and right second line segments Darranged along the first direction X may be set in the first area A, and each group of second line segments Dmay include multiple second line segments D. One or more first line segments Dmay be set on two sides of each group of second line segments Dalong the first direction X to perform electrostatic protection on the second line segments Din the group of second line segments D, and the two sides of one group of second line segments Don the left side along the first direction X may correspond to the EE′ area and the FF″ area respectively.

24 FIG. 22 FIG. 24 FIG. 1 1 2 1 2 1 1 1 2 1 1 2 1 1 2 1 2 1 2 It can be understood that, as shown inwhich is an enlarged schematic diagram of the layout structure of the FF′ area in, in the direction perpendicular to the plane where the display panel is located, the cut-off end Jof the first line segment Dclose to the second area Amay be covered by the first main body V. When the second line segment Dof the first area Ais subjected to static electricity, the cut-off end Jof the first line segment Dclose to the second area Amay accumulate static electricity. Once the static electricity accumulated by the cut-off end Jof the first line segment Dclose to the second area Ais released, tip discharge occurs, which is likely to damage the first main body Vof the first power supply voltage line PV and destroy the transmission of the first power supply voltage line PV. In, to show the first line segment Dand the second line segment D, the first line segment Dand the second line segment Dare drawn above the first main body Vand the first extension portion Vof the first power supply voltage line PV. Similar situations are not repeated below.

1 1 2 1 1 1 2 1 The cut-off end Jof the first line segment Dclose to the second area Amay be extended out of the area outside the first main body Vto form a protruding structure. In this way, even when the cut-off end Jof the first line segment Dclose to the second area Aaccumulates a lot of electrostatic charge for tip discharge, it may not cause damage to the first main body Vof the nearby first power line PVDD.

25 FIG. 22 FIG. 23 FIG. 25 FIG. 1 1 2 1 1 1 2 1 1 1 2 1 For example, as shown inwhich is another enlarged schematic diagram of the layout structure corresponding to the EE′ area in, compared with, it can be seen that in the layout structure shown in, the cut-off end Jof the first line segment Dclose to the second area Amay be extended out of the area outside the first main body Vto form a protruding structure, such that in the direction perpendicular to the plane where the display panel is located, the cut-off end Jof the first line segment Dclose to the second area Adoes not overlap with the first main body Vof the first power voltage line PV, to avoid the electrostatic charge accumulated at the cut-off end Jof the first line segment Dclose to the second area Afrom damaging the first main body Vof the first power line PVDD when the discharge is performed.

26 FIG. 22 FIG. 24 FIG. 26 FIG. 1 1 2 1 1 1 2 1 1 1 2 1 As shown inwhich is another enlarged schematic diagram of the layout structure corresponding to the FF′ area in, compared with, in the layout structure shown in, by extending the cut-off end Jof the first line segment Dclose to the second area Aout of the area outside the first main body V, a protruding structure may be formed. Therefore, in the direction perpendicular to the plane where the display panel is located, the cut-off end Jof the first line segment Dclose to the second area Amay not overlap with the first main body Vof the first power supply voltage line PV, to avoid the electrostatic charge accumulated at the cut-off end Jof the first line segment Dclose to the second area Afrom damaging the first main body Vof the first power supply line PVDD when it is released.

1 1 2 1 1 2 1 1 Also, the ability of the cut-off end Jof the first line segment Dclose to the second area Ato accumulate electrostatic charge may be improved by increasing the width of the cut-off end Jof the first line segment Dclose to the second area Ain the direction perpendicular to the extension direction of the first line segment D, and designing the cut-off end of the first line segment Das a divergent structure.

27 FIG. 22 FIG. 27 FIG. 1 1 2 1 1 1 2 1 1 1 2 1 1 2 1 1 1 2 1 shows another enlarged schematic diagram of the layout structure corresponding to the EE′ region in. As shown in, in the direction perpendicular to the extension direction of the first line segment D, the width of the cut-off end of the first line segment Dclose to the second area Amay be larger than the width of the other portions of the first line segment Dexcept the cut-off end. For example, on the basis of extending the cut-off end Jof the first line segment Dclose to the second area Aout of the first main body Vto form a protruding structure, the cut-off end Jof the first line segment Dclose to the second area Amay be further arranged to be in an arc shape. Such an arrangement may not only prevent the electrostatic charge accumulated at the cut-off end Jof the first line segment Dclose to the second area Afrom damaging the first main body Vwhen releasing, but also improve the ability of the cut-off end Jof the first line segment Dclose to the second area Ato accumulate electrostatic charge, to improve the reliability of electrostatic protection of the cut-off end of the first line segment D.

27 FIG. 1 1 2 1 1 2 1 1 1 2 1 1 1 2 1 1 2 1 1 2 1 shows that the width of the cut-off end Jof the first line segment Dnear the second area Amay be increased on the basis that the cut-off end Jof the first line segment Dnear the second area Aextends out of the first main body Vto form a protruding structure. It may be understood that, even when the cut-off end Jof the first line segment Dnear the second area Amay not be extended out of the first main body Vto form a protruding structure and only the width of the cut-off end Jof the first line segment Dnear the second area Amay be increased, the ability of the cut-off end Jof the first line segment Dnear the second area Ato accumulate electrostatic charge may be improved, thereby preventing the cut-off end Jof the first line segment Dnear the second area Afrom releasing static electricity to damage the first main body Vof the first power line PVDD to a certain extent.

28 FIG. 22 FIG. 28 FIG. 1 11 12 12 11 1 2 1 2 1 2 shows another enlarged schematic diagram of the layout structure corresponding to the EE′ area in. As shown in, the first line segment Dmay include a main body Dand forked portions Dextending in different directions, and the forked portions Dmay be connected to the main body D. In this way, the cut-off end of the first line segment Dclose to the second area Amay be a bifurcated structure to increase the path for the cut-off end of the first line segment Dclose to the second area Ato accumulate electrostatic charge, thereby improving the ability of the cut-off end of the first line segment Dclose to the second area Ato accumulate electrostatic charge.

28 FIG. 1 1 2 1 1 2 1 1 2 1 1 2 1 1 2 1 1 2 1 shows that, on the basis of the cut-off end Jof the first line segment Dclose to the second area Aextending out of the first main body Vto form a protruding structure, the cut-off end of the first line segment Dclose to the second area Amay be set as a bifurcated structure. It may be understood that, even when the cut-off end Jof the first line segment Dclose to the second area Amay not be extended out of the first main body Vto form a protruding structure and only the cut-off end of the first line segment Dclose to the second area Amay be set as a bifurcated structure, the ability of the cut-off end Jof the first line segment Dclose to the second area Ato accumulate electrostatic charge may be improved, thereby preventing the cut-off end Jof the first line segment Dclose to the second area Afrom releasing static electricity to damage the first main body Vof the first power line PVDD to a certain extent.

1 1 2 1 1 Further, a sacrificial structure for releasing static electricity may be provided at the cut-off end of the first line segment D. Therefore, when too much static electricity is accumulated at the cut-off end of the first line segment D, static electricity may be preferentially released at the sacrificial structure, thereby protecting the second line segment Dand the first main body Vin the first power supply voltage line PV from static electricity damage, and improving the reliability of static electricity protection at the cut-off end of the first line segment D.

11 FIG. 12 FIG. 1 2 3 1 As shown inand, the display panel may include a substrate sub, an active layer py located on one side of the substrate sub, and a multi-layer metal layer located on the side of the active layer py away from the substrate sub. The multi-layer metal layer may include a metal layer M, a metal layer MC, a metal layer M, a metal layer M, and a metal layer RE arranged in a direction away from the substrate sub. The first line segment Dmay be located in at least one metal layer in the multi-layer metal layer. Different metal layers and metal layers and active layers may be isolated by insulating layers.

11 FIG. 12 FIG. 23 FIG. 28 FIG. 1 101 102 101 102 101 102 As shown intoandto, the first line segment Dmay include a first sub-line segment Dand a second sub-line segment D. The first sub-line segment Dand the second sub-line segment Dmay be arranged in different layers. The orthographic projection of the first sub-line segment Don the plane where the display panel is located and the orthographic projection of the second sub-line segment Don the plane where the display panel is located may extend in the same direction.

2 201 202 201 202 201 202 The second line segment Dmay include a third sub-line segment Dand a fourth sub-line segment D. The third sub-line segment Dand the fourth sub-line segment Dmay be arranged in different layers. The orthographic projection of the third sub-line segment Don the plane where the display panel is located and the orthographic projection of the fourth sub-line segment Don the plane where the display panel is located may have the same extension direction, and the two may be arranged alternately.

101 201 The first sub-line segment Dand the third sub-line segment Dmay be arranged in the same layer, and the two may have the same extension direction.

102 202 The second sub-line segment Dand the fourth sub-line segment Dmay be arranged in the same layer, and the two may have the same extension direction.

11 FIG. 12 FIG. 1 2 101 201 1 102 202 1 2 Furthermore, referring toand, the multi-layer metal layer may include a first metal layer (metal layer M), a second metal layer (metal layer MC), and a third metal layer (metal layer M) stacked in sequence in a direction away from the substrate sub. The first sub-segment Dand the third sub-segment Dmay be located in the first metal layer (metal layer M), the second sub-segment Dand the fourth sub-segment Dmay be located in the second metal layer (metal layer MC), and the first main body Vof the first power supply voltage line PV may be located in the third metal layer (metal layer M).

1 2 201 1 201 1 2 1 It may be seen that in the first area A, the second line segment Dmay include a third sub-segment Dlocated in the first metal layer (metal layer M) and a fourth sub-segment Dlocated in the second metal layer (metal layer MC), both of which extend in the same direction and may be alternately arranged along the first direction X, and the extension direction and wiring method of the first line segment Dmay be the same as those of the second line segment D, and the only difference may be that both ends of the first line segment Dmay be cut-off ends.

3 1 2 3 4 1 2 4 It may be understood that, when the first power supply voltage line PV may be the power supply voltage line PVDD, the first subordinate line in the first power supply voltage line PV may be usually located in the metal layer M, and the first main body Vmay be electrically connected to the first subordinate line by switching from the metal layer Mto the metal layer M. When the first power supply voltage line PV may be the power supply voltage line PVEE, the first subordinate line in the first power supply voltage line PV may be usually located in the metal layer M, and the first main body Vmay be electrically connected to the first subordinate line by switching from the metal layer Mto the metal layer M.

23 FIG. 28 FIG. 2 101 1 102 1 101 1 102 1 2 Optionally, as shown into, on either side of a group of second line segments Dalong the first direction X, a first sub-line segment Dlocated in the first metal layer (metal layer M) and a second sub-line segment Dlocated in the second metal layer (metal layer MC) may be set to form a first line segment D. Alternatively, a first sub-segment Dlocated in the first metal layer (metal layer M) or a second sub-segment Dlocated in the second metal layer (metal layer MC) may be provided as the first segment Don either side of a group of second segments Dalong the first direction X.

1 1 2 1 Alternatively, in the first area A, the first segment Dand the second segment Dmay both be located in the first metal layer (metal layer M).

1 2 2 1 1 Compared with setting the first line segment Dand the second line segment Din the same metal layer, setting the second line segment Dand the first sub-segment Dby two sub-segments set in different layers to be arranged alternately along the first direction X may reduce the wiring density in the same metal layer of the first area A, which may be convenient for wiring.

101 102 201 202 11 3 2 It may also be understood that the first sub-segment D, the second sub-segment D, the third sub-segment Dand the fourth sub-segment Dhave the same extension direction, which means that they all extend from the data pin Pof the third area Ato the direction of the data signal line ND of the second area A, and may be not limited to being completely parallel.

29 FIG. 22 FIG. 30 FIG. 22 FIG. 29 FIG. 30 FIG. 29 FIG. 30 FIG. 31 FIG. 2 2 1 1 2 1 2 1 1 1 2 2 1 2 1 1 2 2 2 1 3 2 shows an enlarged schematic diagram of another layout structure corresponding to the EE′ area in, andshows an enlarged schematic diagram of another layout structure corresponding to the FF′ area in. As shown inand, the display panel may further include a second conductive portion B, and the second conductive portion Band the first line segment Dmay be arranged in different layers. In the direction perpendicular to the plane where the display panel may be located, the cut-off end of the first line segment Dmay at least partially overlap with the second conductive portion B, and an insulating layer may be provided between the cut-off end of the first line segment Dand the second conductive portion B. The cut-off end of the first line segment Dmay include the cut-off end Jof the first line segment Dclose to the second area Aand the cut-off end Jof the first line segment Dclose to the third area A.andshow the situation that the cut-off end Jof the first line segment Dclose to the second area Aoverlaps with the second conductive portion Bin the direction perpendicular to the plane where the display panel may be located, andshows the situation that the cut-off end Jof the first line segment Dclose to the third area Aoverlaps with the second conductive portion Bin a direction perpendicular to the plane where the display panel may be located.

1 1 2 2 1 1 In this way, when the cut-off end of the first line segment Daccumulates a lot of electrostatic charge which needs to be discharged at the tip, the insulating layer between the cut-off end of the first line segment Dand the second conductive portion Bmay be preferentially broken down, and the electrostatic discharge may be performed to the second conductive portion B, which may more effectively protect the second line segment Dand the first power supply voltage line PV from electrostatic damage and further improve the reliability of electrostatic protection of the cut-off end of the first line segment D.

2 1 2 1 2 2 1 1 2 1 2 1 2 Optionally, in some embodiments of the present application, the second conductive portion Bmay be located between the metal layer where the first line segment Dis located and the base substrate sub. In this configuration, the second conductive portion Bmay be first formed on the base substrate sub, and then the first line segment Dand the second line segment Dmay be formed on the side of the second conductive portion Baway from the base substrate sub. Therefore, when the static electricity needs to be released at the cut-off end of the first line segment Dduring the preparation of the first line segment Dand the second line segment D, the cut-off end of the first line segment Dmay release static electricity to the second conductive portion B, thereby improving the preparation yield of the display panel; and during the use of the display panel, the cut-off end of the first line segment Dmay also release static electricity to the second conductive portion B.

2 1 1 2 In some other embodiments of the present disclosure, the second conductive portion Bmay also be located between the metal layer where the first line segment Dis located and the substrate sub. With such a configuration, during the use of the display panel, the cut-off end of the first line segment Dmay release static electricity to the second conductive portion B.

2 1 1 101 1 102 2 On the basis that the second conductive portion Bis located between the metal layer where the first line segment Dis located and the substrate sub, considering that the first line segment Dmay include a first sub-line segment Dlocated in the first metal layer (metal layer M) and a second sub-line segment Dlocated in the second metal layer (metal layer MC), optionally, in some embodiments of the present disclosure, the second conductive portion Bmay be located in the active layer py.

29 FIG. 31 FIG. 1 2 1 2 Optionally, in some embodiments of the present disclosure, as shown into, the orthographic projection of the cut-off end of the first line segment Don the plane where the display panel is located may be located within the orthographic projection of the second conductive portion Bon the plane where the display panel is located. This configuration may be beneficial for the electrostatic charge accumulated at the cut-off end of the first line segment Dto be fully released to the second conductive portion B.

29 FIG. 32 FIG. 32 FIG. 22 FIG. 2 1 2 1 1 2 Further optionally, in some embodiments of the present disclosure, as shown into, especially as shown inwhich is another enlarged schematic diagram of the layout structure corresponding to the EE′ area in, the second conductive portion Bmay extend along the extension direction of the first line segment D, that is, the second conductive portion Bmay be a linear structure extending along the extension direction of the first line segment D. Such a setting may be more conducive to the full release of the electrostatic charge accumulated at the cut-off end of the first line segment Dto the second conductive portion B.

1 1 1 2 2 1 1 It should be noted that the structural design of the first conductive portion Boverlapping with the first line segment Din the first signal line Sin the direction perpendicular to the plane where the display panel is located in the aforementioned embodiments may also be applied to the second conductive portion B, and the linear structure of the second conductive portion Bextending along the extension direction of the first line segment Dmay also be applied to the first conductive portion B, which will not be repeated.

33 FIG. 34 FIG. 400 300 300 Accordingly, the present disclosure also provides a display device, as shown inand, the display devicemay include a display panelprovided by any of the aforementioned embodiments. Since the display panelhas been described in detail in the above embodiments, it will not be repeated here.

400 The display devicemay be any electronic device with a display function, such as a touch screen, a mobile phone, a tablet computer, a laptop computer, an e-book or a TV.

300 It should be noted that, since the driving circuit may be set in the display area in the above embodiments to realize a borderless and full-screen design of the display panel, the display device provided in the embodiment of the present disclosure may be a spliced display device, including multiple borderless display units (i.e., the display panel).

In the present disclosure, relational terms such as “first” and “second” are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is a relationship between these entities or operations. There is no such actual relationship or sequence. Furthermore, the terms “comprises”, “include”, or any other variations thereof are intended to cover a non-exclusive inclusion such that a process, method, article, or apparatus that includes a list of elements includes not only those elements, but also those not expressly listed, or elements inherent to the process, method, article or equipment. Without further limitation, an element defined by the statement “comprises a . . . ” does not exclude the presence of additional identical elements in a process, method, article, or apparatus that includes the stated element.

Various embodiments have been described to illustrate the operation principles and exemplary implementations. It should be understood by those skilled in the art that the present disclosure is not limited to the specific embodiments described herein and that various other obvious changes, rearrangements, and substitutions will occur to those skilled in the art without departing from the scope of the disclosure. Thus, while the present disclosure has been described in detail with reference to the above described embodiments, the present disclosure is not limited to the above described embodiments, but may be embodied in other equivalent forms without departing from the scope of the present disclosure, which is determined by the appended claims.