Memory Device and Memory System

This application is based on and claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2025-0009820, filed on Jan. 22, 2025, in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety.

The inventive concept relates to a memory device, and more particularly, to a power gating operation of a memory device.

In recent years, there have been increasing demands for both high performance and low power consumption in electronic equipment. In particular, semiconductor memory devices are important components in battery-based systems, such as mobile equipment, and the power consumption of a memory device may have a significant impact on the power efficiency of a system as a whole.

The power consumed by memory devices is mainly classified into operating power and leakage power. The leakage power is continuously consumed even when the memory devices are in an inactive state and tends to increase as sizes of the semiconductor devices decrease. Therefore, reduction of the leakage current is becoming an increasingly important issue in designing memory devices.

Among several technologies for reducing the leakage current, power gating is one of the widely used techniques. The power gating reduces the leakage current in the inactive state by cutting off or limiting power to a specific part of a circuit and may thus be effective in improving the power efficiency of memory devices.

However, power gating methods according to the related art have limitations, such as power consumption and operating delays that occur during voltage switching processes, and thus, improved design and implementation methods for solving these limitations are required.

The inventive concept provides a memory device and a memory system capable of reducing the power required for a power gating operation.

According to an aspect of the inventive concept, there is provided a memory device including a memory cell array including memory cells, a peripheral circuit configured to transmit a plurality of signals for writing or reading data to the memory cells, a control logic circuit configured to output a power gating enable signal, and a power gating circuit configured to, in response to the power gating enable signal, connect the peripheral circuit to or disconnect the peripheral circuit from a power supply voltage line. The power gating circuit includes a positive power gating switch connected between the peripheral circuit and the power supply voltage line and a boosting control circuit configured to boost a gate voltage of the positive power gating switch to a first voltage level during a first stage and then boost the gate voltage of the positive power gating switch to a second voltage level higher than the first voltage level during a second stage after the first stage, to allow the memory device to operate in a standby mode.

According to another aspect of the inventive concept, there is provided a memory device including a memory cell array including memory cells, a peripheral configured to transmit a plurality of signals for writing or reading data to the memory cells, a control logic circuit configured to output a power gating enable signal, and a power gating circuit configured to, in response to the power gating enable signal, connect the peripheral circuit to or disconnect the peripheral circuit from a ground voltage line. The power gating circuit includes a negative power gating switch connected between the peripheral circuit and the ground voltage line and a dropping control circuit configured to drop a gate voltage of the negative power gating switch to a first voltage level during a first stage and then drop the gate voltage of the negative power gating switch to a second voltage level lower than the first voltage level during a second stage after the first stage, to allow the memory device to operate in a standby mode.

According to another aspect of the inventive concept, there is provided a memory system including a host device configured to transmit a command indicating a standby mode and a memory device configured to operate in the standby mode in response to the command. The memory device includes a memory cell array including memory cells, a peripheral circuit configured to transmit a plurality of signals for writing or reading data to the memory cell, a control logic circuit configured to output a power gating enable signal in response to the command, and a power gating circuit configured to, in response to the power gating enable signal, connect the peripheral circuit to or disconnect the peripheral circuit from a power supply voltage line. The power gating circuit includes a positive power gating switch connected between the peripheral circuit and the power supply voltage line and a boosting control circuit configured to boost a gate voltage of the positive power gating switch to a first voltage level during a first stage and then boost the gate voltage of the positive power gating switch to a second voltage level higher than the first voltage level during a second stage after the first stage.

Hereinafter, various embodiments are described with reference to the accompanying drawings. The same reference numerals are given to the same elements in the drawings, and repeated descriptions thereof are omitted.

1 FIG. 10 is a block diagram of a memory systemaccording to an embodiment.

10 10 10 The memory systemmay be a computing device such as an integrated circuit, an electronic device or system, a smartphone, a tablet personal computer (PC), a computer, a server, a workstation, a portable communication terminal, a personal digital assistant (PDA), a portable multimedia player (PMP), and other appropriate computers, a virtual machine or a virtual computing device thereof, and the like. Alternatively, the memory systemmay represent some components of a computing system, such as a graphics card. According to an embodiment, the memory systemmay be provided as an unbuffered dual in-line memory module (UDIMM), a registered DIMM (RDIMM), a load reduced DIMM (LRDIMM), a fully buffered DIMM (FBDIMM), or a small outline DIMM (SODIMM).

10 10 Also, the memory systemor a data processing system including the memory systemmay be provided as a PC, a data server, a cloud system, an artificial intelligence server, a network-attached storage (NAS), an Internet of Things (IoT) device, or a portable electronic product. Also, when the data processing system is provided as the portable electronic product, the data processing system may include a laptop computer, a mobile phone, a smartphone, a tablet PC, a PDA, an enterprise digital assistant (EDA), a digital still camera, a digital video camera, an audio device, a PMP, a personal navigation device (PND), an MP3 player, a handheld game console, an e-book, a wearable device, etc.

1 FIG. 10 100 20 20 100 20 100 100 Referring to, the memory systemmay include a memory deviceand a memory controller. The memory controllerand the memory deviceeach may include an interface circuit (not shown) to communicate various signals. For example, the memory controllermay provide a clock and a command/address CMD/ADDR to the memory deviceand access data DATA of the memory device.

1 FIG. 100 110 120 130 Referring to, the memory devicemay include a memory cell array, a peripheral circuit, and a power gating circuit.

110 110 The memory cell arraymay include a plurality of word lines, a plurality of bit lines, and a plurality of memory cells formed at intersections between the word lines and the bit lines. The memory cells of the memory cell arraymay include volatile memory cells (e.g., dynamic random-access memory (DRAM) cells or static random-access memory (SRAM) cells), non-volatile memory cells (e.g., flash memory cells, resistive random-access memory (ReRAM) cells, phase-change random access memory (PRAM) cells, or magnetic random-access memory (MRAM) cells), or other types of memory cells.

120 120 110 110 The peripheral circuitmay provide the plurality of memory cells with a plurality of signals for accessing data, such as writing or reading data. The peripheral circuitmay be located around the memory cell arrayon a semiconductor substrate and provide signals necessary for data access to the memory cell array in the memory cell array.

120 100 In an embodiment, the peripheral circuitmay include a command/address decoder (not shown), perform a decoding operation on the command/address CMD/ADDR, and control an operation of the memory deviceon the basis of the decoding result.

130 120 130 120 100 130 120 100 The power gating circuitmay be connected between the peripheral circuitand a power supply voltage line (or a ground voltage line). The power gating circuitmay allow or block providing the power supply voltage (or the ground voltage) to the peripheral circuitdepending on the mode of the memory device(the active mode ACT or the standby mode STBY). That is, the power gating circuitmay selectively supply power to the peripheral circuitdepending on the mode of the memory device.

100 130 120 120 When the memory deviceoperates in the active mode ACT, the power gating circuitmay provide the power supply voltage (or the ground voltage) to the peripheral circuitso that the peripheral circuitoperates.

100 130 120 120 When the memory deviceoperates in the standby mode STBY, the power gating circuitmay block providing the power supply voltage (or the ground voltage) to the peripheral circuitso that the peripheral circuitdoes not operate.

100 130 That is, the memory devicemay include the power gating circuitto reduce unnecessary power consumption due to leakage current in an idle state (the standby mode STBY).

100 100 Also, the memory devicemay include DRAM, such as double data rate synchronous dynamic random-access memory (DDR SDRAM), low power double data rate (LPDDR) SDRAM, graphics double data rate (GDDR) SDRAM, Rambus dynamic random-access memory (RDRAM), DDR2 SDRAM, DDR3 SDRAM, and DDR4 SDRAM. However, the embodiments are not limited thereto, and the memory devicemay include, for example, non-volatile memory, such as flash memory, MRAM, spin-transfer torque MRAM, conductive bridging RAM (CBRAM), ferroelectric RAM (FeRAM), PRAM, and ReRAM.

100 100 100 1 FIG. Also, the memory devicemay correspond to a single semiconductor chip or may be configured to correspond to a single channel in a memory device including a plurality of channels having independent interfaces. Also, the memory devicemay have a configuration corresponding to a memory module. Also, a memory module may include a plurality of memory chips, and the memory deviceofmay correspond to a single memory chip mounted on a module board.

20 100 20 20 20 100 10 The memory controllermay access the memory devicein response to a request from a host HOST, and the memory controllermay communicate with the host HOST via various protocols. According to embodiments, the memory controllermay correspond to the host HOST, or the memory controllermay correspond to a component provided inside the host HOST. The host HOST and the memory devicemay constitute a data processing system, and accordingly, the memory systemmay correspond to the data processing system or be defined as a component provided in the data processing system.

20 100 100 100 20 100 100 20 100 In response to read/write requests from the host HOST, the memory controllermay control the memory deviceto read data stored in the memory deviceor program data into the memory device. Specifically, the memory controllermay provide a command CMD, an address ADDR, and a control signal to the memory device, thereby controlling programming, reading, and erasing operations with respect to the memory device. Also, data DATA for programming and data DATA to be read may be exchanged between the memory controllerand the memory device.

3 FIG. 2 200 According to the inventive concept, when entering the idle state (the standby mode STBY), a gate voltage level of a positive power gating switch PPS inis not raised (boosted) to a positive power gating voltage VPGP at once, but is raised to a second power supply voltage VDDin an intermediate stage and then raised to the positive power gating voltage VPGP. This may reduce power consumed by a power gating operation of a first power gating circuit.

3 FIG. 300 According to the inventive concept, when entering the idle state (the standby mode STBY), a gate voltage level of a negative power gating switch NPS inis not lowered (dropped) to a negative power gating voltage VPGN at once, but is lowered to a ground voltage VGND in an intermediate stage and then lowered to the negative power gating voltage VPGN. This reduces power consumed by a power gating operation of a second power gating circuit.

2 2 2 Since power is proportional to the square of the voltage, the power consumed by the power gating operation may be reduced by raising (or lowering) the voltage level of the positive power gating switch PPS (or the negative power gating switch NPS) twice instead of once. For example, when voltage is raised from 0 V to 1.2 V, the power consumption when the voltage is raised twice, from 0 V to 1 V and then from 1 V to 1.2 V, is less than the power consumption when the voltage is raised from 0 V to 1.2 V all at once (1.2>10.2).

2 FIG. 3 FIG. 4 FIG. 100 100 is a block diagram of the memory deviceaccording to an embodiment.is a diagram showing a power gating circuit and a peripheral circuit that are included in the memory deviceaccording to an embodiment.is a timing chart of the power gating circuit according to an embodiment.

2 FIG. 100 is a diagram conceptually showing the configuration of the memory deviceimplemented as a DRAM.

2 FIG. 2 FIG. 100 110 120 130 140 130 140 120 130 140 120 Referring to, the memory devicemay include a memory cell array, a peripheral circuit, a power gating circuit, and a voltage generator.illustrates that the power gating circuitand the voltage generatorare separate from the peripheral circuit, but the embodiment is not limited thereto. According to embodiments, the power gating circuitand the voltage generatormay be provided inside the peripheral circuit.

120 121 123 125 127 120 The peripheral circuitmay include a control logic circuit, a row decoder, a column decoder, and a sense amplifier. The peripheral circuitmay further include an address buffer (not shown), an input/output gating circuit (not shown), and a data input/output circuit (not shown).

110 123 127 110 The memory cell arraymay be connected to the row decodervia word lines WL and connected to the sense amplifiervia bit lines BL. The memory cell arraymay include a plurality of bank memory arrays. Each of the plurality of bank memory arrays may include a plurality of word lines WL, a plurality of bit lines BL, and a plurality of memory cells formed at intersections between the word lines WL and the bit lines BL.

123 125 127 The row decodermay include bank row decoders respectively connected to the plurality of bank memory arrays, and the column decodermay include bank column decoders respectively connected to the plurality of bank memory arrays. The sense amplifiermay include sense amplifiers respectively connected to the plurality of bank memory arrays.

100 One bank memory array, one bank row decoder, one bank column decoder, and one sense amplifier may constitute one bank. Here, the one bank memory array, the one bank row decoder, the one bank column decoder, and the one sense amplifier may be referred to as core circuits of the corresponding bank. According to embodiments, the memory devicemay include various numbers of banks.

121 20 100 121 123 125 121 121 121 121 1 FIG. 2 FIG. The control logic circuitmay include an address buffer (not shown). The address buffer (not shown) may receive the address ADDR, including a row address and a column address, from the memory controller() connected to the memory device. Also, the address buffer (not shown) may receive a bank address and provide the bank address to the control logic circuit, provide the received row address to the row decoder, and provide the received column address to the column decoder. The control logic circuitmay generate bank control signals in response to the bank address. In response to the bank control signals, a bank row decoder, corresponding to the bank address, among the plurality of bank row decoders may be activated, and a bank column decoder, corresponding to the bank address, among the plurality of bank column decoders may be activated. In an embodiment of, it is described that the control logic circuitincludes the address buffer (not shown), but the embodiment is not limited thereto. According to embodiments, the address buffer (not shown) may be provided outside the control logic circuitand thus be separated from the control logic circuit.

121 100 121 100 121 The control logic circuitmay control all operations of the memory device. The control logic circuitmay generate control signals for performing a write operation and/or a read operation of the memory device. Also, the control logic circuitmay output a voltage control signal CTRL_VOL and/or a power gating enable signal PGEN.

140 140 The voltage generatormay generate various types of voltages for performing program, read, and erase operations on the basis of the voltage control signal CTRL_VOL. The voltage generatormay be formed as a low dropout regulator (LDO) or a charge pump circuit, etc.

140 140 1 2 2 FIG. Also, the voltage generatormay generate voltages for the power gating operation. Referring to, the voltage generatormay generate a negative power gating voltage VPGN and the positive power gating voltage VPGP on the basis of a first power supply voltage VDDand/or the second power supply voltage VDD.

1 100 2 1 2 2 Here, the first power supply voltage VDDmay include a voltage that is supplied to an internal core logic of the memory device, and the second power supply voltage VDDmay include a voltage that is supplied to a memory cell and an input/output interface. For example, the first power supply voltage VDDmay be 1.0 V, and the second power supply voltage VDDmay be 1.8 V. Also, the positive power gating voltage VPGP may be higher than the second power supply voltage VDD, and the negative power gating voltage VPGN may be lower than a ground voltage VGN (e.g., 0 V).

121 100 Also, the control logic circuitmay include a mode register for setting a plurality of operating options of the memory deviceand a command decoder for decoding the command CMD received from a memory controller.

121 100 100 100 100 100 100 Also, in response to the command CMD, the control logic circuitmay control the operations of the memory deviceso that the memory deviceoperates in the active mode ACT or the standby mode STBY. Here, the active mode ACT represents a state in which the memory deviceis operating normally and processing data, and the memory devicein the active mode ACT may perform the write operation and/or the read operation. The standby mode STBY represents a state in which the memory deviceis in an idle state, and the memory devicein the standby mode STBY may maintain data and not perform the write operation and the read operation.

121 130 2 120 121 130 2 120 For example, the control logic circuitmay output the power gating enable signal PGEN having a logic low level in response to the command CMD indicating the active mode ACT. The power gating circuitmay provide the second power supply voltage VDD(or the ground voltage VGND) to the peripheral circuitin response to the power gating enable signal PGEN having the logic low level. Also, the control logic circuitmay output the power gating enable signal PGEN having a logic high level in response to the command CMD indicating the standby mode STBY. The power gating circuitmay block the second power supply voltage VDD(or the ground voltage VGND), provided to the peripheral circuit, in response to the power gating enable signal PGEN having the logic high level.

127 127 110 127 The sense amplifiermay be connected to an input/output gating circuit (not shown), and the input/output gating circuit (not shown) may be connected to a data input/output circuit (not shown). The sense amplifiermay sense data stored in the memory cell and transmit the sensed data to the data input/output circuit (not shown) so that the data may be output to the memory controller via data pad(s). The data input/output circuit (not shown) may receive data, which is to be written to the memory cells, from the memory controller via the data pad(s) and transmit the data to the memory cell array. The input/output gating circuit (not shown) may output read data by using a data line amplifier that receives and amplifies the data sensed by the sense amplifier. The read data may be output to the memory controller via the data pad(s). The input/output gating circuit (not shown) may include circuits for gating input/output data DATA or DQ, a column selection circuit, input data mask logic, read data latches for storing read data output from the bank memory arrays, and write drivers for writing data on the bank memory arrays.

20 1 FIG. The read data output from one bank memory array may be sensed by the corresponding sense amplifier and stored in the read data latches. The write data, which is to be written on the memory cell array of one bank memory array, may be provided from the memory controller() to the data input/output circuit (not shown). The data provided to the data input/output circuit (not shown) may be written on the bank memory array via the write driver.

100 130 120 130 121 123 125 127 120 The memory devicemay include the power gating circuitthat selectively supplies power to the peripheral circuit. The power gating circuitmay selectively supply power to each of the control logic circuit, the row decoder, the column decoder, the sense amplifier, the address buffer (not shown), the input/output gating circuit (not shown), and/or the data input/output circuit (not shown), which are provided in the peripheral circuit.

130 120 100 130 120 100 Also, the power gating circuitmay allow or block providing the power supply voltage (or the ground voltage) to the peripheral circuitdepending on the mode of the memory device(the active mode ACT or the standby mode STBY). That is, the power gating circuitmay selectively supply power to the peripheral circuitdepending on the mode of the memory device.

2 3 FIGS.and 3 FIG. 130 200 300 200 210 300 310 Referring to, the power gating circuitmay include the first power gating circuitand the second power gating circuit. Referring to, the first power gating circuitmay include the positive power gating switch PPS and a boosting control circuit, and the second power gating circuitmay include the negative power gating switch NPS and a dropping control circuit.

Switches described below may include a metal oxide silicon field effect transistor (MOSFET), but the inventive concept is not limited thereto. For example, the positive power gating switch PPS may be formed as a p-channel metal-oxide semiconductor (PMOS) transistor, and the negative power gating switch NPS may be formed as an n-channel metal-oxide semiconductor (NMOS) transistor.

2 3 FIGS.and 200 120 2 2 120 210 Referring to, the first power gating circuitmay be connected between the peripheral circuitand a line of the second power supply voltage VDD. A source terminal of the positive power gating switch PPS may be connected to the line of the second power supply voltage VDD, and a drain terminal of the positive power gating switch PPS may be connected to the peripheral circuitvia a node NPWR. A gate terminal of the positive power gating switch PPS may be connected to the boosting control circuitvia a node NPG.

120 2 120 120 Here, the node NPWR may refer to a head node of the peripheral circuitand represent a node from which current from the line of the second power supply voltage VDDbegins to be distributed to the peripheral circuit. That is, the node NPWR may represent a start point for the current that flows in the peripheral circuit.

210 210 2 In response to the power gating enable signal PGEN, the boosting control circuitmay adjust a voltage level of the node NPG connected to the gate terminal of the positive power gating switch PPS. The boosting control circuitmay be connected to a line of the ground voltage VGND, the line of the second power supply voltage VDD, and/or a line of the positive power gating voltage VPGP.

3 FIG. 210 2 120 Referring to, in the active mode ACT, the boosting control circuitmay turn on the positive power gating switch PPS by adjusting the voltage level of the node NPG to the ground voltage VGND. Accordingly, the line of the second power supply voltage VDDmay be connected to the peripheral circuit.

210 2 2 120 On the other hand, in the standby mode STBY, the boosting control circuitmay turn off the positive power gating switch PPS by adjusting the voltage level of the node NPG to the second power supply voltage VDDand then further adjusting the voltage level to the positive power gating voltage VPGP. Accordingly, the line of the second power supply voltage VDDmay be disconnected from the peripheral circuit.

3 4 FIGS.and 1 121 210 1 210 1 210 2 2 1 210 3 121 210 3 210 Referring to, at a point in time t, the control logic circuitmay provide the power gating enable signal PGEN having the logic high level to the boosting control circuitin response to the command CMD indicating the standby mode STBY. At the point in time t, the boosting control circuitresponds to the power gating enable signal PGEN having the logic high level. From the point in time t, the boosting control circuitmay raise the voltage level of the node NPG to the second power supply voltage VDD. From a point in time tdelayed by a predetermined amount of time after the point in time t, the boosting control circuitmay raise the voltage level of the node NPG to the positive power gating voltage VPGP. Subsequently, at a point in time t, the control logic circuitmay provide the power gating enable signal PGEN having the logic low level to the boosting control circuitin response to the command CMD indicating the active mode ACT. From the point in time t, the boosting control circuitmay lower the voltage level of the node NPG to the ground voltage VGND in response to the power gating enable signal PGEN having the logic low level.

2 200 According to the inventive concept, the voltage level of the node NPG is not raised to the positive power gating voltage VPGP at once, but is raised to the second power supply voltage VDDin an intermediate stage and then raised to the positive power gating voltage VPGP. This may reduce the power consumed by the power gating operation of the first power gating circuit.

2 3 FIGS.and 300 120 120 310 Referring to, the second power gating circuitmay be connected between the peripheral circuitand the line of the ground voltage VGND. A source terminal of the negative power gating switch NPS may be connected to the line of the ground voltage VGND, and a drain terminal of the negative power gating switch NPS may be connected to the peripheral circuitvia a node NGND. A gate terminal of a negative power gating switch NPS may be connected to the dropping control circuitvia a node NNG.

120 120 120 Here, the node NGND may refer to a foot node of the peripheral circuitand represent a node through which the current from the peripheral circuitpasses just before escaping to the line of the ground voltage VGND. That is, the node NGND may represent an end point for the current that flows in the peripheral circuit.

310 310 2 In response to the power gating enable signal PGEN, the dropping control circuitmay adjust a voltage level of the node NNG connected to the gate terminal of the negative power gating switch NPS. The dropping control circuitmay be connected to the line of the second power supply voltage VDD, the line of the ground voltage VGND, and/or a line of the negative power gating voltage VPGN.

3 FIG. 310 2 120 Referring to, in the active mode ACT, the dropping control circuitmay turn on the negative power gating switch NPS by adjusting the voltage level of the node NNG to the second power supply voltage VDD. Accordingly, the line of the ground voltage VGND may be connected to the peripheral circuit.

310 120 On the other hand, in the standby mode STBY, the dropping control circuitmay turn off the negative power gating switch NPS by adjusting the voltage level of the node NNG to the ground voltage VGND and then further adjusting the voltage level to the negative power gating voltage VPGN. Accordingly, the line of the ground voltage VGND may be disconnected from the peripheral circuit.

3 4 FIGS.and 1 121 310 1 310 1 310 2 1 310 3 121 310 3 310 2 Referring to, at the point in time t, the control logic circuitmay provide the power gating enable signal PGEN having the logic high level to the dropping control circuitin response to the command CMD indicating the standby mode STBY. At the point in time t, the dropping control circuitresponds to the power gating enable signal PGEN having the logic high level. From the point in time t, the dropping control circuitmay lower the voltage level of the node NNG to the ground voltage VGND. From the point in time tdelayed by the predetermined amount of time after the point in time t, the dropping control circuitmay lower the voltage level of the node NNG to the negative power gating voltage VPGN. Subsequently, at the point in time t, the control logic circuitmay provide the power gating enable signal PGEN having the logic low level to the dropping control circuitin response to the command CMD indicating the active mode ACT. From the point in time t, the dropping control circuitmay raise the voltage level of the node NNG to the second power supply voltage VDDin response to the power gating enable signal PGEN having the logic low level.

300 According to the inventive concept, the voltage level of the node NNG is not lowered to the negative power gating voltage VPGN at once, but is lowered to the ground voltage VGND in an intermediate stage and then lowered to the negative power gating voltage VPGN. This may reduce the power consumed by the power gating operation of the second power gating circuit.

5 FIG. 210 a is a block diagram of an example of a boosting control circuitaccording to the inventive concept.

5 FIG. 210 211 212 213 214 215 216 a a a a a a a. Referring to, the boosting control circuitmay include a pulse generating circuit, a first inverter chain circuit, a boosting switch, a delay circuit, a second inverter chain circuit, and a short protection circuit

211 211 a a The pulse generating circuitmay output a pulse signal NPLS in response to the power gating enable signal PGEN. For example, when the power gating enable signal PGEN transitions from the logic low level to the logic high level, the pulse generating circuitmay output the pulse signal NPLS having the logic low level.

212 215 212 215 a a a a Each of the first inverter chain circuitand the second inverter chain circuitmay include a plurality of inverter circuits that are connected to each other in series. Here, a positive power supply terminal of each of the inverter circuits may be connected to the line of the positive power gating voltage VPGP, and a negative power supply terminal of each of the inverter circuits may be connected to the line of the ground voltage VGND. The first inverter chain circuitand the second inverter chain circuitmay output the positive power gating voltage VPGP or the ground voltage VGND according to a logic level of an input signal.

212 1 a a The first inverter chain circuitmay receive the pulse signal NPLS as an input signal and output the positive power gating voltage VPGP or the ground voltage VGND as a first power gating signal PGaccording to the logic level of the pulse signal NPLS.

215 2 a a The second inverter chain circuitmay receive the power gating enable signal PGEN as an input signal and output the positive power gating voltage VPGP or the ground voltage VGND as a second power gating signal PGaccording to the logic level of the power gating enable signal PGEN.

213 2 213 1 213 1 2 213 1 2 a a a a a a a The boosting switchmay be connected between the line of the second power supply voltage VDDand the node NPG. The boosting switchmay be turned on or off in response to the first power gating signal PG. For example, the boosting switchmay be turned on in response to the first power gating signal PGhaving the level of the ground voltage VGND, and accordingly, the line of the second power supply voltage VDDmay be connected to the node NPG. Also, the boosting switchmay be turned off in response to the first power gating signal PGhaving the level of the positive power gating voltage VPGP, and accordingly, the line of the second power supply voltage VDDmay be disconnected from the node NPG.

214 a The delay circuitmay receive the pulse signal NPLS as an input signal and output a delayed pulse signal NPLS_D. Here, the delayed pulse signal NPLS_D may represent a pulse signal having a form in which a period of time having a specific logic level of the pulse signal NPLS has been increased by a predetermined amount of time. For example, when the pulse signal NPLS has a logic low level, the delayed pulse signal NPLS_D may represent a pulse signal having a form in which a period of time having the logic low level of the pulse signal NPLS has been increased by a predetermined amount of time.

216 215 216 216 215 216 2 a a a a a a a. The short protection circuitmay be connected between the second inverter chain circuitand the node NPG. The short protection circuitmay be turned on or off in response to the delayed pulse signal NPLS_D. For example, the short protection circuitmay be turned on in response to the delayed pulse signal NPLS_D having the logic high level, and accordingly, the second inverter chain circuitmay be connected to the node NPG. Accordingly, the short protection circuitmay provide the node NPG with the positive power gating voltage VPGP or the ground voltage VGND, which represents the voltage level of the second power gating signal PG

216 215 216 215 2 213 a a a a a. Also, the short protection circuitmay be turned off in response to the delayed pulse signal NPLS_D having the logic low level, and accordingly, the second inverter chain circuitmay be disconnected from the node NPG. The short protection circuitmay prevent a short-circuit between the line of the positive power gating voltage VPGP connected to a positive power supply terminal of the second inverter chain circuitand the line of the second power supply voltage VDDconnected to the boosting switch

6 FIG. 5 FIG. 7 FIG.A 6 FIG. 7 FIG.B 8 FIG.A 6 FIG. 8 FIG.B 9 FIG. 6 FIG. 210 211 214 210 a a a a is a diagram of an equivalent circuit according to an example of the boosting control circuitof.shows an equivalent circuit according to an example of the pulse generating circuitof, andis a timing chart of the equivalent circuit.shows an equivalent circuit according to an example of the delay circuitof, andis a timing chart of the equivalent circuit.is a timing chart of the boosting control circuitof.

210 211 214 a a a 6 FIG. 7 7 FIGS.A andB 8 8 FIGS.A andB Prior to describing the boosting control circuitof, the pulse generating circuitand the delay circuitare described first with reference toand.

7 FIG.A 211 211 1 211 2 211 3 a a a a Referring to, the pulse generating circuitmay include a sub delay circuit-, an inverter circuit-, and a NAND logic circuit-.

211 1 211 2 211 3 a a a The sub delay circuit-may receive the power gating enable signal PGEN as an input signal and output a delayed power gating enable signal. The inverter circuit-may receive the delayed power gating enable signal as an input signal and output a delayed inverted power gating enable signal PGENb_D. The NAND logic circuit-may receive the power gating enable signal PGEN and the delayed inverted power gating enable signal PGENb_D as input signals and output the pulse signal NPLS.

211 1 211 1 a a The sub delay circuit-may output, as an output signal, a signal having a form in which the input signal is delayed by a predetermined pulse time t_NPLS. The pulse time t_NPLS may be determined in advance by considering a response speed or power consumption, etc. according to characteristics of current in total circuits. Also, the sub delay circuit-may be formed as an inverter chain circuit, etc., and the pulse time t_NPLS may be determined according to design parameters (e.g., the number of steps in the inverter chain, etc.).

7 FIG.B Referring to, when the power gating enable signal PGEN is continuously at a low level, the logic levels of both the delayed inverted power gating enable signal PGENb_D and the pulse signal NPLS may also be at the logic high level. When the power gating enable signal PGEN transitions from the logic low level to the logic high level, the delayed inverted power gating enable signal PGENb_D may transition from the logic high level to the logic low level after the pulse time t_NPLS has elapsed. Accordingly, the pulse signal NPLS may have the logic low level during the pulse time t_NPLS.

8 FIG.A 214 214 1 214 2 214 3 a a a a Referring to, the delay circuitmay include a sub delay circuit-, a NAND logic circuit-, and an inverter circuit-.

214 1 214 2 214 3 a a a 7 FIG.A The sub delay circuit-may receive the pulse signal NPLS ofas an input signal and output a pulse signal NPLS_SD having a form in which all of the pulse signal NPLS is delayed by a delay time DP. The NAND logic circuit-may receive the pulse signal NPLS and the delayed pulse signal NPLS_SD as input signals and output a delayed inverted pulse signal NPLSb_D. The inverter circuit-may receive the delayed inverted pulse signal NPLSb_D as an input signal and output the delayed pulse signal NPLS_D.

214 1 214 1 a a The sub delay circuit-may output, as an output signal, a signal having a form in which the input signal is delayed by a predetermined delay time DP. The delay time DP may be determined in advance by considering a response speed or power consumption, etc. according to characteristics of current in total circuits. Also, the sub delay circuit-may be formed as an inverter chain circuit, etc., and the pulse time t_NPLS may be determined according to design parameters (e.g., the number of steps in the inverter chain, etc.).

8 FIG.B Referring to, the delayed pulse signal NPLS_D may represent a pulse signal having a form in which a period of time having a specific logic level of the pulse signal NPLS has been increased by the predetermined delay time DP. When the pulse signal NPLS has a logic low level, the delayed pulse signal NPLS_D may represent a pulse signal having a form in which a period of time having the logic low level of the pulse signal NPLS has been increased by the predetermined delay time DP. Unlike the delayed pulse signal NPLS_D, a transition point in time of the delayed pulse signal NPLS_SD from the logic high level to the logic low level may also be delayed by the delay time DP. That is, in the delayed pulse signal NPLS_D, the transition point in time from the logic high level to the logic low level is maintained, and only the transition point in time from the logic low level to the logic high level may be delayed by the delay time DP in addition to the pulse time t_NPLS. Accordingly, a period of time for which the delayed pulse signal NPLS_D remains at the logic low level may be increased by the delay time DP.

6 FIG. 6 FIG. 6 9 FIGS.and 210 a Returning to, the boosting control circuitofis described with reference to.

6 FIG. 212 215 212 215 a a a a Referring to, each of the first inverter chain circuitand the second inverter chain circuitmay include two inverter circuits. However, the embodiment is not limited thereto, and the number of inverter circuits in the first and second inverter chain circuitsandmay vary according to embodiments. The number of inverter circuits may be determined by considering a response speed or power consumption, etc. according to characteristics of current in total circuits. Also, the inverter circuit may be formed as a complementary metal-insulator-semiconductor (CMOS) transistor and configured such that the NMOS transistor and the PMOS transistor in the inverter circuit operate in a complementary manner.

6 FIG. 212 212 1 212 2 212 1 212 2 212 1 212 2 1 a a a a a a a a Referring to, the first inverter chain circuitmay include an inverter circuit-and an inverter circuit-. The inverter circuit-and the inverter circuit-may be connected to each other in series. The inverter circuit-may receive the pulse signal NPLS as an input signal, and the inverter circuit-may output the positive power gating voltage VPGP or the ground voltage VGND as the first power gating signal PGaccording to the logic level of the pulse signal NPLS.

6 FIG. 212 2 1 1 1 1 1 1 212 1 1 1 1 1 212 1 a a a Referring to, the inverter circuit-may include a PMOS transistor IPTand an NMOS transistor INT. A source terminal of the PMOS transistor IPTmay be connected to the line of the positive power gating voltage VPGP, a drain terminal of the PMOS transistor IPTmay be connected to a gate terminal of a PMOS transistor BPT and a drain terminal of the NMOS transistor INT, and a gate terminal of the PMOS transistor IPTmay be connected to an output terminal of the inverter circuit-. A source terminal of the NMOS transistor INTmay be connected to the line of the ground voltage VGND, the drain terminal of the NMOS transistor INTmay be connected to the gate terminal of the PMOS transistor BPT and the drain terminal of the PMOS transistor IPT, and a gate terminal of the NMOS transistor INTmay be connected to the output terminal of the inverter circuit-.

6 FIG. 215 215 1 215 2 215 1 215 2 215 1 215 2 2 a a a a a a a a Referring to, the second inverter chain circuitmay include an inverter circuit-and an inverter circuit-. The inverter circuit-and the inverter circuit-may be connected to each other in series. The inverter circuit-may receive the power gating enable signal PGEN as an input signal, and the inverter circuit-may output the positive power gating voltage VPGP or the ground voltage VGND as the second power gating signal PGaccording to the logic level of the power gating enable signal PGEN.

6 FIG. 215 2 2 2 2 2 216 2 2 215 1 2 2 216 2 2 215 1 a a a a a Referring to, the inverter circuit-may include a PMOS transistor IPTand an NMOS transistor INT. A source terminal of the PMOS transistor IPTmay be connected to the line of the positive power gating voltage VPGP, a drain terminal of the PMOS transistor IPTmay be connected to the short protection circuitand a drain terminal of the NMOS transistor INT, and a gate terminal of the PMOS transistor IPTmay be connected to an output terminal of the inverter circuit-. A source terminal of the NMOS transistor INTmay be connected to the line of the ground voltage VGND, the drain terminal of the NMOS transistor INTmay be connected to the short protection circuitand the drain terminal of the PMOS transistor IPT, and a gate terminal of the NMOS transistor INTmay be connected to the output terminal of the inverter circuit-.

6 FIG. 213 2 1 1 2 1 2 a a a a Referring to, the boosting switchmay include the PMOS transistor BPT. The PMOS transistor BPT may be connected between the line of the second power supply voltage VDDand the node NPG. The PMOS transistor BPT may be turned on or off in response to the first power gating signal PG. For example, the PMOS transistor BPT may be turned on in response to the first power gating signal PGhaving the level of the ground voltage VGND, and accordingly, the line of the second power supply voltage VDDmay be connected to the node NPG. Also, the PMOS transistor BPT may be turned off in response to the first power gating signal PGhaving the level of the positive power gating voltage VPGP, and accordingly, the line of the second power supply voltage VDDmay be disconnected from the node NPG.

6 FIG. 216 1 1 1 215 2 1 1 1 1 215 2 1 1 1 a a a Referring to, the short protection circuitmay include an NMOS transistor SNTand a PMOS transistor SPT. A source terminal of the PMOS transistor SPTmay be connected to an output terminal of the inverter circuit-and a source terminal of the NMOS transistor SNT, a drain terminal of the PMOS transistor SPTmay be connected to the node NPG, and a gate terminal of the PMOS transistor SPTmay be connected to a line of the delayed inverted pulse signal NPLSb_D. The source terminal of the NMOS transistor SNTmay be connected to the output terminal of the inverter circuit-and the source terminal of the PMOS transistor SPT, a drain terminal of the NMOS transistor SNTmay be connected to the node NPG, and a gate terminal of the NMOS transistor SNTmay be connected to a line of the delayed pulse signal NPLS_D.

1 1 2 The NMOS transistor SNTmay be turned on in response to the delayed pulse signal NPLS_D having the logic high level. As the NMOS transistor SNTis turned on, the line of the ground voltage VGND connected to the NMOS transistor INTmay be connected to the node NPG. Accordingly, the ground voltage VGND may be provided to the node NPG.

1 1 2 The PMOS transistor SPTmay be turned on in response to the delayed inverted pulse signal NPLSb_D having the logic low level. As the PMOS transistor SPTis turned on, the line of the positive power gating voltage VPGP connected to the PMOS transistor IPTmay be connected to the node NPG. Accordingly, the positive power gating voltage VPGP may be provided to the node NPG.

1 1 215 216 215 2 213 a a a a. Also, the NMOS transistor SNTmay be turned off in response to the delayed pulse signal NPLS_D having the logic low level, and the PMOS transistor SPTmay be turned off in response to the delayed inverted pulse signal NPLSb_D having the logic high level. Accordingly, the second inverter chain circuitmay be disconnected from the node NPG. Here, the short protection circuitmay prevent the short-circuit between the line of the positive power gating voltage VPGP connected to the positive power supply terminal of the second inverter chain circuitand the line of the second power supply voltage VDDconnected to the boosting switch

9 FIG. 6 9 FIGS.and 1 121 1 3 121 3 121 210 1 3 a a a a a a a Referring to, the diagram shows a timing chart of the active mode ACT and the standby mode STBY. Referring to, prior to a point in time t, the control logic circuitmay output the power gating enable signal PGEN having the logic low level in response to the command CMD indicating the active mode ACT. From the point in time tto a point in time t, the control logic circuitmay output the power gating enable signal PGEN having the logic high level in response to the command CMD indicating the standby mode STBY. After the point in time t, the control logic circuitmay output the power gating enable signal PGEN having the logic low level in response to the command CMD indicating the active mode ACT. Hereafter, the operation of the boosting control circuitfrom the point in time tto the point in time tis described.

1 211 211 a a a From the point in time t, the pulse generating circuitmay output the pulse signal NPLS having the logic low level during the pulse time t_NPLS in response to the power gating enable signal PGEN having the logic high level. After the pulse time t_NPLS, the pulse generating circuitmay output the pulse signal NPLS having the logic high level.

1 212 2 212 1 212 2 212 1 a a a a a a a Also, from the point in time t, the inverter circuit-of the first inverter chain circuitmay output the first power gating signal PGhaving the level of the ground voltage VGND during the pulse time t_NPLS in response to the pulse signal NPLS having the logic low level. After the pulse time t_NPLS, the inverter circuit-of the first inverter chain circuitmay output the first power gating signal PGhaving the level of the positive power gating voltage VPGP in response to the pulse signal NPLS having the logic high level.

1 214 2 214 a a a a Also, from the point in time t, the delay circuitmay output the delayed pulse signal NPLS_D having the logic low level during the pulse time t_NPLS and the delay time DP in response to the pulse signal NPLS having the logic low level. From a point in time tafter the pulse time t_NPLS and the delay time DP, the delay circuitmay output the delayed pulse signal NPLS_D having the logic high level.

1 215 2 215 2 a a a a Also, from the point in time t, the inverter circuit-of the second inverter chain circuitmay output the second power gating signal PGhaving the level of the positive power gating voltage VPGP in response to the power gating enable signal PGEN having the logic high level.

1 1 2 2 1 2 2 2 2 a a a In addition, during the pulse time t_NPLS from the point in time t, the PMOS transistor BPT is turned on in response to the first power gating signal PGhaving the level of the ground voltage VGND. Accordingly, the second power supply voltage VDDmay be provided to the node NPG from the line of the second power supply voltage VDD. After the pulse time t_NPLS, the PMOS transistor BPT is turned off in response to the first power gating signal PGhaving the level of the positive power gating voltage VPGP. Accordingly, the second power supply voltage VDDmay not be supplied to the node NPG from the line of the second power supply voltage VDD. Here, during the delay time DP after the pulse time t_NPLS, the node NPG may be disconnected from both the line of the second power supply voltage VDDand the line of the positive power gating voltage VPGP, and accordingly, a short-circuit between the line of the second power supply voltage VDDand the line of the positive power gating voltage VPGP may be prevented.

2 1 1 a a The second power gating signal PGhaving the level of the positive power gating voltage VPGP may be output from the point in time t, but not be provided to the node NPG. This is because the logic level of the delayed inverted pulse signal NPLSb_D is logic high during the pulse time t_NPLS and the delay time DP, and thus, the PMOS transistor SPTis not turned on.

2 1 2 1 a a From the point in time tafter the pulse time t_NPLS and the delay time DP, the PMOS transistor SPTmay be turned on in response to the delayed inverted pulse signal NPLSb_D having the logic low level. From the point in time t, the PMOS transistor SPTis turned on, and thus, the positive power gating voltage VPGP may be provided to the node NPG from the line of the positive power gating voltage VPGP.

2 200 As described above, according to the inventive concept, the voltage level of the node NPG is not raised to the positive power gating voltage VPGP at once, but is raised to the second power supply voltage VDDin an intermediate stage and then raised to the positive power gating voltage VPGP. This may reduce the power consumed by the power gating operation of the first power gating circuit.

10 FIG. 310 a is a block diagram showing an example of a dropping control circuitaccording to the inventive concept.

10 FIG. 310 311 312 313 314 315 316 a a a a a a a. Referring to, the dropping control circuitmay include a pulse generating circuit, a third inverter chain circuit, a dropping switch, a delay circuit, a fourth inverter chain circuit, and a short protection circuit

311 311 a a The pulse generating circuitmay output a pulse signal PPLS in response to the power gating enable signal PGEN. For example, when the power gating enable signal PGEN transitions from the logic low level to the logic high level, the pulse generating circuitmay output the pulse signal PPLS having the logic high level.

312 315 2 312 315 2 a a a a Each of the third inverter chain circuitand the fourth inverter chain circuitmay include a plurality of inverter circuits that are connected to each other in series. Here, a positive power supply terminal of each of the inverter circuits may be connected to the line of the second power supply voltage VDD, and a negative power supply terminal of each of the inverter circuits may be connected to the line of the negative power gating voltage VPGN. The third inverter chain circuitand the fourth inverter chain circuitmay output the second power supply voltage VDDor the negative power gating voltage VPGN according to a logic level of an input signal.

312 2 1 a a The third inverter chain circuitmay receive the pulse signal PPLS as an input signal and output the second power supply voltage VDDor the negative power gating voltage VPGN as a first power gating signal NGaccording to the logic level of the pulse signal PPLS.

315 2 2 a a The fourth inverter chain circuitmay receive the power gating enable signal PGEN as an input signal and output the second power supply voltage VDDor the negative power gating voltage VPGN as a second power gating signal NGaccording to the logic level of the power gating enable signal PGEN.

313 313 1 313 1 2 313 1 a a a a a a a The dropping switchmay be connected between the line of the ground voltage VGND and the node NNG. The dropping switchmay be turned on or off in response to the first power gating signal NG. For example, the dropping switchmay be turned on in response to the first power gating signal NGhaving the level of the second power supply voltage VDD, and accordingly, the line of the ground voltage VGND may be connected to the node NNG. Also, the dropping switchmay be turned off in response to the first power gating signal NGhaving the negative power gating voltage VPGN, and accordingly, the line of the ground voltage VGND may be disconnected from the node NNG.

314 a The delay circuitmay receive the pulse signal PPLS as an input signal and output a delayed inverted pulse signal PPLSb_D. Here, the delayed inverted pulse signal PPLSb_D may represent a pulse signal having a form in which a period of time having a specific logic level of the inverted signal of the pulse signal PPLS has been increased by a predetermined amount of time. For example, when the pulse signal PPLS has the logic high level, the delayed inverted pulse signal PPLSb_D may represent the inverted signal of the pulse signal PPLS, and the delayed inverted pulse signal PPLSb_D may be a pulse signal having a form in which a period of time having the logic low level is increased by a predetermined amount of time.

316 315 316 316 315 316 2 2 a a a a a a a. The short protection circuitmay be connected between the fourth inverter chain circuitand the node NNG. The short protection circuitmay be turned on or off in response to the delayed inverted pulse signal PPLSb_D. For example, the short protection circuitmay be turned on in response to the delayed inverted pulse signal PPLSb_D having the logic high level, and accordingly, the fourth inverter chain circuitmay be connected to the node NNG. Accordingly, the short protection circuitmay provide the node NNG with the second power supply voltage VDDor the negative power gating voltage VPGN, which represents the voltage level of the second power gating signal NG

316 315 316 315 313 a a a a a. Also, the short protection circuitmay be turned off in response to the delayed inverted pulse signal PPLSb_D having the logic low level, and accordingly, the fourth inverter chain circuitmay be disconnected from the node NNG. Here, the short protection circuitmay prevent the short-circuit between the line of the negative power gating voltage VPGN connected to the negative power supply terminal of the fourth inverter chain circuitand the line of the ground voltage VGND connected to the dropping switch

11 FIG. 10 FIG. 12 FIG.A 11 FIG. 12 FIG.B 13 FIG.A 11 FIG. 13 FIG.B 14 FIG. 11 FIG. 310 311 314 310 a a a a is a diagram of an equivalent circuit according to an example of the dropping control circuitof.shows an equivalent circuit according to an example of the pulse generating circuitof, andis a timing chart of the equivalent circuit.shows an equivalent circuit according to an example of the delay circuitof, andis a timing chart of the equivalent circuit.is a timing chart of the dropping control circuitof.

310 311 314 a a a 11 FIG. 12 12 FIGS.A andB 13 13 FIGS.A andB Prior to describing the dropping control circuitof, the pulse generating circuitand the delay circuitare described first with reference toand.

12 FIG.A 311 311 1 311 2 311 3 311 4 a a a a a Referring to, the pulse generating circuitmay include a sub delay circuit-, an inverter circuit-, a NAND logic circuit-, and an inverter circuit-.

311 1 311 2 311 3 311 4 a a a a The sub delay circuit-may receive the power gating enable signal PGEN as an input signal and output a delayed power gating enable signal. The inverter circuit-may receive the delayed power gating enable signal as an input signal and output a delayed inverted power gating enable signal PGENb_D. The NAND logic circuit-may receive the power gating enable signal PGEN and the delayed inverted power gating enable signal PGENb_D as input signals and output the pulse signal NPLS. The inverter circuit-may receive the pulse signal NPLS as an input signal and output the pulse signal PPLS by inverting the pulse signal NPLS.

311 1 311 1 a a Here, the sub delay circuit-may output, as an output signal, a signal having a form in which the input signal is delayed by a predetermined pulse time t_PPLS. The pulse time t_PPLS may be determined in advance by considering a response speed or power consumption, etc., according to characteristics of current in total circuits. Also, the sub delay circuit-may be formed as an inverter chain circuit, etc., and the pulse time t_PPLS may be determined according to design parameters (e.g., the number of steps in the inverter chain, etc.).

12 FIG.B Referring to, when the power gating enable signal PGEN is continuously at a low level, the logic levels of both the delayed inverted power gating enable signal PGENb_D and the pulse signal NPLS may also be at the logic high level. When the power gating enable signal PGEN transitions from the logic low level to the logic high level, the delayed inverted power gating enable signal PGENb_D may transition from the logic high level to the logic low level after a pulse time t_PPLS has elapsed. Accordingly, the pulse signal NPLS may have the logic low level during the pulse time t_PPLS. Since the pulse signal NPLS has the logic low level during the pulse time t_PPLS, the pulse signal PPLS, which is the inverted signal of the pulse signal NPLS, may have the logic high level during the pulse time t_PPLS.

13 FIG.A 314 314 1 314 2 314 3 a a a a Referring to, the delay circuitmay include a sub delay circuit-, a NOR logic circuit-, and an inverter circuit-.

314 1 314 2 314 3 a a a 12 FIG.A The sub delay circuit-may receive the pulse signal PPLS ofas an input signal and output a pulse signal PPLS_SD having a form in which all of the pulse signal PPLS is delayed by a delay time DN. The NOR logic circuit-may receive the pulse signal PPLS and the delayed pulse signal PPLS_SD as input signals and output a delayed inverted pulse signal PPLSb_D. The inverter circuit-may receive the delayed inverted pulse signal PPLSb_D as an input signal and output a delayed pulse signal PPLS_D.

314 1 314 1 a a Here, the sub delay circuit-may output, as an output signal, a signal having a form in which the input signal is delayed by a predetermined delay time DN. The delay time DN may be determined in advance by considering a response speed or power consumption, etc., according to characteristics of current in total circuits. Also, the sub delay circuit-may be formed as an inverter chain circuit, etc., and the pulse time t_PPLS may be determined according to design parameters (e.g., the number of steps in the inverter chain, etc.).

13 FIG.B Referring to, here, the delayed inverted pulse signal PPLSb_D may represent an inverted signal of a pulse signal having a form in which a period of time having a specific logic level of the pulse signal PPLS has been increased by the predetermined delay time DN. When the pulse signal PPLS has a logic high level, the delayed inverted pulse signal PPLSb_D may represent the inverted signal of the pulse signal having a form in which a period of time having the logic high level of the pulse signal PPLS has been increased by the predetermined delay time DN.

11 FIG. 11 FIG. 11 14 FIGS.and 310 a Returning to, the dropping control circuitofis described with reference to.

312 315 312 315 a a a a The third inverter chain circuitmay include two inverter circuits, and the fourth inverter chain circuitmay include three inverter circuits. However, the embodiment is not limited thereto, and the number of inverter circuits in the third and fourth inverter chain circuitsandmay vary according to embodiments. The number of inverter circuits may be determined by considering a response speed or power consumption, etc., according to characteristics of current in total circuits. Also, the inverter circuit may be formed as the CMOS transistor and configured such that the NMOS transistor and the PMOS transistor in the inverter circuit operate in a complementary manner.

11 FIG. 312 312 1 312 2 312 1 312 2 312 1 312 2 2 1 a a a a a a a a Referring to, the third inverter chain circuitmay include an inverter circuit-and an inverter circuit-. The inverter circuit-and the inverter circuit-may be connected to each other in series. The inverter circuit-may receive the pulse signal PPLS as an input signal, and the inverter circuit-may output the second power supply voltage VDDor the negative power gating voltage VPGN as a first power gating signal NGaccording to the logic level of the pulse signal PPLS.

11 FIG. 312 2 3 3 3 2 3 3 3 312 1 3 3 3 3 312 1 a a a Referring to, the inverter circuit-may include a PMOS transistor IPTand an NMOS transistor INT. A source terminal of the PMOS transistor IPTmay be connected to the line of the second power supply voltage VDD, a drain terminal of the PMOS transistor IPTmay be connected to a gate terminal of an NMOS transistor DNT and a drain terminal of the NMOS transistor INT, and a gate terminal of the PMOS transistor IPTmay be connected to an output terminal of the inverter circuit-. A source terminal of the NMOS transistor INTmay be connected to the line of the negative power gating voltage VPGN, the drain terminal of the NMOS transistor INTmay be connected to the gate terminal of the NMOS transistor DNT and the drain terminal of the PMOS transistor IPT, and a gate terminal of the NMOS transistor INTmay be connected to the output terminal of the inverter circuit-.

11 FIG. 315 315 1 315 2 315 3 315 1 315 2 315 3 315 1 315 3 2 2 a a a a a a a a a a Referring to, the fourth inverter chain circuitmay include an inverter circuit-, an inverter circuit-, and an inverter circuit-. The inverter circuit-, the inverter circuit-, and the inverter circuit-may be connected to each other in series. The inverter circuit-may receive the power gating enable signal PGEN as an input signal, and the inverter circuit-may output the second power supply voltage VDDor the negative power gating voltage VPGN as a second power gating signal NGaccording to the logic level of the power gating enable signal PGEN.

11 FIG. 315 3 4 4 4 2 4 316 4 4 315 2 4 4 316 4 4 315 2 a a a a a Referring to, the inverter circuit-may include a PMOS transistor IPTand an NMOS transistor INT. A source terminal of the PMOS transistor IPTmay be connected to the line of the second power supply voltage VDD, a drain terminal of the PMOS transistor IPTmay be connected to the short protection circuitand a drain terminal of the NMOS transistor INT, and a gate terminal of the PMOS transistor IPTmay be connected to an output terminal of the inverter circuit-. A source terminal of the NMOS transistor INTmay be connected to the line of the negative power gating voltage VPGN, the drain terminal of the NMOS transistor INTmay be connected to the short protection circuitand the drain terminal of the PMOS transistor IPT, and a gate terminal of the NMOS transistor INTmay be connected to the output terminal of the inverter circuit-.

11 FIG. 313 313 1 1 2 1 a a a a a Referring to, the dropping switchmay include the NMOS transistor DNT. The dropping switchmay be connected between the line of the ground voltage VGND and the node NNG. The NMOS transistor DNT may be turned on or off in response to the first power gating signal NG. For example, the NMOS transistor DNT may be turned on in response to the first power gating signal NGhaving the level of the second power supply voltage VDD, and accordingly, the line of the ground voltage VGND may be connected to the node NNG. Also, the NMOS transistor DNT may be turned off in response to the first power gating signal NGhaving the level of the negative power gating voltage VPGN, and accordingly, the line of the ground voltage VGND may be disconnected from the node NNG.

11 FIG. 316 2 2 2 315 3 2 2 2 2 315 3 2 2 2 a a a Referring to, the short protection circuitmay include an NMOS transistor SNTand a PMOS transistor SPT. A source terminal of the PMOS transistor SPTmay be connected to an output terminal of the inverter circuit-and a source terminal of the NMOS transistor SNT, a drain terminal of the PMOS transistor SPTmay be connected to the node NNG, and a gate terminal of the PMOS transistor SPTmay be connected to a line of the delayed pulse signal PPLS_D. The source terminal of the NMOS transistor SNTmay be connected to the output terminal of the inverter circuit-and the source terminal of the PMOS transistor SPT, a drain terminal of the NMOS transistor SNTmay be connected to the node NNG, and a gate terminal of the NMOS transistor SNTmay be connected to the line of the delayed inverted pulse signal PPLSb_D.

2 2 4 The NMOS transistor SNTmay be turned on in response to the delayed inverted pulse signal PPLSb_D having the logic high level. As the NMOS transistor SNTis turned on, the line of the negative power gating voltage VPGN connected to the NMOS transistor INTmay be connected to the node NNG. Accordingly, the negative power gating voltage VPGN may be provided to the node NNG.

2 2 2 4 2 The PMOS transistor SPTmay be turned on in response to the delayed pulse signal PPLS_D having the logic low level. As the PMOS transistor SPTis turned on, the line of the second power supply voltage VDDconnected to the PMOS transistor IPTmay be connected to the node NNG. Accordingly, the second power supply voltage VDDmay be provided to the node NNG.

2 2 315 316 315 313 a a a a. Also, the NMOS transistor SNTmay be turned off in response to the delayed inverted pulse signal PPLSb_D having the logic low level, and the PMOS transistor SPTmay be turned off in response to the delayed pulse signal PPLS_D having the logic high level. Accordingly, the fourth inverter chain circuitmay be disconnected from the node NNG. Here, the short protection circuitmay prevent the short-circuit between the line of the negative power gating voltage VPGN connected to the negative power supply terminal of the fourth inverter chain circuitand the line of the ground voltage VGND connected to the dropping switch

14 FIG. 11 14 FIGS.and 1 121 1 3 121 3 121 310 1 3 b b b b a b b Referring to, the diagram shows a timing chart of the active mode ACT and the standby mode STBY. Referring to, prior to a point in time t, the control logic circuitmay output the power gating enable signal PGEN having the logic low level in response to the command CMD indicating the active mode ACT. From the point in time tto a point in time t, the control logic circuitmay output the power gating enable signal PGEN having the logic high level in response to the command CMD indicating the standby mode STBY. After the point in time t, the control logic circuitmay output the power gating enable signal PGEN having the logic low level in response to the command CMD indicating the active mode ACT. Hereafter, the operation of the dropping control circuitfrom the point in time tto the point in time tis described.

1 311 311 b a a From the point in time t, the pulse generating circuitmay output the pulse signal PPLS having the logic high level during the pulse time t_PPLS in response to the power gating enable signal PGEN having the logic high level. After the pulse time t_PPLS, the pulse generating circuitmay output the pulse signal PPLS having the logic low level.

1 312 2 312 1 2 312 2 312 1 b a a a a a a Also, from the point in time t, the inverter circuit-of the third inverter chain circuitmay output the first power gating signal NGhaving the level of the second power supply voltage VDDduring the pulse time t_PPLS in response to the pulse signal PPLS having the logic high level. After the pulse time t_PPLS, the inverter circuit-of the third inverter chain circuitmay output the first power gating signal NGhaving the level of the negative power gating voltage VPGN in response to the pulse signal PPLS having the logic low level.

1 314 2 314 b a b a Also, from the point in time t, the delay circuitmay output the delayed inverted pulse signal PPLSb_D having the logic low level during the pulse time t_PPLS and the delay time DN in response to the pulse signal PPLS having the logic high level. From a point in time tafter the pulse time t_PPLS and the delay time DN, the delay circuitmay output the delayed inverted pulse signal PPLSb_D having the logic high level.

1 315 3 315 2 b a a a Also, from the point in time t, the inverter circuit-of the fourth inverter chain circuitmay output the second power gating signal NGhaving the level of the negative power gating voltage VPGN in response to the power gating enable signal PGEN having the logic high level.

1 1 2 1 b a a In addition, during the pulse time t_PPLS from the point in time t, the NMOS transistor DNT is turned on in response to the first power gating signal NGhaving the level of the second power supply voltage VDD. Accordingly, the ground voltage VGND may be provided to the node NNG from the line of the ground voltage VGND. After the pulse time t_PPLS, the NMOS transistor DNT is turned off in response to the first power gating signal NGhaving the level of the negative power gating voltage VPGN. Accordingly, the ground voltage VGND may not be supplied to the node NNG from the line of the ground voltage VGND. Here, during the delay time DN after the pulse time t_PPLS, the node NNG may be disconnected from both the line of the ground voltage VGND and the line of the negative power gating voltage VPGN, and accordingly, a short-circuit between the line of the ground voltage VGND and the line of the negative power gating voltage VPGN may be prevented.

2 1 2 a b The second power gating signal NGhaving the level of the negative power gating voltage VPGN may be output from the point in time t, but not be provided to the node NNG. This is because the logic level of the delayed pulse signal PPLS_D is logic high during the pulse time t_PPLS and the delay time DN, and thus, the PMOS transistor SPTis not turned on.

2 2 2 2 b b From the point in time tafter the pulse time t_PPLS and the delay time DN, the PMOS transistor SPTmay be turned on in response to the delayed pulse signal PPLS_D having the logic low level. From the point in time t, the PMOS transistor SPTis turned on, and thus, the negative power gating voltage VPGN may be provided to the node NNG from the line of the negative power gating voltage VPGN.

300 As described above, according to the inventive concept, the voltage level of the node NNG is not lowered to the negative power gating voltage VPGN at once, but is lowered to the ground voltage VGND in an intermediate stage and then lowered to the negative power gating voltage VPGN. This may reduce the power consumed by the power gating operation of the second power gating circuit.

15 FIG. 210 b is a block diagram showing another example of a boosting control circuitaccording to the inventive concept.

15 FIG. 210 211 212 213 214 215 216 217 218 219 b b b b b b b b b b. Referring to, the boosting control circuitmay include a pulse generating circuit, a first inverter chain circuit, a first boosting switch, a delay circuit, a second inverter chain circuit, a second boosting switch, a third inverter chain circuit, a dropping switch, and a voltage control circuit

211 211 b b The pulse generating circuitmay output the pulse signal NPLS in response to the power gating enable signal PGEN. For example, when the power gating enable signal PGEN transitions from the logic low level to the logic high level, the pulse generating circuitmay output the pulse signal NPLS having the logic low level.

212 215 217 b b b Each of the first inverter chain circuit, the second inverter chain circuit, and the third inverter chain circuitmay include a plurality of inverter circuits connected to each other in series.

212 215 212 215 212 215 217 2 217 217 2 b b b b b b b b b Here, a positive power supply terminal of each of inverter circuits of the first inverter chain circuitand the second inverter chain circuitmay be connected to the line of the positive power gating voltage VPGP, and a negative power supply terminal of each of the inverter circuits of the first inverter chain circuitand the second inverter chain circuitmay be connected to the line of the ground voltage VGND. The first inverter chain circuitand the second inverter chain circuitmay output the positive power gating voltage VPGP or the ground voltage VGND according to a logic level of an input signal. A positive power supply terminal of each of inverter circuits of the third inverter chain circuitmay be connected to the line of the second power supply voltage VDD, and a negative power supply terminal of each of the inverter circuits of the third inverter chain circuitmay be connected to the line of the ground voltage VGND. The third inverter chain circuitmay output the second power supply voltage VDDor the ground voltage VGND according to a logic level of an input signal.

15 FIG. 217 b In some embodiments, unlike that shown in, the positive power supply terminal of each of the inverter circuits of the third inverter chain circuitmay be connected to the line of the positive power gating voltage VPGP.

212 1 b b The first inverter chain circuitmay receive the pulse signal NPLS as an input signal and output the positive power gating voltage VPGP or the ground voltage VGND as a first power gating signal PGaccording to the logic level of the pulse signal NPLS.

215 2 b b The second inverter chain circuitmay receive a voltage control signal PCTRL_VOL as an input signal and output the positive power gating voltage VPGP or the ground voltage VGND as a second power gating signal PGaccording to the logic level of the voltage control signal PCTRL_VOL.

217 2 3 b b The third inverter chain circuitmay receive the power gating enable signal PGEN as an input signal and output the second power supply voltage VDDor the ground voltage VGND as a third power gating signal PGaccording to the logic level of the power gating enable signal PGEN.

213 2 213 1 213 1 2 213 1 2 b b b b b b b The first boosting switchmay be connected between the line of the second power supply voltage VDDand the node NPG. The first boosting switchmay be turned on or off in response to the first power gating signal PG. For example, the first boosting switchmay be turned on in response to the first power gating signal PGhaving the level of the ground voltage VGND, and accordingly, the line of the second power supply voltage VDDmay be connected to the node NPG. Also, the first boosting switchmay be turned off in response to the first power gating signal PGhaving the level of the positive power gating voltage VPGP, and accordingly, the line of the second power supply voltage VDDmay be disconnected from the node NPG.

216 216 2 216 2 216 2 b b b b b b b The second boosting switchmay be connected between the line of the positive power gating voltage VPGP and the node NPG. The second boosting switchmay be turned on or off in response to the second power gating signal PG. For example, the second boosting switchmay be turned on in response to the second power gating signal PGhaving the level of the ground voltage VGND, and accordingly, the line of the positive power gating voltage VPGP may be connected to the node NPG. Also, the second boosting switchmay be turned off in response to the second power gating signal PGhaving the level of the positive power gating voltage VPGP, and accordingly, the line of the positive power gating voltage VPGP may be disconnected from the node NPG.

218 218 3 218 3 2 218 3 b b b b b b b The dropping switchmay be connected between the line of the ground voltage VGND and the node NPG. The dropping switchmay be turned on or off in response to the third power gating signal PG. For example, the dropping switchmay be turned on in response to the third power gating signal PGhaving the level of the second power supply voltage VDD, and accordingly, the line of the ground voltage VGND may be connected to the node NPG. Also, the dropping switchmay be turned off in response to the third power gating signal PGhaving the level of the ground voltage VGND, and accordingly, the line of the ground voltage VGND may be disconnected from the node NPG.

214 b The delay circuitmay receive the pulse signal NPLS as an input signal and output the delayed inverted pulse signal NPLSb_D. Here, the delayed inverted pulse signal NPLSb_D may represent a pulse signal having a form in which a period of time having a specific logic level of the inverted signal of the pulse signal NPLS has been increased by a predetermined amount of time. For example, when the pulse signal NPLS has the logic low level, the delayed inverted pulse signal NPLSb_D may represent the inverted signal of the pulse signal NPLS, and the delayed inverted pulse signal NPLSb_D may be a pulse signal having a form in which a period of time having the logic high level is increased by a predetermined amount of time.

219 219 b b 19 FIG. The voltage control circuitmay receive the power gating enable signal PGEN and the delayed inverted pulse signal NPLSb_D as input signals and may output the voltage control signal PCTRL_VOL. The voltage control signal PCTRL_VOL of the voltage control circuitis described in detail with reference to.

210 210 216 210 a b a b 5 FIG. 15 FIG. Compared to the boosting control circuitof, the boosting control circuitofmay not include the short protection circuit. Instead, the boosting control circuitmay include two voltage boosting paths for raising the voltage of the node NPG and one voltage dropping path for lowering the voltage of the node NPG, thereby preventing a short-circuit between voltage lines.

16 FIG. 15 FIG. 17 FIG.A 16 FIG. 17 FIG.B 18 18 FIGS.A andB 16 FIG. 19 FIG. 16 FIG. 210 214 219 210 b b b b is a diagram showing an equivalent circuit according to an example of the boosting control circuitof.shows an equivalent circuit according to an example of the delay circuitof, andis a timing chart of the equivalent circuit.are diagrams illustrating the voltage control circuitof.is a timing chart of the boosting control circuitof.

211 211 b a 15 16 FIGS.and 7 FIG. The pulse generating circuitofmay correspond to the pulse generating circuitof, and repeated descriptions thereof are omitted.

210 214 219 b b b 16 FIG. 17 17 FIGS.A andB 18 18 FIGS.A andB Prior to describing the boosting control circuitof, the delay circuitand the voltage control circuitare described first with reference toand.

17 FIG.A 8 FIG. 8 FIG. 214 214 1 214 2 214 1 214 2 214 1 214 2 214 214 214 3 b b b b b a a a b a Referring to, the delay circuitmay include a sub delay circuit-and a NAND logic circuit-. The sub delay circuit-and the NAND logic circuit-may correspond to the sub delay circuit-and the NAND logic circuit-of, respectively, and repeated descriptions thereof are omitted. Compared to the delay circuitof, the delay circuitmay not include the inverter circuit-.

17 FIG.B 214 b Referring to, the delay circuitmay receive the pulse signal NPLS as an input signal and output the delayed inverted pulse signal NPLSb_D. Here, the delayed inverted pulse signal NPLSb_D may represent an inverted signal of a pulse signal having a form in which a period of time having a specific logic level of the pulse signal NPLS has been increased by the predetermined delay time DP. When the pulse signal NPLS has a logic low level, the delayed inverted pulse signal NPLSb_D may represent the inverted signal of the pulse signal having a form in which a period of time having the logic low level of the pulse signal NPLS has been increased by the predetermined delay time DP.

18 FIG.A 219 b Referring to, the voltage control circuitmay receive the power gating enable signal PGEN and the delayed inverted pulse signal NPLSb_D as input signals and may output the voltage control signal PCTRL_VOL.

18 FIG.B 219 b Referring to, when the logic level of the power gating enable signal PGEN is logic low, the voltage control circuitmay output the voltage control signal PCTRL_VOL having the logic high level, irrespective of the logic level of the delayed inverted pulse signal NPLSb_D.

18 FIG.B 219 219 219 b b b Referring to, when the logic level of the power gating enable signal PGEN is logic high, the voltage control circuitmay output the voltage control signal PCTRL_VOL, based on the logic level of the delayed inverted pulse signal NPLSb_D. When the logic level of the power gating enable signal PGEN is logic high and the logic level of the delayed inverted pulse signal NPLSb_D is logic high, the voltage control circuitmay output the voltage control signal PCTRL_VOL having the logic high level. When the logic level of the power gating enable signal PGEN is logic high and the logic level of the delayed inverted pulse signal NPLSb_D is logic low, the voltage control circuitmay output the voltage control signal PCTRL_VOL having the logic low level.

16 FIG. 16 FIG. 16 19 FIGS.and 210 b Returning to, the boosting control circuitofis described with reference to.

16 FIG. 212 215 217 212 215 217 b b b b b b Referring to, each of the first inverter chain circuitand the second inverter chain circuitmay include two inverter circuits. The third inverter chain circuitmay include three inverter circuits. However, the embodiment is not limited thereto, and the number of inverter circuits in the first to third inverter chain circuits,, andmay vary according to embodiments. The number of inverter circuits may be determined by considering a response speed or power consumption, etc., according to characteristics of current in total circuits. Also, the inverter circuit may be formed as the CMOS transistor and configured such that the NMOS transistor and the PMOS transistor in the inverter circuit operate in a complementary manner.

16 FIG. 212 212 1 212 2 212 1 212 2 212 1 212 2 1 b b b b b b b b Referring to, the first inverter chain circuitmay include an inverter circuit-and an inverter circuit-. The inverter circuit-and the inverter circuit-may be connected to each other in series. The inverter circuit-may receive the pulse signal NPLS as an input signal, and the inverter circuit-may output the positive power gating voltage VPGP or the ground voltage VGND as the first power gating signal PGaccording to the logic level of the pulse signal NPLS.

16 FIG. 212 2 5 5 5 5 1 5 5 212 1 5 5 1 5 5 212 1 b b b Referring to, the inverter circuit-may include a PMOS transistor IPTand an NMOS transistor INT. A source terminal of the PMOS transistor IPTmay be connected to the line of the positive power gating voltage VPGP, a drain terminal of the PMOS transistor IPTmay be connected to a gate terminal of a PMOS transistor BPTand a drain terminal of the NMOS transistor INT, and a gate terminal of the PMOS transistor IPTmay be connected to an output terminal of the inverter circuit-. A source terminal of the NMOS transistor INTmay be connected to the line of the ground voltage VGND, the drain terminal of the NMOS transistor INTmay be connected to the gate terminal of the PMOS transistor BPTand the drain terminal of the PMOS transistor IPT, and a gate terminal of the NMOS transistor INTmay be connected to the output terminal of the inverter circuit-.

16 FIG. 215 215 1 215 2 215 1 215 2 215 1 215 2 2 b b b b b b b b Referring to, the second inverter chain circuitmay include an inverter circuit-and an inverter circuit-. The inverter circuit-and the inverter circuit-may be connected to each other in series. The inverter circuit-may receive the voltage control signal PCTRL_VOL as an input signal, and the inverter circuit-may output the positive power gating voltage VPGP or the ground voltage VGND as the second power gating signal PGaccording to the logic level of the voltage control signal PCTRL_VOL.

16 FIG. 215 2 6 6 6 6 2 6 6 215 1 6 6 2 6 6 215 1 b b b Referring to, the inverter circuit-may include a PMOS transistor IPTand an NMOS transistor INT. A source terminal of the PMOS transistor IPTmay be connected to the line of the positive power gating voltage VPGP, a drain terminal of the PMOS transistor IPTmay be connected to a gate terminal of a PMOS transistor BPTand a drain terminal of the NMOS transistor INT, and a gate terminal of the PMOS transistor IPTmay be connected to an output terminal of the inverter circuit-. A source terminal of the NMOS transistor INTmay be connected to the line of the ground voltage VGND, the drain terminal of the NMOS transistor INTmay be connected to the gate terminal of the PMOS transistor BPTand the drain terminal of the PMOS transistor IPT, and a gate terminal of the NMOS transistor INTmay be connected to the output terminal of the inverter circuit-.

16 FIG. 217 217 1 217 2 217 3 217 1 217 2 217 3 217 1 217 3 2 3 b b b b b b b b b b Referring to, the third inverter chain circuitmay include an inverter circuit-, an inverter circuit-, and an inverter circuit-. The inverter circuit-, the inverter circuit-, and the inverter circuit-may be connected to each other in series. The inverter circuit-may receive the power gating enable signal PGEN as an input signal, and the inverter circuit-may output the second power supply voltage VDDor the ground voltage VGND as the third power gating signal PGaccording to the logic level of the power gating enable signal PGEN.

16 FIG. 217 3 7 7 7 2 7 1 7 7 217 2 7 7 1 7 7 217 2 b b b Referring to, the inverter circuit-may include a PMOS transistor IPTand an NMOS transistor INT. A source terminal of the PMOS transistor IPTmay be connected to the line of the second power supply voltage VDD, a drain terminal of the PMOS transistor IPTmay be connected to a gate terminal of an NMOS transistor DNTand a drain terminal of the NMOS transistor INT, and a gate terminal of the PMOS transistor IPTmay be connected to an output terminal of the inverter circuit-. A source terminal of the NMOS transistor INTmay be connected to the line of the ground voltage VGND, the drain terminal of the NMOS transistor INTmay be connected to the gate terminal of the NMOS transistor DNTand the drain terminal of the PMOS transistor IPT, and a gate terminal of the NMOS transistor INTmay be connected to the output terminal of the inverter circuit-.

16 FIG. 213 1 1 2 1 1 1 1 2 1 1 2 b b b b Referring to, the first boosting switchmay include the PMOS transistor BPT. The PMOS transistor BPTmay be connected between the line of the second power supply voltage VDDand the node NPG. The PMOS transistor BPTmay be turned on or off in response to the first power gating signal PG. For example, the PMOS transistor BPTmay be turned on in response to the first power gating signal PGhaving the level of the ground voltage VGND, and accordingly, the line of the second power supply voltage VDDmay be connected to the node NPG. Also, the PMOS transistor BPTmay be turned off in response to the first power gating signal PGhaving the level of the positive power gating voltage VPGP, and accordingly, the line of the second power supply voltage VDDmay be disconnected from the node NPG.

16 FIG. 216 2 2 2 2 2 2 2 2 b b b b Referring to, the second boosting switchmay include the PMOS transistor BPT. The PMOS transistor BPTmay be connected between the line of the positive power gating voltage VPGP and the node NPG. The PMOS transistor BPTmay be turned on or off in response to the second power gating signal PG. For example, the PMOS transistor BPTmay be turned on in response to the second power gating signal PGhaving the level of the ground voltage VGND, and accordingly, the line of the positive power gating voltage VPGP may be connected to the node NPG. Also, the PMOS transistor BPTmay be turned off in response to the second power gating signal PGhaving the level of the positive power gating voltage VPGP, and accordingly, the line of the positive power gating voltage VPGP may be disconnected from the node NPG.

16 FIG. 218 1 1 1 3 1 3 2 1 3 b b b b Referring to, the dropping switchmay include the NMOS transistor DNT. The NMOS transistor DNTmay be connected between the line of the ground voltage VGND and the node NPG. The NMOS transistor DNTmay be turned on or off in response to the third power gating signal PG. For example, the NMOS transistor DNTmay be turned on in response to the third power gating signal PGhaving the level of the second power source voltage VDD, and accordingly, the line of the ground voltage VGND may be connected to the node NPG. Also, the NMOS transistor DNTmay be turned off in response to the third power gating signal PGhaving the level of the ground voltage VGND, and accordingly, the line of the ground voltage VGND may be disconnected from the node NPG.

19 FIG. 16 19 FIGS.and 1 121 1 3 121 3 121 210 1 3 c c c c b c c Referring to, the diagram shows a timing chart of the active mode ACT and the standby mode STBY. Referring to, prior to a point in time t, the control logic circuitmay output the power gating enable signal PGEN having the logic low level in response to the command CMD indicating the active mode ACT. From the point in time tto a point in time t, the control logic circuitmay output the power gating enable signal PGEN having the logic high level in response to the command CMD indicating the standby mode STBY. After the point in time t, the control logic circuitmay output the power gating enable signal PGEN having the logic low level in response to the command CMD indicating the active mode ACT. Hereafter, the operation of the boosting control circuitfrom the point in time tto the point in time tis described.

1 211 211 c b b From the point in time t, the pulse generating circuitmay output the pulse signal NPLS having the logic low level during the pulse time t_NPLS in response to the power gating enable signal PGEN having the logic high level. After the pulse time t_NPLS, the pulse generating circuitmay output the pulse signal NPLS having the logic high level.

1 212 2 212 1 212 2 212 1 c b b b b b b Also, from the point in time t, the inverter circuit-of the first inverter chain circuitmay output the first power gating signal PGhaving the level of the ground voltage VGND during the pulse time t_NPLS in response to the pulse signal NPLS having the logic low level. After the pulse time t_NPLS, the inverter circuit-of the first inverter chain circuitmay output the first power gating signal PGhaving the level of the positive power gating voltage VPGP in response to the pulse signal NPLS having the logic high level.

1 214 2 214 c b c b Also, from the point in time t, the delay circuitmay output the delayed inverted pulse signal NPLSb_D having the logic high level during the pulse time t_NPLS and the delay time DP in response to the pulse signal NPLS having the logic low level. From a point in time tafter the pulse time t_NPLS and the delay time DP, the delay circuitmay output the delayed inverted pulse signal NPLSb_D having the logic low level.

1 2 219 2 219 c c b c b 18 FIG. 18 FIG. Also, from the point in time tto the point in time t, the logic level of the power gating enable signal PGEN is logic high, and the logic level of the delayed inverted pulse signal NPLSb_D is logic high, as described with reference to. Therefore, the voltage control circuitmay output the voltage control signal PCTRL_VOL having the logic high level. Also, after the point in time t, the logic level of the power gating enable signal PGEN is logic high, and the logic level of the delayed inverted pulse signal NPLSb_D is logic low, as described with reference to. Therefore, the voltage control circuitmay output the voltage control signal PCTRL_VOL having the logic low level.

1 2 215 2 215 2 2 215 2 215 2 c c b b b c b b b Also, from the point in time tto the point in time t, the inverter circuit-of the second inverter chain circuitmay output the second power gating signal PGhaving the level of the positive power gating voltage VPGP in response to the voltage control signal PCTRL_VOL having the logic high level. Also, after the point in time t, the inverter circuit-of the second inverter chain circuitmay output the second power gating signal PGhaving the level of the ground voltage VGND in response to the voltage control signal PCTRL_VOL having the logic low level.

1 217 3 217 3 c b b b Also, from the point in time t, the inverter circuit-of the third inverter chain circuitmay output the third power gating signal PGhaving the level of the ground voltage VGND in response to the power gating enable signal PGEN having the logic high level.

1 1 1 2 2 c b In addition, during the pulse time t_NPLS from the point in time t, the PMOS transistor BPTis turned on in response to the first power gating signal PGhaving the level of the ground voltage VGND. Accordingly, the second power supply voltage VDDmay be provided to the node NPG from the line of the second power supply voltage VDD.

1 1 2 2 2 2 b After the pulse time t_NPLS, the PMOS transistor BPTis turned off in response to the first power gating signal PGhaving the level of the positive power gating voltage VPGP. Accordingly, the second power supply voltage VDDmay not be supplied to the node NPG from the line of the second power supply voltage VDD. Here, during the delay time DP after the pulse time t_NPLS, the node NPG may be disconnected from all of the line of the second power supply voltage VDD, the line of the positive power gating voltage VPGP, and the line of the ground voltage VGND, and accordingly, a short-circuit between the line of the second power supply voltage VDD, the line of the positive power gating voltage VPGP, and the line of the ground voltage VGND may be prevented.

2 2 2 c b From the point in time tafter the pulse time t_NPLS and the delay time DP, the PMOS transistor BPTis turned on in response to the second power gating signal PGhaving the level of the ground voltage VGND. Accordingly, the positive power gating voltage VPGP may be provided to the node NPG from the line of the positive power gating voltage VPGP.

218 3 2 b b When the command CMD indicates the active mode ACT, the dropping switchis turned on in response to the third power gating signal PGhaving the level of the second power supply voltage VDD. Accordingly, the line of the ground voltage VGND may be connected to the node NPG.

2 200 As described above, according to the inventive concept, the voltage level of the node NPG is not raised to the positive power gating voltage VPGP at once, but is raised to the second power supply voltage VDDin an intermediate stage and then raised to the positive power gating voltage VPGP. This may reduce the power consumed by the power gating operation of the first power gating circuit.

20 FIG. 310 b is a block diagram showing another example of a dropping control circuitaccording to the inventive concept.

20 FIG. 310 311 312 313 314 315 316 317 318 319 b b b b b b b b b b. Referring to, the dropping control circuitmay include a pulse generating circuit, a fourth inverter chain circuit, a first dropping switch, a delay circuit, a fifth inverter chain circuit, a second dropping switch, a sixth inverter chain circuit, a boosting switch, and a voltage control circuit

311 311 b b The pulse generating circuitmay output a pulse signal PPLS in response to the power gating enable signal PGEN. For example, when the power gating enable signal PGEN transitions from the logic low level to the logic high level, the pulse generating circuitmay output the pulse signal PPLS having the logic high level.

312 315 317 b b b Each of the fourth inverter chain circuit, the fifth inverter chain circuit, and the sixth inverter chain circuitmay include a plurality of inverter circuits connected to each other in series.

312 315 2 312 315 312 315 2 317 2 317 317 2 b b b b b b b b b Here, a positive power supply terminal of each of inverter circuits of the fourth inverter chain circuitand the fifth inverter chain circuitmay be connected to the line of the second power supply voltage VDD, and a negative power supply terminal of each of the inverter circuits of the fourth inverter chain circuitand the fifth inverter chain circuitmay be connected to the line of the negative power gating voltage VPGN. The fourth inverter chain circuitand the fifth inverter chain circuitmay output the second power supply voltage VDDor the negative power gating voltage VPGN according to a logic level of an input signal. A positive power supply terminal of each of inverter circuits of the sixth inverter chain circuitmay be connected to the line of the second power supply voltage VDD, and a negative power supply terminal of each of the inverter circuits of the sixth inverter chain circuitmay be connected to the line of the ground voltage VGND. The sixth inverter chain circuitmay output the second power supply voltage VDDor the ground voltage VGND according to a logic level of an input signal.

20 FIG. 317 b In some embodiments, unlike that shown in, the negative power supply terminal of each of the inverter circuits of the sixth inverter chain circuitmay be connected to the line of the negative power gating voltage VPGN.

312 2 1 b b The fourth inverter chain circuitmay receive the pulse signal PPLS as an input signal and output the second power supply voltage VDDor the negative power gating voltage VPGN as a first power gating signal NGaccording to the logic level of the pulse signal PPLS.

315 2 2 b b The fifth inverter chain circuitmay receive a voltage control signal NCTRL_VOL as an input signal and output the second power supply voltage VDDor the negative power gating voltage VPGN as a second power gating signal NGaccording to the logic level of the voltage control signal NCTRL_VOL.

317 2 3 b b The sixth inverter chain circuitmay receive the power gating enable signal PGEN as an input signal and output the second power supply voltage VDDor the ground voltage VGND as a third power gating signal NGaccording to the logic level of the power gating enable signal PGEN.

313 313 1 313 1 2 313 1 b b b b b b b The first dropping switchmay be connected between the line of the ground voltage VGND and the node NNG. The first dropping switchmay be turned on or off in response to the first power gating signal NG. For example, the first dropping switchmay be turned on in response to the first power gating signal NGhaving the second power supply voltage VDD, and accordingly, the line of the ground voltage VGND may be connected to the node NNG. Also, the first dropping switchmay be turned off in response to the first power gating signal NGhaving the level of the negative power gating voltage VPGN, and accordingly, the line of the ground voltage VGND may be disconnected from the node NNG.

316 316 2 316 2 2 316 2 b b b b b b b The second dropping switchmay be connected between the line of the negative power gating voltage VPGN and the node NNG. The second dropping switchmay be turned on or off in response to the second power gating signal NG. For example, the second dropping switchmay be turned on in response to the second power gating signal NGhaving the second power supply voltage VDD, and accordingly, the line of the negative power gating voltage VPGN may be connected to the node NNG. Also, the second dropping switchmay be turned off in response to the second power gating signal NGhaving the level of the negative power gating voltage VPGN, and accordingly, the line of the negative power gating voltage VPGN may be disconnected from the node NNG.

318 2 318 3 318 3 2 318 3 2 2 b b b b b b b The boosting switchmay be connected between the line of the second power supply voltage VDDand the node NNG. The boosting switchmay be turned on or off in response to the third power gating signal NG. For example, the boosting switchmay be turned on in response to the third power gating signal NGhaving the level of the ground voltage VGND, and accordingly, the line of the second power supply voltage VDDmay be connected to the node NNG. Also, the boosting switchmay be turned off in response to the third power gating signal NGhaving the level of the second power supply voltage VDD, and accordingly, the line of the second power supply voltage VDDmay be disconnected from the node NNG.

314 b The delay circuitmay receive the pulse signal PPLS as an input signal and output a delayed pulse signal PPLS_D. Here, the delayed pulse signal PPLS_D may represent a pulse signal having a form in which a period of time having a specific logic level of the pulse signal PPLS has been increased by a predetermined amount of time. For example, when the pulse signal PPLS has a logic high level, the delayed pulse signal PPLS_D may represent a pulse signal having a form in which a period of time having the logic high level of the pulse signal PPLS has been increased by a predetermined amount of time.

319 319 b b 22 FIG. The voltage control circuitmay receive the power gating enable signal PGEN and the delayed pulse signal PPLS_D as input signals and may output the voltage control signal NCTRL_VOL. The voltage control signal NCTRL_VOL of the voltage control circuitis described in detail with reference to.

310 310 316 310 a b a b 10 FIG. 20 FIG. Compared to the dropping control circuitof, the dropping control circuitofmay not include the short protection circuit. Instead, the dropping control circuitmay include two voltage dropping paths for lowering the voltage of the node NNG and one voltage boosting path for raising the voltage of the node NNG, thereby preventing a short-circuit between voltage lines.

21 FIG. 20 FIG. 22 22 FIGS.A andB 20 FIG. 23 FIG. 21 FIG. 310 319 310 b b b is a diagram showing an equivalent circuit according to an example of the dropping control circuitof.are diagrams illustrating the voltage control circuitof.is a timing chart of the dropping control circuitof.

311 311 314 314 b a b a 20 21 FIGS.and 12 FIG. 20 21 FIGS.and 13 FIG. The pulse generating circuitofmay correspond to the pulse generating circuitof, the delay circuitofmay correspond to the delay circuitof, and repeated descriptions thereof are omitted.

310 319 b b 21 FIG. 22 22 FIGS.A andB Prior to describing the dropping control circuitof, the voltage control circuitis described first with reference to.

22 FIG.A 319 b Referring to, the voltage control circuitmay receive the power gating enable signal PGEN and the delayed pulse signal PPLS_D as input signals and may output the voltage control signal NCTRL_VOL.

22 FIG.B 319 b Referring to, when the logic level of the power gating enable signal PGEN is logic low, the voltage control circuitmay output the voltage control signal NCTRL_VOL having the logic low level, irrespective of the logic level of the delayed pulse signal PPLS_D.

22 FIG.B 319 319 319 b b b Referring to, when the logic level of the power gating enable signal PGEN is logic high, the voltage control circuitmay output the voltage control signal NCTRL_VOL, based on the logic level of the delayed pulse signal PPLS_D. When the logic level of the power gating enable signal PGEN is logic high and the logic level of the delayed pulse signal PPLS_D is logic high, the voltage control circuitmay output the voltage control signal NCTRL_VOL having the logic low level. When the logic level of the power gating enable signal PGEN is logic high and the logic level of the delayed pulse signal PPLS_D is logic low, the voltage control circuitmay output the voltage control signal NCTRL_VOL having the logic high level.

21 FIG. 21 FIG. 21 23 FIGS.and 310 b Returning to, the dropping control circuitofis described with reference to.

21 FIG. 312 315 317 312 315 317 b b b b b b Referring to, each of the fourth inverter chain circuit, the fifth inverter chain circuit, and the sixth inverter chain circuitmay include two inverter circuits. However, the embodiment is not limited thereto, and the number of inverter circuits in the fourth to sixth inverter chain circuits,, andmay vary according to embodiments. The number of inverter circuits may be determined by considering a response speed or power consumption, etc., according to characteristics of current in total circuits. Also, the inverter circuit may be formed as the CMOS transistor and configured such that the NMOS transistor and the PMOS transistor in the inverter circuit operate in a complementary manner.

21 FIG. 312 312 1 312 2 312 1 312 2 312 1 312 2 2 1 b b b b b b b b Referring to, the fourth inverter chain circuitmay include an inverter circuit-and an inverter circuit-. The inverter circuit-and the inverter circuit-may be connected to each other in series. The inverter circuit-may receive the pulse signal PPLS as an input signal, and the inverter circuit-may output the second power supply voltage VDDor the negative power gating voltage VPGN as the first power gating signal NGaccording to the logic level of the pulse signal PPLS.

21 FIG. 312 2 8 8 8 2 8 2 8 8 312 1 8 8 2 8 8 312 1 b b b Referring to, the inverter circuit-may include a PMOS transistor IPTand an NMOS transistor INT. A source terminal of the PMOS transistor IPTmay be connected to the line of the second power supply voltage VDD, a drain terminal of the PMOS transistor IPTmay be connected to a gate terminal of an NMOS transistor DNTand a drain terminal of the NMOS transistor INT, and a gate terminal of the PMOS transistor IPTmay be connected to an output terminal of the inverter circuit-. A source terminal of the NMOS transistor INTmay be connected to the line of the negative power gating voltage VPGN, the drain terminal of the NMOS transistor INTmay be connected to the gate terminal of the NMOS transistor DNTand the drain terminal of the PMOS transistor IPT, and a gate terminal of the NMOS transistor INTmay be connected to the output terminal of the inverter circuit-.

21 FIG. 315 315 1 315 2 315 1 315 2 315 1 315 2 2 2 b b b b b b b b Referring to, the fifth inverter chain circuitmay include an inverter circuit-and an inverter circuit-. The inverter circuit-and the inverter circuit-may be connected to each other in series. The inverter circuit-may receive the voltage control signal NCTRL_VOL as an input signal, and the inverter circuit-may output the second power supply voltage VDDor the negative power gating voltage VPGN as the second power gating signal NGaccording to the logic level of the voltage control signal NCTRL_VOL.

21 FIG. 315 2 9 9 9 2 9 3 9 9 315 1 9 9 3 9 9 315 1 b b b Referring to, the inverter circuit-may include a PMOS transistor IPTand an NMOS transistor INT. A source terminal of the PMOS transistor IPTmay be connected to the line of the second power supply voltage VDD, a drain terminal of the PMOS transistor IPTmay be connected to a gate terminal of an NMOS transistor DNTand a drain terminal of the NMOS transistor INT, and a gate terminal of the PMOS transistor IPTmay be connected to an output terminal of the inverter circuit-. A source terminal of the NMOS transistor INTmay be connected to the line of the negative power gating voltage VPGN, the drain terminal of the NMOS transistor INTmay be connected to the gate terminal of the NMOS transistor DNTand the drain terminal of the PMOS transistor IPT, and a gate terminal of the NMOS transistor INTmay be connected to the output terminal of the inverter circuit-.

21 FIG. 317 317 1 317 2 317 1 317 2 317 1 317 2 2 3 b b b b b b b b Referring to, the sixth inverter chain circuitmay include an inverter circuit-and an inverter circuit-. The inverter circuit-and the inverter circuit-may be connected to each other in series. The inverter circuit-may receive the power gating enable signal PGEN as an input signal, and the inverter circuit-may output the second power supply voltage VDDor the ground voltage VGND as the third power gating signal NGaccording to the logic level of the power gating enable signal PGEN.

21 FIG. 317 2 10 10 10 2 10 3 10 10 317 1 10 10 3 10 10 317 1 b b b Referring to, the inverter circuit-may include a PMOS transistor IPTand an NMOS transistor INT. A source terminal of the PMOS transistor IPTmay be connected to the line of the second power supply voltage VDD, a drain terminal of the PMOS transistor IPTmay be connected to a gate terminal of a PMOS transistor BPTand a drain terminal of the NMOS transistor INT, and a gate terminal of the PMOS transistor IPTmay be connected to an output terminal of the inverter circuit-. A source terminal of the NMOS transistor INTmay be connected to the line of the ground voltage VGND, the drain terminal of the NMOS transistor INTmay be connected to the gate terminal of the PMOS transistor BPTand the drain terminal of the PMOS transistor IPT, and a gate terminal of the NMOS transistor INTmay be connected to the output terminal of the inverter circuit-.

21 FIG. 313 2 2 2 1 2 1 2 2 1 b b b b Referring to, the first dropping switchmay include the NMOS transistor DNT. The NMOS transistor DNTmay be connected between the line of the ground voltage VGND and the node NNG. The NMOS transistor DNTmay be turned on or off in response to the first power gating signal NG. For example, the NMOS transistor DNTmay be turned on in response to the first power gating signal NGhaving the level of the second power supply voltage VDD, and accordingly, the line of the ground voltage VGND may be connected to the node NNG. Also, the NMOS transistor DNTmay be turned off in response to the first power gating signal NGhaving the level of the negative power gating voltage VPGN, and accordingly, the line of the ground voltage VGND may be disconnected from the node NNG.

21 FIG. 316 3 3 3 2 3 2 2 3 2 b b b b Referring to, the second dropping switchmay include the NMOS transistor DNT. The NMOS transistor DNTmay be connected between the line of the negative power gating voltage VPGN and the node NNG. The NMOS transistor DNTmay be turned on or off in response to the second power gating signal NG. For example, the NMOS transistor DNTmay be turned on in response to the second power gating signal NGhaving the level of the second power supply voltage VDD, and accordingly, the line of the negative power gating voltage VPGN may be connected to the node NNG. Also, the NMOS transistor DNTmay be turned off in response to the second power gating signal NGhaving the level of the negative power gating voltage VPGN, and accordingly, the line of the negative power gating voltage VPGN may be disconnected from the node NNG.

21 FIG. 318 3 3 2 3 3 3 3 2 3 3 2 2 b b b b Referring to, the boosting switchmay include the PMOS transistor BPT. The PMOS transistor BPTmay be connected between the line of the second power supply voltage VDDand the node NNG. The PMOS transistor BPTmay be turned on or off in response to the third power gating signal NG. For example, the PMOS transistor BPTmay be turned on in response to the third power gating signal NGhaving the level of the ground voltage VGND, and accordingly, the line of the second power supply voltage VDDmay be connected to the node NNG. Also, the PMOS transistor BPTmay be turned off in response to the third power gating signal NGhaving the level of the second power supply voltage VDD, and accordingly, the line of the second power supply voltage VDDmay be disconnected from the node NNG.

23 FIG. 21 23 FIGS.and 1 121 1 3 121 3 121 310 1 3 d d d d b d d Referring to, the diagram shows a timing chart of the active mode ACT and the standby mode STBY. Referring to, prior to a point in time t, the control logic circuitmay output the power gating enable signal PGEN having the logic low level in response to the command CMD indicating the active mode ACT. From the point in time tto a point in time t, the control logic circuitmay output the power gating enable signal PGEN having the logic high level in response to the command CMD indicating the standby mode STBY. After the point in time t, the control logic circuitmay output the power gating enable signal PGEN having the logic low level in response to the command CMD indicating the active mode ACT. Hereafter, the operation of the dropping control circuitfrom the point in time tto the point in time tis described.

1 311 311 d b b From the point in time t, the pulse generating circuitmay output the pulse signal PPLS having the logic high level during the pulse time t_PPLS in response to the power gating enable signal PGEN having the logic high level. After the pulse time t_PPLS, the pulse generating circuitmay output the pulse signal PPLS having the logic low level.

1 312 2 312 1 2 312 2 312 1 d b b b b b b Also, from the point in time t, the inverter circuit-of the fourth inverter chain circuitmay output the first power gating signal NGhaving the level of the second power supply voltage VDDduring the pulse time t_PPLS in response to the pulse signal PPLS having the logic high level. After the pulse time t_PPLS, the inverter circuit-of the fourth inverter chain circuitmay output the first power gating signal NGhaving the level of the negative power gating voltage VPGN in response to the pulse signal PPLS having the logic low level.

1 314 2 314 d b d b Also, from the point in time t, the delay circuitmay output the delayed pulse signal PPLS_D having the logic high level during the pulse time t_PPLS and the delay time DN in response to the pulse signal PPLS having the logic high level. From a point in time tafter the pulse time t_PPLS and the delay time DN, the delay circuitmay output the delayed pulse signal PPLS_D having the logic low level.

1 2 319 2 319 d d b d b 22 FIG. 22 FIG. Also, from the point in time tto the point in time t, the logic level of the power gating enable signal PGEN is logic high, and the logic level of the delayed pulse signal PPLS_D is logic high, as described with reference to. Therefore, the voltage control circuitmay output the voltage control signal NCTRL_VOL having the logic low level. Also, after the point in time t, the logic level of the power gating enable signal PGEN is logic high, and the logic level of the delayed pulse signal PPLS_D is logic low, as described with reference to. Therefore, the voltage control circuitmay output the voltage control signal NCTRL_VOL having the logic high level.

1 2 315 2 315 2 2 315 2 315 2 2 d d b b b d b b b Also, from the point in time tto the point in time t, the inverter circuit-of the fifth inverter chain circuitmay output the second power gating signal NGhaving the level of the negative power gating voltage VPGN in response to the voltage control signal NCTRL_VOL having the logic low level. Also, after the point in time t, the inverter circuit-of the fifth inverter chain circuitmay output the second power gating signal NGhaving the level of the second power supply voltage VDDin response to the voltage control signal NCTRL_VOL having the logic high level.

1 317 2 317 3 2 d b b b Also, from the point in time t, the inverter circuit-of the sixth inverter chain circuitmay output the third power gating signal NGhaving the level of the second power supply voltage VDDin response to the power gating enable signal PGEN having the logic high level.

1 3 1 2 d b In addition, during the pulse time t_PPLS from the point in time t, the NMOS transistor DNTis turned on in response to the first power gating signal NGhaving the level of the second power supply voltage VDD. Accordingly, the ground voltage VGND may be provided to the node NNG from the line of the ground voltage VGND.

3 1 2 2 b After the pulse time t_PPLS, the NMOS transistor DNTis turned off in response to the first power gating signal NGhaving the level of the negative power gating voltage VPGN. Accordingly, the ground voltage VGND may not be supplied to the node NNG from the line of the ground voltage VGND. Here, during the delay time DN after the pulse time t_PPLS, the node NNG may be disconnected from all of the line of the second power supply voltage VDD, the line of the negative power gating voltage VPGN, and the line of the ground voltage VGND, and accordingly, a short-circuit between the line of the second power supply voltage VDD, the line of the negative power gating voltage VPGN, and the line of the ground voltage VGND may be prevented.

2 3 2 2 d b From the point in time tafter the pulse time t_PPLS and the delay time DN, the NMOS transistor DNTis turned on in response to the second power gating signal NGhaving the level of the second power supply voltage VDD. Accordingly, the negative power gating voltage VPGN may be provided to the node NNG from the line of the negative power gating voltage VPGN.

300 As described above, according to the inventive concept, the voltage level of the node NNG is not lowered to the negative power gating voltage VPGN at once, but is lowered to the ground voltage VGND in an intermediate stage and then lowered to the negative power gating voltage VPGN. This may reduce the power consumed by the power gating operation of the second power gating circuit.

24 FIG. 2000 is a block diagram of a systemand illustrates an electronic product including a memory device according to embodiments.

24 FIG. 2000 2100 2200 2300 2400 2500 2500 2600 2600 2700 2700 2800 2000 2000 a b a b a b As shown in, the systemmay include a camera, a display, an audio processor, a modem, DRAMand, flash memoryand, input/output (I/O) devicesand, and an application processor(hereinafter referred to as “AP”). The systemmay be provided as a laptop computer, a mobile phone, a smart phone, a tablet personal computer (PC), a wearable device, a healthcare device, or an IoT device. In addition, the systemmay be provided as a server or a PC.

2100 2200 2300 2600 2600 2400 2700 2700 a b a b The cameramay capture still images or moving images under control by a user, and store the captured image/video data or transmit the data to the display. The audio processormay process audio data in contents of the flash memoryandor a network. The modemmodulates and transmits signals to transmit and receive wired/wireless data, and the modulated and transmitted signals may be demodulated and restored to original signals at a reception side. The I/O devicesandmay include devices that provide digital input and/or output functions, such as a universal serial bus (USB) or storage, a digital camera, a secure digital (SD) card, a digital versatile disc (DVD), a network adapter, and a touch screen.

2800 2000 2800 2810 2820 2830 2800 2200 2600 2600 2200 2700 2700 2800 2800 2820 2800 2820 2500 2800 a b a b b The APmay control all operations of the system. The APmay include a control block, an accelerator block or an accelerator chip, and an interface block. The APmay control the displayso that some contents stored in the flash memoryandare displayed on the display. When a user input is received via the I/O devicesand, the APmay perform a control operation in response to the user input. The APmay include the accelerator block, which is dedicated circuit for computing artificial intelligence (AI) data, or may have the accelerator chipseparate from the AP. The accelerator block or the accelerator chipmay be further equipped with the DRAM. An accelerator represents a function block specialized in performing a particular function of the AP, and the accelerator may include a graphics processing unit (GPU) that is a function block specialized in processing graphic data, a neural processing unit (NPU) that is a block specialized in performing AI computation and inference, and a data processing unit (DPU) that is a block specialized in data transmission.

2000 2500 2500 2800 2500 2500 2800 2500 2820 2500 2500 a b a b a b a. The systemmay include the plurality of DRAMand. The APmay control the DRAMandby setting a mode register (MRS) and commands conforming to Joint Electron Device Engineering Council (JEDEC) standards, or may perform communication by establishing DRAM interface protocols to utilize vendor-specific functions, such as low voltage/high speed/reliability, and cyclic redundancy check (CRC)/error correction code (ECC) functions. For example, the APmay communicate with the DRAMover an interface conforming to JEDEC standards, such as low power double data rate 4th generation (LPDDR4) and low power double data rate 5th generation (LPDDR5), and the accelerator block or the accelerator chipmay perform communication by establishing a new DRAM interface protocol to control the DRAMfor an accelerator that has a higher bandwidth than the DRAM

2500 2500 2800 2820 2500 2500 2700 2700 2600 2600 2500 2500 2000 2500 2500 a b a b a b a b a b a b 24 FIG. Only the DRAMandare shown in, but the embodiment is not limited thereto. Any memory may be used, such as PRAM, SRAM, MRAM, ReRAM, FeRAM, and hybrid RAM memory, as long as such memory satisfies the bandwidth, response speed, and voltage requirements of the APor the accelerator chip. The DRAMandhave relatively less latency and bandwidth than the I/O devicesandor the flash memoryand. The DRAMandare initialized at a point in time when the systemis powered on, and an operating system and application data are loaded thereon. The DRAMandmay be used as temporary storage spaces for the operating system and application data or as execution spaces for various pieces of software code.

2500 2500 2500 2500 2100 2500 2820 2500 a b a b b b Arithmetic operations, such as addition, subtraction, multiplication, and division, vector operations, address operations, or fast Fourier transform (FFT) operations may be performed in the DRAMand. In addition, a function for execution used for inference may be performed inside the DRAMand. Here, the inference may be performed in a deep learning algorithm using an artificial neural network. The deep learning algorithm may include a training stage of training a model by using various pieces of data and an inference stage of identifying data by using the trained model. In an embodiment, the images captured by the user via the cameraare signal-processed and stored in the DRAM, and the accelerator block or the accelerator chipmay perform AI data calculation in which data is identified by using the data stored in the DRAMand the functions used in the inference.

2000 2600 2600 2500 2500 2820 2600 2600 2600 2600 2610 2620 2610 2800 2820 2600 2600 2100 a b a b a b a b a b The systemmay include a plurality of storage devices or the plurality of flash memoryandhaving larger capacities than the DRAMand. The accelerator block or the accelerator chipmay perform the training stage and the AI data calculation by using the flash memoryand. In an embodiment, the flash memoryandmay include a memory controllerand a flash memory device, and an arithmetic unit provided in the memory controllermay be used so that the training stage and the inference AI data calculation performed by the APand/or the accelerator chipmay be performed more efficiently. The flash memoryandmay store images captured by the cameraor data transmitted via a data network. For example, augmented reality (AR)/virtual reality (VR), high definition (HD), or ultra high definition (UHD) contents may be stored.

2000 2500 2500 a b 1 FIG. 23 FIG. In the system, the DRAMandmay perform an operating method of the memory device described with reference toto.

While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the following claims.