Decentralized Arbitration Crossbar Network

This application claims the benefit of Taiwan Patent Application No. 114102999, filed Jan. 23, 2025, the subject matter of which is incorporated herein by reference.

The present invention relates to a crossbar network, and more particularly to a decentralized arbitration crossbar network.

As is well known, an IC chip includes a plurality of circuits. In addition, these circuits can transmit data and commands between each other. Correspondingly, a crossbar network is provided to transmit data and commands between circuits.

1 FIG.A 100 110 120 130 140 110 1 1 120 2 2 130 3 3 140 4 4 110 120 130 140 110 120 130 140 is a schematic circuit block diagram illustrating the architecture of a conventional IC chip. The IC chipis equipped with a first circuit, a second circuit, a third circuitand a fourth circuit. The first circuitincludes a transmitter Txand a receiver Rx. The second circuitincludes a transmitter Txand a receiver Rx. The third circuitincludes a transmitter Txand a receiver Rx. The fourth circuitincludes a transmitter Txand a receiver Rx. Furthermore, each of the first circuit, the second circuit, the third circuitand the fourth circuitcan receive data and commands from the other three circuits. For example, each of the first circuit, the second circuit, the third circuitand the fourth circuitis one of a control unit, a storage unit, a data processing unit and a graphic processing unit.

100 110 120 130 140 150 151 152 153 154 In order to realize the above relationship, the IC chipis further equipped with an arbitrating unit to allocate the data paths between all the circuits,,,to transmit data and commands. The arbitrating unit includes an arbitratorand a plurality of multiplexers,,,.

151 1 2 3 4 110 120 130 140 151 1 110 151 152 1 2 3 4 110 120 130 140 152 2 120 152 153 1 2 3 4 110 120 130 140 153 3 130 153 154 1 2 3 4 110 120 130 140 154 4 140 154 A B C D The four input terminals of the first multiplexerare respectively connected with the transmitters Tx, Tx, Txand Txof the four circuits,,and. The output terminal of the first multiplexeris connected with the receiver Rxof the first circuit. The select terminal of the first multiplexerreceives a first select signal S. The four input terminals of the second multiplexerare respectively connected with the transmitters Tx, Tx, Txand Txof the four circuits,,and. The output terminal of the second multiplexeris connected with the receiver Rxof the second circuit. The select terminal of the second multiplexerreceives a second select signal S. The four input terminals of the third multiplexerare respectively connected with the transmitters Tx, Tx, Txand Txof the four circuits,,and. The output terminal of the third multiplexeris connected with the receiver Rxof the third circuit. The select terminal of the third multiplexerreceives a third select signal S. The four input terminals of the fourth multiplexerare respectively connected with the transmitters Tx, Tx, Txand Txof the four circuits,,and. The output terminal of the fourth multiplexeris connected with the receiver Rxof the fourth circuit. The select terminal of the fourth multiplexerreceives a fourth select signal S.

150 110 120 130 140 150 110 150 120 150 130 150 140 150 110 120 130 140 1 2 3 4 1 2 3 4 The arbitratoris connected with four circuits,,and. The arbitratorand the first circuitexchange link information with each other according to a first communication signal C. The arbitratorand the second circuitexchange link information with each other according to a second communication signal C. The arbitratorand the third circuitexchange link information with each other according to a third communication signal C. The arbitratorand the fourth circuitexchange link information with each other according to a first communication signal C. Furthermore, the arbitratoris used to configure the data paths between the circuits,,andaccording to the link information of the four communication signals C, C, Cand C.

1 FIG.B 1 2 3 4 150 110 120 150 130 140 schematically illustrates the operations of the conventional IC chip. For example, according to the four communication signals C, C, Cand C, the arbitratordetermines that data and commands are transmitted between the first circuitand the second. The arbitratoralso determines that data and commands are transmitted between the third circuitand the fourth circuit.

150 151 2 120 1 110 150 152 1 110 2 120 150 153 4 140 3 130 150 154 3 130 4 140 A B C D Meanwhile, the arbitratoruses the first select signal Sto control the first multiplexerto establish the data path, and thus the transmitter Txof the second circuitis connected with the receiver Rxof the first circuit. Similarly, the arbitratoruses the second select signal Sto control the second multiplexerto establish the data path, and thus the transmitter Txof the first circuitis connected with the receiver Rxof the second circuit. Similarly, the arbitratoruses the third select signal Sto control the third multiplexerto establish the data path, and thus the transmitter Txof the fourth circuitis connected with the receiver Rxof the third circuit. Similarly, the arbitratoruses the fourth select signal Sto control the fourth multiplexerto establish the data path, and thus the transmitter Txof the third circuitis connected with the receiver Rxof the fourth circuit.

150 110 120 130 140 110 120 130 140 110 120 130 140 1 2 3 4 After all data paths have been established, the arbiternotifies the four circuits,,andthrough the communication signals C, C, Cand C. Consequently, the four circuits,,andstart to transmit data and commands. In other words, the four circuits,,andcan transmit data and commands to the desired circuits through the established data paths.

150 110 130 110 150 130 110 130 150 150 150 153 150 110 130 1 3 C 1 Furthermore, if the data path needs to be changed, the arbitratorcan establish other data paths at an appropriate time. If the first circuitintends to transmit data and commands to the third circuit, the first circuitwill notify the arbitratorthrough the communication signal C. After the third circuitconfirms that the data and commands from the first circuitcan be received, the third circuitwill notify the arbitratorthrough the communication signal C. Meanwhile, the arbitratorinitiates the arbiteruses the third select signal Sto control the third multiplexerto establish a new data path. After the new data path is established, the arbitratornotifies the first circuitto transmit the data and commands to the third circuitthrough the communication signal C.

2 FIG. 1 FIG.A 2 FIG. 260 1 2 3 4 5 6 1 2 3 4 5 6 1 1 2 2 1 2 3 4 5 6 1 2 3 4 5 6 Generally, the data transmission inside an IC chip is realized by using a crossbar network.schematically illustrates the architecture of a conventional crossbar network. The crossbar network includes an arbitrating unit, a plurality of transmitters Tx, Tx, Tx, Tx, Tx, Tx, and a plurality of receivers Rx, Rx, Rx, Rx, Rx, Rx. Like the architecture, the transmitter Txand the receiver Rxare included in a first circuit (not shown), the transmitter Txand the receiver Rxare included in a second circuit (not shown), . . . , and so on. In, six transmitters Tx, Tx, Tx, Tx, Tx, Txand six receivers Rx, Rx, Rx, Rx, Rx, Rxare presented herein for illustration. It is noted that the number of the transmitters and the number of the receivers are not restricted. That is, the number of the transmitters and the number of the receivers in the crossbar network may be varied according to the practical requirements.

260 250 251 252 253 254 255 256 251 1 2 3 4 5 6 251 1 251 252 1 2 3 4 5 6 252 2 252 256 1 2 3 4 5 6 256 6 256 The arbitrating unitincludes an arbitratorand a plurality of multiplexers,,,,and. The input terminals of the multiplexerare connected with the transmitters Tx, Tx, Tx, Tx, Txand Tx. The output terminal of the multiplexeris connected with the receiver Rx. The select terminal of the multiplexerreceives a select signal S. The input terminals of the multiplexerare connected with the transmitters Tx, Tx, Tx, Tx, Txand Tx. The output terminal of the multiplexeris connected with the receiver Rx. The select terminal of the multiplexerreceives the select signal S. The rest may be deduced by analogy. The input terminals of the multiplexerare connected with the transmitters Tx, Tx, Tx, Tx, Txand Tx. The output terminal of the multiplexeris connected with the receiver Rx. The select terminal of the multiplexerreceives the select signal S.

251 252 253 254 255 256 250 251 252 253 254 255 256 1 2 3 4 5 6 1 2 3 4 5 6 250 1 2 3 4 5 6 1 2 3 4 5 6 Furthermore, the select signal S contains a plurality of sub-select signals for controlling corresponding multiplexers,,,,and. In other words, the arbitratorinitiates the select signal S to control the multiplexers,,,,andto establish a plurality of data paths between the transmitters Tx, Tx, Tx, Tx, Tx, Txand the receivers Rx, Rx, Rx, Rx, Rx, Rx. Similarly, the arbitratorexchanges link information with the transmitters Tx, Tx, Tx, Tx, Tx, Txand the receivers Rx, Rx, Rx, Rx, Rx, Rxaccording to communication signals (not shown). Consequently, the data paths are determined.

260 250 As mentioned above, the conventional crossbar network requires the arbitrating unitto configure all data paths. Furthermore, in order to establish a new data path, the arbitratorneeds to implement coordination and allocation again.

Furthermore, as the numbers of transmitters and receivers in the crossbar network increase, the number of communication lines increases. Consequently, the internal connection design of the IC chip becomes more complicated.

1 2 3 4 5 6 1 2 3 4 5 6 250 1 2 3 4 5 6 1 2 3 4 5 6 250 1 2 3 4 5 6 1 2 3 4 5 6 Alternatively, the communication signals can be transmitted between the transmitters Tx, Tx, Tx, Tx, Tx, Txand the receivers Rx, Rx, Rx, Rx, Rx, Rxthrough a shared communication line. Under this circumstance, the arbitratorsequentially exchanges link information with the transmitters Tx, Tx, Tx, Tx, Tx, Txand the receivers Rx, Rx, Rx, Rx, Rx, Rxin a polling manner. Since it is time-consuming for the arbitratorto exchange link information with the transmitters Tx, Tx, Tx, Tx, Tx, Txand the receivers Rx, Rx, Rx, Rx, Rx, Rxin the polling manner, the operating performance of the crossbar network is deteriorated.

An embodiment of the present invention provides a crossbar network. The crossbar network includes a first circuit, a second circuit, a first bus, a second bus, a first multiplexing device, a second multiplexing device, a first link detecting device and a second link detecting device. The first circuit includes a first transmitter and a first receiver. The second circuit includes a second transmitter and a second receiver. The first bus is connected to the first transmitter of the first circuit. The second bus is connected to the second transmitter of the second circuit. The first multiplexing device is connected to the second bus. The first receiver of the first circuit is coupled to the second bus through the first multiplexing device. The second multiplexing device is connected to the first bus. The second receiver of the second circuit is coupled to the first bus through the second multiplexing device. The first link detecting device is coupled to the second bus. When the second circuit initiates a link request to the first circuit, the first link detecting device detects the link request and notifies the first circuit through the second bus. The second link detecting device is coupled to the first bus. When the first circuit initiates the link request to the second circuit, the second link detecting device detects the link request and notifies the second circuit through the first bus.

Numerous objects, features and advantages of the present invention will be readily apparent upon a reading of the following detailed description of embodiments of the present invention when taken in conjunction with the accompanying drawings. However, the drawings employed herein are for the purpose of descriptions and should not be regarded as limiting.

The present invention proposes a decentralized arbitration crossbar network. In accordance with a feature of the present invention, the crossbar network is not equipped with an arbitrating unit to configure a data path. Instead, after a three-way handshake process between two circuits is performed, the data path is established. In other words, a link can be established after the three-way handshake process between two circuits is performed.

3 FIG.A 310 320 330 340 310 320 330 340 310 320 330 340 schematically illustrates the architecture of a crossbar network according to an embodiment of the present invention. The crossbar network is designed in an IC chip. In an embodiment, the crossbar network includes a first circuit, a second circuit, a third circuitand a fourth circuit. Each of the first circuit, the second circuit, the third circuitand the fourth circuitcorresponds to a unique address. In other words, the addresses of the first circuit, the second circuit, the third circuitand the fourth circuitare different.

310 314 1 1 320 324 2 2 330 334 3 3 340 344 4 4 The first circuitincludes a link allocation device, a transmitter Txand a receiver Rx. The second circuitincludes a link allocation device, a transmitter Txand a receiver Rx. The third circuitincludes a link allocation device, a transmitter Txand a receiver Rx. The fourth circuitincludes a link allocation device, a transmitter Txand a receiver Rx.

310 312 316 320 322 326 330 332 336 340 342 346 312 322 332 342 316 326 336 346 310 320 330 340 The first circuitfurther includes a multiplexing deviceand a link detecting device. The second circuitfurther includes a multiplexing deviceand a link detecting device. The third circuitfurther includes a multiplexing deviceand a link detecting device. The fourth circuitfurther includes a multiplexing deviceand a link detecting device. The multiplexing devices,,andand the link detecting devices,,andmay be respectively designed outside the circuits,,and.

310 320 330 340 310 320 330 340 3 FIG.A For example, each of the circuits,,andis one of a control unit, a storage unit, a processing unit, a graphics processing unit, or the like. The crossbar network inincludes four circuits,,,only. It is noted that the number of circuits in the crossbar network is not restricted. That is, the number of circuits in the crossbar network is greater than or equal to 2.

3 FIG.A 1 310 2 320 3 330 4 340 1 2 3 4 Furthermore, the transmitter of each circuit is connected to the corresponding bus, and the signals sent by each circuit are transmitted through the corresponding bus. As shown in, the transmitter Txof the first circuitis connected to a first bus Bus, the transmitter Txof the second circuitis connected to a second bus Bus, the transmitter Txof the third circuitis connected to a third bus Bus, and the transmitter Txof the fourth circuitis connected to a fourth bus Bus.

1 310 2 320 3 330 4 340 1 1 1 1 1 2 2 2 2 2 3 3 3 3 3 4 4 4 4 4 The signals from the transmitter Txof the first circuitcontain a data signal D, an address signal A, a clock signal CKand a command signal CMD, and these signals are transmitted through the first bus Bus. The signals from the transmitter Txof the second circuitcontain a data signal D, an address signal A, a clock signal CKand a command signal CMD, and these signals are transmitted through the second bus Bus. The signals from the transmitter Txof the third circuitcontain a data signal D, an address signal A, a clock signal CKand a command signal CMD, and these signals are transmitted through the third bus Bus. The signals from the transmitter Txof the fourth circuitcontain a data signal D, an address signal A, a clock signal CKand a command signal CMD, and these signals are transmitted through the fourth bus Bus.

1 310 312 2 320 322 3 330 332 4 340 342 312 322 332 342 1 2 3 4 2 3 4 1 3 4 1 2 4 1 2 3 Furthermore, the receiver of each circuit is coupled to all non-corresponding buses through the corresponding multiplexing device. Consequently, the receiver can be coupled to one of the non-corresponding buses by controlling the multiplexing device. For example, the receiver Rxof the first circuitis coupled to the second bus Bus, the third bus Busand the fourth bus Busthrough the multiplexing device. Similarly, the receiver Rxof the second circuitis coupled to the first bus Bus, the third bus Busand the fourth bus Busthrough the multiplexing device. Similarly, the receiver Rxof the third circuitis coupled to the first bus Bus, the second bus Busand the fourth bus Busthrough the multiplexing device. The receiver Rxof the fourth circuitis coupled to the first bus Bus, the second bus Busand the third bus Busthrough the multiplexing device. In some other embodiments, the multiplexing devices,,andcan also be integrated into the corresponding receivers Rx, Rx, Rxand Rx.

312 310 1 1 312 1 310 320 1 310 312 1 2 320 310 340 1 310 312 1 4 340 2 3 4 320 330 340 310 1 1 2 3 4 1 2 1 2 2 2 2 2 4 1 4 4 4 4 4 For example, the multiplexing devicein the first circuitincludes four multiplexers. According to a select signal S, four signals from a specified bus are transmitted to the receiver Rxthrough the four multiplexers. That is, the receiver Rxuses the select signal Sto control the multiplexing device, and thus the receiver Rxis coupled to one of the second bus Bus, the third bus Busand the fourth bus Busaccording to the select signal S. If the first circuitdecides to be couple to the second bus Buscorresponding to the second circuit, the receiver Rxof the first circuituses the select signal Sto control the four multiplexers in the multiplexing device. Consequently, the receiver Rxreceives the data signal D, the address signal A, the clock signal CKand the command signal CMDfrom the second bus Bus. These signals are outputted from the transmitter Txof the second circuit. Similarly, if the first circuitdecides to be coupled to the fourth bus Buscorresponding to the fourth circuit, the receiver Rxof the first circuituses the select signal Sto control the four multiplexers in the multiplexing device. Consequently, the receiver Rxreceives the data signal D, the address signal A, the clock signal CKand the command signal CMDfrom the fourth bus Bus. These signals are outputted from the transmitter Txof the fourth circuit. The control methods of the receivers Rx, Rxand Rxin the other circuits,andare similar to the control method of the first circuit, and not redundantly described herein.

316 310 326 320 336 330 346 340 2 3 4 1 3 4 1 2 4 1 2 3 Furthermore, the link detecting device of each circuit is connected to all non-corresponding buses. The link detecting device is used to detect whether any other circuit initiates a link request and notify the link allocation device. For example, the link detecting deviceof the first circuitis connected to the second bus Bus, the third bus Busand the fourth bus Bus. Similarly, the link detecting deviceof the second circuitis connected to the first bus Bus, the third bus Busand the fourth bus Bus. Similarly, the link detecting deviceof the third circuitis connected to the first bus Bus, the second bus Busand the fourth bus Bus. Similarly, the link detecting deviceof the fourth circuitis connected to the first bus Bus, the second bus Busand the third bus Bus.

316 310 320 330 340 316 316 316 2 3 4 2 2 3 3 4 4 For example, the link detecting deviceof the first circuitis connected to the second bus Bus, the third bus Busand the fourth bus Busto detect whether the second circuit, the third circuitor the fourth circuitinitiates the link request. In an embodiment, a link detector Ldof the link detecting deviceis connected to the second bus Bus, a link detector Ldof the link detecting deviceis connected to the third bus Bus, and a link detector Ldof the link detecting deviceis connected to the fourth bus Bus.

320 310 310 320 316 314 310 340 310 310 340 316 314 310 326 336 346 320 330 340 326 336 346 320 330 340 310 2 2 2 2 2 4 4 4 4 4 When the second circuitinitiates a link request to the first circuit, the link detector Ldof the first circuitconfirms that the second circuitinitiates the link request according to the address signal A, the clock signal CKand the command signal CMDon the second bus Bus, and then the link detecting devicenotifies the link allocation deviceof the first circuit. Similarly, when the fourth circuitinitiates a link request to the first circuit, the link detector Ldof the first circuitconfirms that the fourth circuitinitiates the link request according to the address signal A, the clock signal CKand the command signal CMDon the fourth bus Bus, and then the link detecting devicenotifies the link allocation deviceof the first circuit. Of course, the link detecting device,andof the other circuits,andcan detect the link request. The operations of the link detecting device,andof the circuits,andare similar to those of the first circuit, and not redundantly described herein.

314 310 310 320 330 340 316 310 316 320 330 340 314 310 320 330 340 314 324 334 344 314 324 334 344 310 320 330 340 2 3 4 2 3 4 In an embodiment, the link allocation devicein the first circuitcan set a link priority to determine the order of establishing links between the first circuitand other circuits,and. For example, since the link detecting deviceof the first circuitis connected to the second bus Bus, the third bus Busand the fourth bus Bus, the three link detectors Ld, Ldand Ldin the link detecting devicecan receive link requests from the other three circuits,andat the same time. According to the setting of the link priority, the link allocation devicecan determine the order of establishing the links between the first circuitand the other circuits,and. In an embodiment, each of the link allocation devices,,andsets the link priority. Furthermore, the link allocation devices,,andin the circuits,,andcan appropriately modify the corresponding link priority according to the actual operation status.

316 326 336 346 314 324 334 344 316 326 336 346 314 324 334 344 1 2 3 4 314 324 334 344 310 320 330 340 It is noted that numerous modifications may be made while retaining the teachings of the present invention. For example, in a variant example, the link detecting devices,,andare respectively integrated into the link allocation devices,,and. In another variant example, the link detecting devices,,andand link allocation devices,,andare respectively integrated into the receivers Rx, Rx, Rxand Rx. Alternatively, the link allocation devices,,andin the circuits,,andare omitted. Under this circumstance, the sequence of establishing the link between the circuits can be determined according to a preset sequence.

316 310 316 310 In the above embodiment, the link detecting deviceof the first circuitdetects whether any of the other circuits initiates the link request according to the address signal, the clock signal and the command signal. It is noted that numerous modifications may be made while retaining the teachings of the present invention. For example, in another embodiment, link detecting deviceof the first circuitdetects whether any of the other circuits initiates the link request according to the address signal and the command signal only.

3 FIG.B 3 FIG.C 310 320 330 340 310 320 330 340 320 310 is a flowchart illustrating an operation process of the initiator in the crossbar network of the present invention.is a flowchart illustrating an operation process of the target in the crossbar network of the present invention. The initiator can be any of the circuits,,andin the crossbar network. The target can be any of the circuit,,andin the crossbar network. Furthermore, the initiator will not issue a link request to itself. In the following description, the second circuitis used as the initiator, and the first circuitis used as the target.

3 FIG.B 320 310 320 351 320 2 Please refer toagain. When the second circuitintends to establish the link with the first circuit, the second circuitinitiates a link request (Step S). In addition, the link request is transmitted from the second circuitthrough the second bus Bus.

2 2 2 2 2 1 2 320 310 2 320 322 2 When the link request is initiated, the clock signal CKon the second bus Busis activated under control of the transmitter Txof the second circuit. In addition, the address signal Acontains the address of the first circuit, and the command signal CMDcontains a synchronous message (SYC). Afterwards, the receiver Rxof the second circuituses the control signal Sto control the multiplexer, so that the receiver Rxis coupled to the first bus Bus.

3 FIG.B 320 310 352 310 1 353 320 310 353 320 354 Please refer toagain. Then, the second circuitdetermines whether a link acceptance from the first circuitis received (step S), and the first circuittransmits the link acceptance through the first bus Bus. Before timeout (Step S), the second circuitcontinues to wait for the link acceptance from the first circuit. If the link acceptance is still not received after a certain time period, i.e., after timeout (Step S), the second circuitconfirms that the link fails (step S).

320 310 320 324 310 320 320 320 After the link fails, the second circuitcan continue to initiate a link request to the first circuit. For example, the second circuitmay adjust the setting of the link priority in the link allocation deviceto increase the link priority of the first circuitand initiate the link request again. Of course, the number of initiating the link request by the second circuitis limited. If the number of initiating the link request by the second circuitand the link still fails, the second circuitreports that the link fails and stops initiating the link request.

2 320 326 320 320 320 310 1 1 1 1 1 1 1 1 1 1 1 Furthermore, in the process of waiting for the link acceptance, the receiver Rxof the second circuitor the link detector Ldof the link detecting devicereceives the clock signal CK, the address signal Aand the command signal CMDfrom the first bus Bus. According to the clock signal CK, the link detector Lddecodes the address signal Aand the command signal CMD. When the second circuitconfirms that the address signal Acontains the address of the second circuitand the command signal CMDcontains the synchronous acceptance message (SYC ACPT), the second circuitconfirms that the first circuitsends the link acceptance.

3 FIG.B 352 320 355 310 2 Please refer to. After the link acceptance is received (Step S), the second circuitsends a link acknowledgement (Step S), and the link acknowledgement is transmitted to the first circuitthrough the second bus Bus.

2 2 2 2 2 320 310 310 320 After the link acknowledgement is issued, the clock signal CKon the second bus Busis activated under control of the transmitter Txof the second circuit. In addition, the address signal Acontains the address of the first circuit, and the command signal CMDcontains a synchronous acknowledge message (SYC ACK). Consequently, the first circuitcan receive the link acknowledgement from the second circuit.

3 FIG.B 320 310 356 320 310 2 Please refer toagain. After the link acknowledgement is issued, it means that the link between the second circuitand the first circuithas been established (Step S). Meanwhile, the second circuitcan start to transmit data and commands to the first circuitthrough the second bus Bus.

1 310 312 1 320 2 1 310 320 310 1 2 2 2 2 2 2 When the link is established, the receiver Rxof the first circuituses the select signal Sto control all multiplexers in the multiplexing device, and thus the data signal D, the address signal A, the clock signal CKand the command signal CMDare transmitted to the receiver Rxthrough the second bus Bus. Consequently, the data and the commands of the second circuitcan be outputted from the transmitter Txand transmitted to the receiver Rxof the first circuitthrough the second bus Bus. Furthermore, in order to terminate the connection, the second circuitonly needs to send a link termination to the first circuitto terminate the link.

3 FIG.C 310 320 330 340 361 310 316 310 310 310 320 310 330 310 340 2 2 2 2 2 2 2 2 2 2 2 3 3 4 4 Please refer to. The first circuitcan receive the link requests from other circuits,andat any time (Step S). For example, in the first circuit, the link detector Ldof the link detecting devicereceives the clock signal CK, the address signal Aand the command signal CMDfrom the second bus Bus. According to the clock signal CK, the link detector Lddecodes the address signal Aand the command signal CMD. After the first circuitconfirms that the address signal Acontains the address of the first circuitand the command signal CMDcontains a synchronous message (SYC), the first circuitconfirms that the second circuithas initiates a link request. Similarly, the link detector Ldof the first circuitcan judge whether the third circuithas initiated a link request through the third bus Bus. Similarly, the link detector Ldof the first circuitcan judge whether the fourth circuithas initiated a link request through the fourth bus Bus.

336 330 346 340 310 336 330 346 340 2 2 As mentioned above, the link detecting deviceof the third circuitand the link detecting deviceof the fourth circuitare also connected to the second bus Bus. However, since the address signal Acontains the address of the first circuit, the link detecting deviceof the third circuitand the link detecting deviceof the fourth circuitwill ignore (don't care) this link request.

3 FIG.C 310 362 363 310 364 310 314 320 310 362 310 365 310 1 Please refer toagain. When the first circuitis in a busy state (step S) for more than a certain time, i.e., a timeout (step S), the first circuitcannot issue a link acceptance, indicating a link failure (step S). Meanwhile, the first circuitmay adjust the setting of the link priority in the link allocation deviceto increase the link priority of the second circuit. When the first circuitis not in the busy state (Step S), the first circuitsends the link acceptance (step S), and the first circuittransmits the link acceptance through the first bus Bus.

1 1 1 1 1 2 1 310 320 1 310 312 1 When the link acceptance is issued, the clock signal CKon the first bus Busis activated under control of the transmitter Txof the first circuit. In addition, the address signal Acontains the address of the second circuit, and the command signal CMDcontains the synchronous acceptance message (SYC ACPT). Afterwards, the receiver Rxof the second circuituses the control signal Sto control the multiplexing device, so that the receiver Rxis coupled to the second bus Bus.

3 FIG.C 310 366 1 310 316 2 310 310 310 320 2 2 2 2 2 2 2 2 2 2 Please refer toagain. Then, the first circuitwaits for the link acknowledgment (Step S). While waiting for the link acknowledgment, the receiver Rxof the first circuitor the link detector Ldof the link detecting devicereceives the clock signal CK, the address signal Aand the command signal CMDfrom the second bus Bus. According to the clock signal CK, the link detector Lddecodes the address signal Aand the command signal CMD. When the first circuitconfirms that the address signal Acontains the address of the first circuitand the command signal CMDcontains the synchronous acknowledge message (SYC ACK), the first circuitconfirms that the second circuitsends the link acknowledgement.

3 FIG.C 320 310 367 310 320 1 Please refer toagain. After the link acknowledgement is received, it means that the link between the second circuitand the first circuithas been established (Step S). Meanwhile, the first circuitcan start to transmit data and commands to the second circuitthrough the second bus Bus.

2 320 322 2 310 1 2 320 310 320 2 1 1 1 1 1 1 When the link is established, the receiver Rxof the second circuituses the select signal Sto control all multiplexers in the multiplexing device, and thus the data signal D, the address signal A, the clock signal CKand the command signal CMDare transmitted to the receiver Rxthrough the first bus Bus. Consequently, the data and the commands of the first circuitcan be outputted from the transmitter Txand transmitted to the receiver Rxof the second circuitthrough the first bus Bus. Furthermore, in order to terminate the connection, the first circuitonly needs to send a link termination to the second circuitto terminate the link.

3 FIG.B 3 FIG.C 320 310 320 310 310 320 320 310 320 310 320 2 1 310 310 1 2 320 2 1 2 2 1 As mentioned inand, a three-way handshake process is required to establish the link between two circuits. For example, the second circuitis the initiator, and the first circuitis the target. The second circuittransmits a link request to the first circuitthrough the second bus Bus. Then, the first circuittransmits a link acceptance to the second circuitthrough the first bus Bus. Finally, the second circuittransmits a link acknowledgement to the first circuitthrough the second bus Bus, and the link between the second circuitand the first circuitis established. Consequently, the data and the commands of the second circuitcan be outputted from the transmitter Txand transmitted to the receiver Rxof the first circuitthrough the second bus Bus. In addition, the data and the commands of the first circuitcan be outputted from the transmitter Txand transmitted to the receiver Rxof the second circuitthrough the first bus Bus.

4 FIG. 3 FIG.A 4 FIG. 3 FIG.A 4 FIG. 421 422 423 424 421 422 423 424 1 2 3 4 Hereinafter, the detailed circuitry structures will be described as follows.schematically illustrates a simplified version of the architecture of the crossbar network shown in. The architecture of the crossbar network shown inis similar to the architecture of the crossbar network shown in. In, the crossbar network further includes phase conversion devices,,and. Similarly, the phase conversion devices,,andcan also be respectively integrated into the corresponding receivers Rx, Rx, Rxand Rx.

1 1 2 2 3 3 4 4 1 2 3 4 4 FIG. In this embodiment, the crossbar network includes four circuits (not shown). Similarly, the first circuit includes a transmitter Txand a receiver Rx, the second circuit includes a transmitter Txand a receiver Rx, the third circuit includes a transmitter Txand a receiver Rx, and the fourth circuit includes a transmitter Txand a receiver Rx. In addition, the link detecting device and the link allocation device in each circuit ofare integrated into the corresponding one of the receivers Rx, Rx, Rxand Rx.

4 FIG. 1 2 3 4 1 2 3 4 Furthermore, the transmitter of each circuit is connected to the corresponding bus. As shown in, the transmitter Txof the first circuit is connected to a first bus Bus, the transmitter Txof the second circuit is connected to a second bus Bus, the transmitter Txof the third circuit is connected to a third bus Bus, and the transmitter Txof the fourth circuit is connected to a fourth bus Bus.

Furthermore, the receiver of each circuit is coupled to all non-corresponding buses through the corresponding multiplexing device and the corresponding phase conversion device. Consequently, the receiver can be selectively coupled to one of the non-corresponding buses.

4 FIG. 1 312 1 2 322 2 3 332 3 4 342 4 1 2 3 4 1 2 1 3 4 2 3 1 2 4 3 4 1 2 3 4 As shown in, the receiver Rxuses the select signal Sto control the multiplexing device, and thus the receiver Rxis selectively coupled to one of the second bus Bus, the third bus Busand the fourth bus Busaccording to the select signal S. Similarly, the receiver Rxuses the select signal Sto control the multiplexing device, and thus the receiver Rxis selectively coupled to one of the first bus Bus, the third bus Busand the fourth bus Busaccording to the select signal S. Similarly, the receiver Rxuses the select signal Sto control the multiplexing device, and thus the receiver Rxis selectively coupled to one of the first bus Bus, the second bus Busand the fourth bus Busaccording to the select signal S. Similarly, the receiver Rxuses the select signal Sto control the multiplexing device, and thus the receiver Rxis selectively coupled to one of the first bus Bus, the second bus Busand the third bus Busaccording to the select signal S.

316 326 336 346 316 326 336 346 314 324 334 344 421 422 423 424 Furthermore, each of the link detecting devices,,andis connected to all non-corresponding buses used to detect whether any other circuit initiates a link request. The link detecting devices,,andare coupled to the corresponding link allocation devices,,andthrough the phase conversion devices,,and, respectively.

4 424 342 344 424 346 346 1 2 3 1 2 3 1 1 1 1 2 2 2 2 3 3 3 3 For example, the receiver Rxin the fourth circuit is coupled to all non-corresponding buses Bus, Busand Busthrough the phase conversion deviceand the multiplexing device. In addition, the link allocation deviceis coupled to all non-corresponding buses Bus, Busand Busthrough the phase conversion deviceand the link detecting device. The link detecting devicereceives the address signal A, the clock signal CKand the command signal CMDfrom the first bus Bus, receives the address signal A, the clock signal CKand the command signal CMDfrom the second bus Bus, and receives the address signal A, the clock signal CKand the command signal CMDfrom the third bus Bus.

4 424 4 424 4 4 1 1 1 1 1 1 1 1 1 4 1 1 1 1 When the receiver Rxis coupled to the first bus Bus, the phase conversion devicecan ensure that the data signal D, the address signal A, the clock signal CKand the command signal CMDreceived by the receiver Rxare correct. That is, the phase conversion deviceneeds to remove the noise on the first bus Busand adjust the phases of the data signal D, the address signal Aand the command signal CMDaccording to the clock signal CK. After the phases are adjusted, these signals are transmitted to the receiver Rx. Consequently, it is ensured that the data signal D, the address signal A, the clock signal CKand the command signal CMDreceived by the receiver Rxare correct.

344 424 346 4 344 1 1 1 1 1 Similarly, the link allocation deviceis coupled to the first bus Bus, through the phase conversion deviceand the link detecting devicein order to ensure that the data signal D, the address signal A, the clock signal CKand the command signal CMDreceived by the receiver Rxare correct. Consequently, the link allocation devicecan accurately detect the link request.

424 424 454 464 466 454 464 342 4 466 346 344 4 454 4 342 454 454 464 4 466 4 FIG. 1 1 1 1 1 1 1 1 1 4 1 An example of the phase conversion devicewill be described as follows. Please refer to. The phase conversion deviceincludes an integrated clock gating device (ICG device)and two phase alignment devices (PA devices)and. The ICG deviceand the PA deviceare coupled between the multiplexing deviceand the receiver Rx. The PA deviceis coupled between the link detecting deviceand the link allocation device. Before the receiver Rxis coupled to the first bus Bus, the ICG deviceis disabled to temporarily isolate the clock signal CKto prevent noise from being generated during the bus switching process. Then, the receiver RXcontrols the multiplexing deviceto switch to the first bus Bus. Afterwards, the ICG deviceis enabled, and thus the clock signal CKis permitted to pass through the ICG device. Then, the clock signal CK, the data signal D, the address signal Aand the command signal CMDfrom the first bus Busare aligned with the clock signal CKby the PA device. Consequently, the receiver Rxcan accurately receive all signals from the first bus Bus. The operations of the PA deviceare similar, and not redundantly described herein.

464 466 464 1 4 Furthermore, the PA devicesandcan be replaced by clock domain crossing devices (CDC devices). The function of the CDC device is similar to the function of the PA device. By the CDC device, all signals from the first bus Buscan be aligned with the clock signal CK.

5 FIG. 4 FIG. 5 FIG. In order to reduce the power consumption, the bus in the crossbar network is modified. For example, the bus is divided into a plurality of parts. According to the locations of the initiator and the target, the transmitter of the circuit only sends signals to a part of the bus.schematically illustrates the architecture of a crossbar network according to another embodiment of the present invention. In comparison with the crossbar network of, each of the four buses in the crossbar network ofis divided into two parts.

5 FIG. 1 2 3 4 1 2 3 4 1_L 1_R 2_L 2_R 3_L 3_R 4_L 4_R 1 2 3 4 As shown in, the transmitter Txis connected to the first bus left side part Busand the first bus right side part Bus, the transmitter Txis connected to the second bus left side part Busand the second bus right side part Bus, the transmitter Txis connected to the third bus left side part Busand the third bus right side part Bus, and the transmitter Txis connected to the fourth bus left side part Busand the fourth bus right side part Bus. According to the locations of the initiator and the target, each of the transmitters Tx, Tx, Txand Txtransmit signals through a part of each of the buses Bus, Bus, Busand Bus.

1 4 1 1 4 1_R 4_L 1_R For example, the first circuit initiates a link request to the fourth circuit. After a three-way handshake process between the first circuit and the fourth circuit is performed, the data path is established. Firstly, the transmitter Txof the first circuit sends a link request to the receiver Rxof the fourth circuit through the first bus right side part Bus. Then, the transmitter of the fourth circuit sends a link acceptance to the receiver Rxof the first circuit through the fourth bus left side part Bus. Afterwards, the transmitter Txof the first circuit sends a link acknowledgement to the receiver Rxof the fourth circuit through the first bus right side part Bus. Consequently, the link between the first circuit and the fourth circuit is established.

1 4 4 1 1_R 4_L 1_L 4_R After the link between the first circuit and the fourth circuit is established, the transmitter Txof the first circuit sends data and commands to the receiver Rxof the fourth circuit through the first bus right side part Bus, and the transmitter Txof the fourth circuit sends data and commands to the receiver Rxof the first circuit through the fourth bus left side part Bus. During the three-way handshake process and during the process of transmitting data and commands after link establishment, both of the first bus left side part Busand the fourth bus right side part Busare not used to transmit signals. Consequently, the power-saving efficacy of the crossbar network is enhanced.

1 2 3 4 1 2 3 4 1 1 1 1 1 1 1 MD1 1 1 In the above embodiments, each of the buses Bus, Bus, Busand Buscan transmit four signals. However, each of the buses Bus, Bus, Busand Buscan transmit more or less signals according to the practical requirements. For example, the address of the data signal Dand the address of the command signal CMDare transmitted through the first bus Busaccording to the address signal A. In a variant example, two address signals are designed for the first bus Bus. The data address is transmitted according to one address signal, and the command address according to the other address signal. In another variant example, the data signal D, the address signal Aand the command signal Care combined into a general signal. Consequently, only the clock signal CKand the general signal are transmitted through the first bus Bus.

314 324 334 344 310 320 330 340 310 320 330 340 320 320 310 Furthermore, the weight of the link priority in each of the link allocation devices,,andof the circuits,,andcan be set according to the practical requirements. In an embodiment, the weights of the link priority about the link acknowledgement, the link acceptance and the link request are different according to settings. For example, the link acknowledgement has the highest weight of the link priority, the link acceptance has the second highest weight of the link priority, and the link request has the lowest weight of the link priority. According to the number of link failures, the circuits,,andmay also adjust the weights of the link priorities. Furthermore, when the second circuitreceives the link termination, the weight of the link priority for linking the second circuitto the first circuitwill be decreased.

While the invention has been described in terms of what is presently considered to be the most practical and preferred embodiments, it is to be understood that the invention needs not be limited to the disclosed embodiment. On the contrary, it is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims which are to be accorded with the broadest interpretation so as to encompass all such modifications and similar structures.