Hybrid Memory

The disclosed embodiments relate generally to memory systems, components, and methods.

A hybrid memory module employs relatively fast, durable, and expensive dynamic, random-access memory (DRAM) components to cache a subset of data stored in a larger amount of relatively slow, wear-sensitive, and inexpensive nonvolatile memory. The DRAM components store the subset of data in association with address tags that map to addresses in the nonvolatile memory. An address buffer component on the memory module caches a subset of the address tags in a static random-access memory (SRAM). Together, the DRAM and SRAM caches hasten read and write access and reduce wear for a larger amount of nonvolatile memory. The address buffer component also manages communication between the DRAM cache and the nonvolatile memory to accommodate disparate access granularities, reduce the requisite number of memory transactions, and minimize the flow of data to and from nonvolatile memory. The memory module thus combines the nonvolatility and reduced per-bit price of nonvolatile memory with the speed and durability of DRAM.

1 FIG.A 100 105 110 115 0 1 115 115 0 115 1 116 115 0 115 1 115 0 117 115 0 115 1 depicts a memory systemin which a motherboardsupports a memory controllerthat communicates with a hybrid memory modulevia twenty pairs of nibble-wide (four-bit, or ×4) primary data ports DQu/DQv and two primary command-and-address (CA) ports DCAand DCA. Memory moduleis logically divided into two module halves() and() that can be controlled separately or together to communicate either forty-bit or eighty-bit data over a module connector. Halves() and() are identical for purposes of this disclosure; the following discussion focusses on low-order module half(). Linksbetween module halves() and() allow both to respond to the same commands in the eighty-bit mode.

115 0 118 0 118 0 125 4 0 110 118 0 119 Module half() includes a local address buffer(), sometimes referred to as a register or registering clock driver (RCD), or a module controller. Address buffer() is an integrated-circuit (IC) component that manages five memory slices[:] at the direction of external controller. Address buffer() is a sophisticated local controller that manages read and write accesses using a multi-set SRAM address cacheto hasten cache hit and miss decisions, and thus improve speed performance.

125 4 0 130 130 135 130 130 130 135 118 0 130 130 125 4 115 0 118 0 125 3 0 130 130 th Each slice[:] includes two nonvolatile memory componentsF, two DRAM componentsD, and a data-buffer (DB) component. Memory componentsF are NAND flash components, but other types of nonvolatile memory can be used. DRAM componentsD collectively have e.g. one one-sixteenth ( 1/16) the storage capacity of flash componentsF. Among other tasks, each DB componentworks with address buffer() to manage the flow of data between DRAM componentsD of the same slice and flash componentsF from the same or different slices. The following discussion focuses on memory slice[], the slice in module half() closest to address buffer(). The remaining slices[:] are essentially identical. DRAM and flash memories can be arranged differently in other embodiments. Where DRAM componentsD are organized in slices, for example, it could be that flash componentsF are separate from all or a subset of these slices. For example, only every other slice with one or more DRAM component might also include flash memory.

118 0 110 0 15 0 0 1 0 118 0 135 4 0 130 130 Address buffer() receives commands from external controllervia links CA[:] and returns status information via links Stat[:]. Address buffer() also controls: DB components[:] via a local communication bus BCOM; DRAM componentsD via a DRAM control bus CSs/CAs (for chip-select/command, and address); and flash componentsF via a flash data and control bus ADQf. In one embodiment, bus ADQf conforms to an interface specification known as ONFI, for “Open NAND Flash Interface.” Other embodiments can use different interfaces and different types of volatile and nonvolatile memory.

125 4 135 4 110 39 32 130 39 32 135 4 125 4 0 115 0 110 115 0 130 130 110 130 4 4 FIGS.A andB Remaining focused on slice[], DB component[] communicates with controllervia eight primary data links DQp[:] and with DRAM componentsD via a corresponding eight secondary data links DQs[:]. Read and write memory accesses are accomplished in sixteen-bit bursts, so DB component[] communicates 128 bits (4×2×16 b=128 b) for each memory access, and the five slices[:] of module half() communicate a cumulative 640 bits (5×128 b=640 b) with external controller. Using ten-bit bytes, module half() thus exhibits an access granularity of sixty-four bytes (64 B). DRAM componentsD are collectively employed as cache memory, and the data sets transferred between DRAM componentsD memory and either controlleror flash componentsF are termed “cache lines.” Each cache line provides 64 B of data, and can include additional bits for e.g. error-detection and correction (EDC), parity, and various cache-related functions. An embodiment that uses 80 B cache lines to store 64 B data and related information is detailed below in connection with.

110 130 130 118 0 130 135 4 0 118 0 130 115 0 External controllerissues read commands that request information from specific addresses in flash componentsF. If requested data is cached in DRAM componentsD, then address buffer() manages the delivery of that cache line from a rank of ten DRAM componentsD via five DB components[:]. In this context, a “rank” refers to a set of components that address buffer() accesses (read or write) responsive to a host-side memory request. Each DRAM componentD has a data width of four bits, so module half() has a rank width of forty bits.

118 0 130 130 115 0 118 0 125 4 0 130 110 130 If the requested data is not in cache—a so-called cache miss—address buffer() reads the requested data from one or more of flash componentsF via local bus ADQf and distributes the requested cache line evenly across all ten DRAM componentsD of module half(). A local bidirectional or paired unidirectional daisy-chain data bus DQt provides point-to-point connections between address buffer() and each slice[:]. Caching a subset of each cache line in each DRAM componentD supports parallel, high-speed read and write access for host controller. Storing complete flash cache lines in individual flash componentsF facilitates fast and efficient cache write-back and garbage-collection processes.

1 FIG.B 1 FIG.A 100 130 130 115 130 117 118 0 118 1 130 130 depicts memory systemof, but includes bold, dashed arrows to illustrate how a 64 B or 80 B cache line of data is distributed from a single flash componentF—highlighted using bold boundaries—to a rank of ten similarly highlighted DRAM componentsD. In a wide mode, modulesupports ranks of twenty DRAM componentsD; linksbetween address buffers() and() allow cache lines from one or more flash componentsF to be distributed across all twenty DRAM componentsD.

2 FIG. 1 1 FIGS.A andB 1 1 FIGS.A andB 3 FIG. 125 4 130 3 0 135 35 32 39 36 130 118 0 15 0 200 205 130 110 39 32 130 205 135 125 4 118 0 125 3 0 depicts memory slice[] ofin accordance with one embodiment. Each of DRAM componentsD includes a DRAM-component interface DQ[:] supporting a four-bit data width (the “volatile data width”) connected to data-buffer componentvia a respective one of the two secondary data link groups DQs[:] and DQs[:]. Each of flash componentsF includes a flash-component interface FQ connected to address buffer() () via multi-drop bus ADQf[:]. Component interfaces FQ and bus ADQf each support a sixteen-bit data width (the “nonvolatile data width”). Steering logicandallow DRAM componentsD to communicate data with controller, via primary data links DQp[:], or with flash componentsF via local bus DQt. Steering logicand links DQt through DB componentadditionally allow slice[] to communicate data between address buffer() and neighboring slices[:]. This functionality is detailed below in connection with.

2 FIG. 215 130 220 225 130 215 130 230 220 118 0 130 235 225 130 230 130 130 additionally shows a packaging optionfor flash componentsF and alternative packaging optionsandfor DRAM componentsD. Flash packaging optionincludes two stacks of eight flash devices, or “dies,” interconnected by e.g. through-silicon vias (TSVs). Flash componentsF are on either side of module substratein this example. DRAM packaging optionincludes two stacks of eight DRAM dies interconnected by e.g. TSVs. Address buffer() thus selects a rank of DRAM dies, one from each DRAM componentD, for each memory access. Each DRAM stack includes a master diewith data-buffer logic. In packaging option, DRAM componentsD are two-package stacks, one package on either side of module substrate. DRAM componentsD serve as cache storage for up to e.g. one sixteenth of the storage space afforded by flash componentsF. Other alternative arrangements with the same or different numbers of DRAM or nonvolatile memory dies or packages can also be used.

3 FIG. 1 FIG. 100 115 0 135 4 118 0 118 0 135 110 300 301 302 300 301 110 depicts memory systemofin a manner that emphasizes functional aspects of low-order module half(). DB component[] and address buffer() include numerous triangles suggestive of buffers and included to highlight the directions of information flow. Selection and placement of signal buffers, and the routing of signals in general, is within the ability of those of skill in the art. At the direction of address buffer() via local communication bus BCOM, each DB componentcommunicates with memory controllervia eight primary data links DQp, delivering read data to a read queueand receiving write data from a write queueinto a data buffer. Queuesandand the other elements of controllerare conventional so a detailed discussion is omitted.

118 0 330 326 327 110 328 110 118 0 119 330 335 Address buffer() manages the flow of data to and from DRAM cacheresponsive to commands and addresses from read and write queuesandof controllerand passes status information back to a status registerin controller. Address buffer() additionally maintains coherence between SRAM address cache, DRAM cache, and flash address space.

130 115 0 330 31 0 332 31 0 332 130 115 0 333 335 335 330 330 39 30 35 30 333 333 335 332 330 1 FIG.A The ten DRAM componentsD of module half() that were introduced in connection withare depicted collectively as DRAM address space, which is logically divided into thirty-two sets Set[:] of 4 KB groups. Each of sets Set[:] includes 524 KB in 4 KB groupsfor a total available DRAM address space of 64 GB for storing data. The ten flash componentsF of module half() are depicted collectively as an array of 4 KB groupsin flash address space. Flash address spacestores sixteen times as many cache lines as DRAM spaceso flash addresses are specified using four more bits than DRAM address space(AF[:] vs. AD[:]). Each of nonvolatile 4 KB groupsincludes sixty-four 64 B cache lines. The total available flash memory space is 2^40 bytes, or 1 TB. Any 4 KB groupin flash address spacecan have a corresponding 4 KB groupin DRAM address space.

118 0 330 The control logic in address buffer() can manage an arbitrary number of sets cached in DRAM, depending in part upon how much space is reserved for data. Embedding the cache tags in the “extra” part of the 80 B cache lines allows the total amount of DRAM cache space to be other than a power of two. This flexibility is useful if e.g. some DRAM address space is to be set aside for buffer space (e.g. for write aggregation) or for address mapping tables (e.g. between flash address space to the physical memory space). The size of each cache set can be an even divisor of the physical address space; both SRAM and DRAM caches will typically support a power-of-two number of cache lines. In some embodiments the Flash address space may be larger than the physical memory, leaving extra nonvolatile storage for e.g. managing erase block rotation.

330 335 31 0 330 335 330 330 In some embodiments a portion of DRAM address spaceis used to aggregate the write-back of dirty pages to flash address space. Dirty pages are moved from DRAM sets Set[:] to a write-back region to await a write-back process. Aggregating write-back operations improves speed performance because moving a 4 KB page within DRAM address spacetakes only a few hundred nanoseconds, whereas a program operation to write to flash address spacetakes tens of microseconds. Write-back aggregation can take advantage of the fact that DRAM address spacecan support a non-power-of-two number of sets even if the physical memory space it caches is a power of two, and each set has a power-of-two number of cache lines. DRAM address spacecan also be used for address mapping between DRAM and flash addresses for e.g. page rotation in support of wear leveling.

118 0 310 315 320 325 310 119 39 6 330 315 310 310 315 332 35 12 330 315 332 315 330 315 330 118 0 Address buffer() includes address-mapping logic, a dirty-group buffer, status logic, and data/address selection logic. Mapping logiccombines address bits from SRAM address cacheand controller addresses AC[:] to provide DRAM addresses for DRAM cacheand dirty-group buffer, and additionally supports control signaling for DRAM and buffer read and write access. Each time address-mapping logicwrites to a given 64 B cache line, address-mapping logicadditionally writes in bufferthe address of the 4 KB groupencompassing the 64 B, with address A being a buffer entry address and address D address bits AD[:] specifying the address field of a dirty group in DRAM address space. Bufferthus maintains a list of blocksthat include at least one dirty cache line. The aggregation of entries in bufferis later used to write dirty bits into DRAM cacheat the first cache line address in each dirty 4 KB group. Dirty-bit updates from bufferto DRAM cachecan be performed during idle times or otherwise interleaved with memory transactions to limit interference. As detailed below, these group-level dirty bits allow address buffer() to quickly find clean 4 KB groups to evict in favor of 4 KB flash groups.

4 FIG.A 3 FIG. 330 31 0 400 400 illustrates DRAM cacheof, which includes thirty-two sets Set[:] of eighty-byte (80 B) cache linesdivided into 2^19 4KB groups. Each cache lineincludes five fields, a 64 B data field to store cached data; a parity-bit field P to store a parity bit; a valid-bit field V, dirty-bit D, and DRAM tag field TagD in support of caching; and an EDC field to store error-correction and detection (EDC) bits.

110 119 330 Controllerand/or an associated processor has access to lower-level caches that manage reads and writes of 64 B cache lines. SRAM address cacheand DRAM cacheexpand cache locality to 4 KB to increase hit rates for cache lines outside the lower level caches. Assuming a paging system with 4 KB granularity, access to a 64 B cache line within a given 4 KB provides a strong likelihood of subsequent accesses to other cache lines within the same page. Different 4 KB pages can belong to different processes so cache locality tends not to extend beyond a page. The sizes of the cache lines and cached blocks can be different in other embodiments.

4 FIG.B 3 FIG. 4 FIG.A 335 400 330 39 0 115 5 0 35 31 31 0 illustrates how 64 B cache lines in flash memory spaceofmap to 80 B cache linesin DRAM memory spacein accordance with one embodiment. Controller addresses AC[:] specify 2^40 individual data bytes (1 TB). Moduledelivers 64 B cache lines so the six least-significant bits AC[:] are not used. The flash addressing accommodates up to sixty-four (2^6) flash devices in a stack, with each device having 16 KB (2^14) erase blocks. Each erase block, in turn, includes sixty-four flash pages, each with 256 (2^8) 64 B cache lines. The six byte-address bits are not used. Finally, the DRAM addressing accommodates up to eight (2^3) DRAM devices in a stack, with each device having sixteen (2^4) banks. Each DRAM bank, in turn, includes 64K (2^16) rows, each with 128 (2^7) 64 B cache lines. The five most-significant bits AD[:] distinguish the thirty-two sets Set[:] depicted in.

4 FIG.C 119 330 119 31 0 410 19 12 415 39 20 119 35 31 330 39 20 30 6 30 6 illustrates the organization of an embodiment of SRAM address cache. Like DRAM cache, SRAM address cacheis divided into thirty-two sets SetS[:]. Each set includes 256 tag locations, each of which in turn includes a twenty-bit index field ACtS and five-bit tag field TagS for a total of 204,800 bits. A decoderdecodes controller address bits AC[:] to select one row of tag locations. Logiccompares high-order address bits AC[:] with the index fields for the selected row in all thirty-two sets. In case of a match, SRAM address cacheconveys the contents of the five-bit tag field TagS of the selected row and set as DRAM address bits AD[:] to select the set within DRAM cachethat includes the requested data. In this example controller address bits AC[:] match the third row of set SetS2, which consequently delivered its five-bit tag TagS. Address bits AC[:] are passed unaltered as DRAM address bits AD[:] to select the cache line within the selected DRAM set.

5 FIG. 5 FIG. 3 FIG. 500 115 0 330 119 is a timing diagramillustrating a read access to module half() when the requested cache line is in DRAM memoryand the address of that cache line is available in SRAM address cache.and subsequent timing diagrams refer to signals and signal lines introduced in. In general, signals and their associated nodes carry the same designations. Whether a given moniker refers to a signal or a corresponding node will be clear from the context.

110 39 6 505 A read transaction begins when external controllerissues a read request over primary links CSp/CAp specifying a controller address AC[:] (). Signals involved in this sample transaction are highlighted with bold boundaries to distinguish them from interleaved transactions. Transaction pipelining increases memory throughput.

118 0 39 12 119 39 20 330 119 35 31 310 30 6 35 6 507 35 31 330 30 6 TAG Address buffer() conveys address bits AC[:] to SRAM address cache, which considers bits AC[:] over a time tto determine whether the requested data is in DRAM cache. Should a match arise, SRAM cachedelivers high-order DRAM address bits AD[:] to address-mapping logic, which concatenates these with controller address bits AC[:] to form the DRAM address AD[:] of the requested 64 B cache line (). DRAM address bits AD[:] designate the set Set[i] of the requested cache line in DRAM cacheand controller address bits AC[:] the offset within designated set Set[i].

330 510 110 118 0 515 118 0 320 520 328 110 115 505 119 118 0 BUF DRAM memory spaceresponsively delivers the addressed data () over secondary data links DQs. That data line is then sent to controllervia primary links DQp with a buffer delay timposed by address buffer() (). Address buffer() instructs status logicto issue a SRAM-hit signalto status registerto let controllerknow that the delivered read data is the requested data. Modulethus returns the requested 64 B cache line in about 30 ns from receipt of request. Thus ends the read transaction in which SRAM address cacheyields a hit. Though not shown, address buffer() can consider parity and EDC bits for error detection and correction. The use of parity and EDC bits is well understood by those of skill in the art.

6 FIG. 5 FIG. 600 115 0 330 119 110 39 6 505 39 20 119 118 0 330 310 610 330 31 0 30 6 615 620 310 118 0 320 625 328 110 625 110 is a timing diagramillustrating a read access to module half() when the requested cache line is in DRAM memoryand an address tag for that cache line is absent from SRAM address cache. As in the example of, a read transaction begins when external controllerissues a read request over primary links CSp/CAp specifying a controller address AC[:] (). This time, however, address bits AC[:] have no match in SRAM address cache. Address buffer() thus attempts to find the requested cache line entry in DRAM cache. To do so, address-mapping logicissues thirty-two successive read requeststo DRAM cache, one request for each set Set[:], by incrementing through each value of AD[35: 31] with offset AC[:]. Each read request returns a cache linewith a DRAM tag, the latter of which is conveyed to address-mapping logicvia connection Qt. Address buffer() instructs status logicto issue a miss signalto status registerfor each of these reads so that controllerignores these read data. For the final DRAM miss, the miss signalcan indicate to controllerthe need for a flash access.

330 615 RCD RD DSi DSi DRAM memorycan be organized such that each read in the sequence of thirty-two reads is directed to a successive bank so that each bank has time to complete a row cycle before the subsequent access. In this example, read datafirst appears after a 10 ns row-to-column read delay tand 15 ns read delay t. Accesses are pipelined such that each additional cache line requires an additional 2.5 ns. All thirty-two reads are therefore accomplished over a time tof 80 ns. DRAM read accesses can be halted responsive to a tag hit, so the average time twill be closer to 40 ns for a DRAM cache hit.

620 39 20 118 0 119 119 505 110 118 0 115 505 505 119 330 5 FIG. Should one of the thirty-two tagsmatch address bits AC[:]—a DRAM cache hit—then address buffer() updates SRAM address cachewith the address and tag information for the requested cache line. The updated set and line in SRAM address cachecan be selected at random, though other replacement policies might be used. A retry of requestfrom controllerwill then result in a SRAM cache hit and the delivery of the requested cache line in the manner detailed in connection with. In other embodiments the requested cache line is retained in address buffer() to hasten cache line delivery responsive to the retry. Modulereturns the requested 64 B cache line in about 150 ns from receipt of the first instance of request. Other transactions can be pipelined between the first instance of requestand the retry to take advantage of available data bandwidth. Thus ends the read transaction in which SRAM address cacheyields a miss and DRAM cachea hit.

7 FIG. 700 115 0 330 119 333 335 330 is a timing diagramillustrating a read access to module half() when the requested cache line is absent DRAM memoryand the address of that cache line is absent from SRAM address cache. This presents the worst case from a read-latency perspective because a relatively large 4 KB groupof data is moved from the relatively slow flash address spaceinto DRAM cache, a process that takes about 3.5 us.

118 0 330 310 710 330 31 0 35 31 30 12 505 11 6 715 720 310 118 0 320 725 328 110 720 332 333 335 332 315 Address buffer() chooses a clean entry in DRAM cache. To do so, address-mapping logicissues thirty-two successive read requeststo DRAM cache, one request for each set Set[:], by incrementing through each value of AD[:] with offset by bits AC[:] of the original requestand bits AC[:]=000000 b. Each read request returns a cache linewith a DRAM dirty bit, the latter of which is conveyed to address-mapping logicvia connection Qt. Address buffer() instructs status logicto issue a miss signalto status registerfor each of these reads so that controllerignores these read data, and considers dirty bitsto identify a clean 4 KB group (i.e., a 4 KB groupwithout any overwritten cache lines) to be evicted in favor of a new 4 KB groupfrom flash address space. As noted previously, the first cache line of each 4 KB groupwith at least one dirty cache line is tagged “dirty” using data accumulated in bufferduring cache line writes.

332 118 0 730 335 15 0 118 0 735 335 119 740 118 0 735 330 745 39 0 750 110 505 110 118 0 110 330 335 RDF TRF While searching for a clean 4 KB group, address buffer() conveys the flash addressof the requested data to flash address spaceover bus ADQf[:]. After a flash-read delay t, address buffer() receives the requested 4 KB blockfrom flash address spaceover a time period t, updates SRAM address cache. Using a series of local write commands, address buffer() writes the 4 KB blockto DRAM memoryas a series of dataon local data buses DQs[:] and conveys a status signalto controllerto instigate a retry for the requested cache line. Thereafter a retry of requestfrom controllerwill result in an SRAM cache hit and the delivery of the requested cache line will proceed as noted previously. In some embodiments, address buffer() allows a retry from controllerwhen the requested cache line is available and before the entire 4 KB block is cached in DRAM memory. If flash address spaceallows reordering of read data, the requested cache line can be provided first with the conveyance of all sixty-four cache lines of a 4 KB group.

118 0 332 330 332 333 335 Address buffer() can maintain a counter (not shown) recording the number of clean 4 KB blocksin DRAM cache. Should the number fall below a threshold, one or more of the 4 KB blocksmay be overwritten by a blockfrom flash address space. Such write-back processes can be scheduled to take place during idle periods.

8 FIG. 800 115 0 330 119 110 805 39 6 118 0 39 12 119 39 20 330 119 35 31 310 30 6 35 6 35 31 30 6 TAG is a timing diagramillustrating a write access to module half() when the requested cache line is in DRAM memoryand the address of that cache line is available in SRAM address cache. A write transaction begins when external controllerissues a write requestover primary links CSp/CAp specifying a controller address AC[:]. Address buffer() conveys address bits AC[:] to SRAM address cache, which considers bits AC[:] over ttTAG to determine whether the requested data is in DRAM cache. Should a match arise, SRAM address cachedelivers high-order DRAM address bits AD[:] to address-mapping logic, which concatenates these with controller address bits AC[:] to form the DRAM address AD[:] of the requested 64 B cache line. DRAM address bits AD[:] designate the set and controller address bits AC[:] the offset within the set of the requested cache line. Accesses are fully pipelined.

110 815 805 39 0 118 0 820 330 39 0 118 0 210 315 35 12 330 335 330 118 0 320 825 328 110 BUF Controllerconveys write datatimed to requeston primary data lines DQp[:]. Address buffer() responsively conveys the write data with valid and dirty bits () to DRAM memory spacevia secondary data line DQs[:] after a buffer delay t. If supported, address buffer() additionally calculates parity and EDC bits for storage with the write data. Address logicupdates bufferto include address bits AD[:] of the 4 KB group associated with the dirty cache line in DRAM cache. As noted previously, this information supports a block eviction process for loading blocks from flash address spaceto DRAM cache. Address buffer() instructs status logicto issue a SRAM-hit signalto status registerto report the successful write to controller.

112 While the subject matter has been described in connection with specific embodiments, other embodiments are also envisioned. Other variations will be evident to those of skill in the art. Therefore, the spirit and scope of the appended claims should not be limited to the foregoing description. Only those claims specifically reciting “means for” or “step for” should be construed in the manner required under the sixth paragraph of 35 U.S.C. §.