Image Sensor for Event Detection

The present disclosure relates to an image sensor and a solid-state imaging device. More particularly, the present disclosure relates to the field of event detection sensors that respond to changes in light intensity, such as dynamic vision sensors (DVS) and event-based vision sensors (EVS) with continuous, asynchronous detection of events.

Event detection image sensors like DVS and EVS deliver information only about the position of changes in the imaged scene. Unlike image sensors that transfer large amounts of image information in frames, transfer of information about pixels that do not change can be omitted, resulting in a sort of in-pixel data compression. The in-pixel data compression removes data redundancy and facilitates high temporal resolution, low latency, low power consumption, high dynamic range, and little motion blur.

Each DVS or EVS pixel temporarily stores an event indicating an increase or a decrease in detected light intensity compared to a previous readout until the next time the pixel is read out. Each readout of a pixel clears the event.

In image sensors for synchronous event detection, a readout circuit reads out a pixel array row by row.

In image sensors for continuous, asynchronous event detection, each pixel that detects an event indicates the event by outputting a request signal to a readout circuit. In the readout circuit, the request signal triggers the compilation of event information. The event information includes the pixel address identifying the position of the pixel in the pixel array, the sign of the change in light intensity, and a time stamp. The readout circuit passes the event information to an image processor and confirms to the pixel that it has received the event. Upon receiving the confirmation, the pixel deletes the event.

Clearing the event typically includes an automatic zeroing process (“autozero process”, “autozeroing”) that resets a voltage in an input path of a comparator stage to an initial value.

For the duration of the autozero process, the pixel is unable to process another event. The autozero process thus defines a dead time for which a previously read pixel is blocked before it can detect the next event. The dead time is sensitive to manufacturing-related deviations between the pixels of a pixel array and is therefore pixel-specific.

The present technology has been made in view of this situation and aims to improve sensing performance of an image sensor for asynchronous event detection.

In this regard, the present disclosure relates to an image sensor having a pixel array that includes pixel circuits. Each pixel circuit is configured to output a request signal in response to a predefined change in illumination. Each pixel circuit includes a floating node configured to temporally store charge as a function of a change of an illumination condition, and a reset switch configured to set a potential of the floating node to a predefined initial potential in response to a reset ramp signal. The image sensor further includes a ramp signal circuit configured to output the reset ramp signal for at least a first group of the pixel circuits. The first group includes more than one pixel circuit.

The ramp signal circuit is shared by at least one group of pixel circuits and may be formed in a peripheral portion of the image sensor and/or in a signal processing layer. The ramp signal circuit(s) can be realized outside the pixel array, and thus with fewer area constraints. Dead time deviations between pixel circuits receiving the reset ramp signals from multiple ramp signal circuits are smaller than for the case where each pixel circuit contains an own ramp signal circuit.

For asynchronous image sensors with separate ramp signal circuits in each pixel circuit, the dead time is usually extended to such an extent that the effects of manufacturing-related deviations between individual pixels are reduced with respect to the response to the autozero process. The dead time can be up to hundreds of microseconds, and each pixel circuit requires a bias source and an appropriately sized capacitor to generate the reset ramp signal. In this respect, the asynchronous image sensor with shared ramp signal circuit according to the present embodiments allows for shorter dead times and shows smaller dead time variations. Time resolution can be increased and thus the sensing performance improved.

The described embodiments, together with further advantages, will be best understood by reference to the following detailed description taken in conjunction with the accompanying drawings.

Embodiments for implementing techniques of the present disclosure will be described below in detail using the drawings. The techniques of the present disclosure are not limited to the described embodiments, and various numerical values and the like in the embodiments are illustrative only. The same elements and elements with the same functions are denoted by the same reference signs. Duplicate descriptions are omitted.

Connected electronic elements may be electrically connected through a direct and permanent low-resistive connection, e.g., through a conductive line. The terms “electrically connected” and “signal-connected” may also include a connection through other electronic elements provided and suitable for permanent and/or temporary signal transmission and/or transmission of energy. For example, electronic elements may be electrically connected or signal-connected through resistors, capacitors, and electronic switches such as transistors or transistor circuits, e.g., MOSFETs, transmission gates, and others.

The load path of a transistor is the controlled path of a transistor. For example, a voltage applied to the gate of a field effect transistor (FET) controls the current flow through the load path between source and drain of the FET by field effect.

1 FIG. 1 91 90 92 93 91 90 In, an imaging apparatusincludes an optical system, a solid-state imaging device, a storage unit, and a control unit. The optical systemincludes one or more lenses and various mechanisms such as an autofocus mechanism and a diaphragm mechanism, and guides light from an object to a light receiving surface of the solid-state imaging device.

90 90 The solid-state imaging deviceincludes an image sensor having a plurality of pixel circuits. Each pixel circuit includes a radiation sensitive element that converts incident radiation into electric signals by photoelectric conversion, and outputs the electric signals. The solid-state imaging devicefurther includes a signal processing unit that performs predetermined signal processing on the electric signals output from the pixel circuits and outputs image data based on the electric signals.

92 90 The storage unitstores the image data output from the solid-state imaging devicein a storage medium. The storage medium may include a volatile storage medium and/or non-volatile storage medium. The non-volatile storage medium may be or include a flash memory or a hard disk drive. The non-volatile storage medium may be or include a dynamic random access memory (DRAM).

93 90 90 The control unitcontrols the solid-state imaging device, such that the solid-state imaging deviceperforms an imaging operation. The imaging operation includes capturing an image of an object or a scene and outputting image data including image information about the object or the scene.

2 FIG. 90 80 90 80 60 80 10 20 30 40 50 is a block diagram illustrating a configuration of an example of a solid-state imaging devicewith an image sensorapplicable to the embodiments. The solid-state imaging deviceincludes the image sensorand a signal processing unit. The image sensorincludes a pixel array, a ramp signal circuit, a row arbiter, a column readout circuit, and a sensor control circuit.

10 100 100 100 2 FIG. 2 FIG. In the pixel array, a plurality of pixel circuitsis arrayed in a two-dimensional matrix in pixel rows and pixel columns. For simplicity, pixel circuitsbelonging to the same pixel row are arranged along a horizontal line in, and pixel circuitsbelonging to the same pixel column are arranged along a vertical line in.

100 100 Each pixel circuitincludes a radiation sensitive circuit, an event detection circuit, and a pixel logic circuit. The radiation sensitive circuit outputs a voltage corresponding to the intensity of received radiation. The event detection circuit detects an event based on the magnitude of changes in the voltage received from the radiation sensitive circuit. The event detection circuit is resettable to an initial state by temporarily turning on a reset switch. The pixel logic circuit controls the output of event data from the pixel circuitand the autozeroing of the event detection circuit.

41 The event data may indicate that the intensity of received radiation has decreased by more than a certain value compared to the previous event readout (“OFF event”). Alternatively, the event data may indicate that the intensity of received radiation has risen by more than a certain magnitude compared to the magnitude at the previous event readout (“ON event”). The event data is transmitted on an event data bus.

31 100 30 31 100 30 31 100 30 31 30 100 Control busesconnect the pixel circuitswith the row arbiter. Each control busconnects the pixel circuitsof one group with the row arbiter. Each control busmay include a request line for transmitting request signals from the pixel circuitsof the pixel group to the row arbiter. The control busmay include an acknowledgement line for transmitting a group select signal from the row arbiterto the pixel circuitsof the pixel group.

100 100 30 31 For each pixel circuitdetecting an event, the pixel logic circuit of the concerned pixel circuitoutputs a request to the row arbiterthrough the control bus. For transmitting the request, a request signal transmitted on the request signal line has an active level.

30 100 10 30 31 40 The row arbiterperforms arbitration according to the pending active requests output from the pixel circuitsof the pixel array. The row arbiterselects a request received from a specific pixel group and confirms the request by outputting a confirmation on the control busand transmits the corresponding row address to the column readout circuit. For transmitting the confirmation, a group select signal transmitted on an acknowledgement signal line has an active level.

100 41 100 100 In response to the confirmation, all pixel circuitsin which an event has been detected, apply the event data on the respective event data bus. Each event data bus may be connected to some or all pixel circuitsof a same pixel column, or to all pixel circuitsof more than one pixel column.

41 41 42 43 42 43 The event data busmay include a shared data line for transmitting the ON events and the OFF events by different signal levels or in a time multiplex scheme. In the illustrated embodiment, the event data busincludes a first data linefor transmitting the ON events and a second data linefor transmitting the OFF events. For transmitting an ON event, an ON event signal transmitted on the first data linehas an active level. For transmitting an OFF event, an OFF event signal transmitted on the second data linehas an active level.

40 100 41 41 40 40 60 The column readout circuitreceives the event data from all pixel circuitsof the selected pixel group via the event data bus, and the row address(es) of the selected pixel group from which the received event data originates. From the row address and identifiers of the event data busestransmitting event data, the column readout circuitcompiles a digital address event representation AER for each event. The AER includes the row address, a column address derived from the identifiers of the event data busses transmitting events, the event data, and, if applicable, a time stamp. The column readout circuitoutputs the AERs to the signal processing unit.

20 100 100 100 100 21 21 20 100 The ramp signal circuitoutputs at least one reset ramp signal REFR and transmits the reset ramp signal REFR via a ramp control bus to a group of pixel circuits, e.g., to some or all pixel circuitsof a pixel row or to the pixel circuitsof more than one pixel row. For each pixel circuit, the pixel logic circuit controls a reset of the event detection circuit by letting pass the reset ramp signal REFR to a gate of the reset switch only when predefined conditions are fulfilled. The ramp control busincludes at least a ramp signal line for transmitting the reset ramp signal. The ramp control busmay include further lines for transmitting further control signals from the ramp signal circuitto the pixel circuits.

50 20 40 60 The sensor control circuitmay control a timing of the ramp signal circuitand/or a communication between the column readout circuitand the signal processing unit.

60 60 60 92 1 FIG. The signal processing unitreceives the AERs. The signal processing unitmay execute signal processing such as image recognition processing based on the received AERs. The signal processing unitmay output processed image data, e.g., to the storage unitofand/or through a wired or wireless electronic interface.

10 100 80 By providing the reset ramp signal REFR from a single source outside the pixel arrayto a plurality of pixel circuitselectrically connected for outputting requests, the image sensorprovides an asynchronous readout which can be operated with comparatively short dead times.

90 90 2 FIG. The solid-state imaging devicea described with reference tocan be provided as, for example, a stacked contact image sensor (CIS) formed by stacking a plurality of semiconductor chips. As an example, the solid-state imaging devicea can be formed by a two-layer structure in which semiconductor chips are stacked in two layers.

3 FIG. 2 FIG. 3 FIG. 90 910 920 910 920 100 90 910 920 is a diagram illustrating an example in which the solid-state imaging deviceofis formed by a stacked CIS having a two-layer structure with a radiation receiving chipand a processing chip. The radiation receiving chipincludes at least the radiation sensitive elements, e.g., the complete radiation sensitive circuit, or the complete radiation sensitive circuit and further elements of the pixel circuits. The processing chipincludes the further elements of the pixel circuits, e.g., the event detection circuit and the pixel logic circuit. As illustrated on a right side of, the solid-state imaging deviceis formed as one sensor by bonding the first-layer semiconductor chip and the second-layer semiconductor chip while electrically bringing contact pads on the radiation receiving chipin contact with corresponding contact pads on the processing chip.

4 FIG. 10 20 10 100 100 100 121 126 121 20 100 shows an image sensor that includes a pixel arrayand a ramp signal circuit. The pixel arrayincludes pixel circuits. Each pixel circuitoutputs a request signal REQ in response to a predefined change in illumination. Each pixel circuitincludes a floating nodeconfigured to temporally store charge as a function of a change of an illumination condition, and a reset switchconfigured to set the floating nodeto a predefined initial potential in response to a reset ramp signal REFR. The ramp signal circuitoutputs the reset ramp signal REFR for at least a first group of the pixel circuits.

100 32 121 The pixel circuitsoutput the request signal REQ on request signal lines. A resulting voltage of the floating nodeis a function of a change in illumination intensity. The change in illumination is the difference in light intensity between a current time and a previous time.

121 100 100 121 121 126 121 126 121 10 121 The amount of charge stored on the floating nodecorresponds to a change in brightness detected by the pixel circuitbetween the currently detected brightness and a brightness evaluated at a previous point in time, e.g., at a preceding readout of the pixel circuit. The predefined change in brightness corresponds to a predefined amount of charge stored on the floating nodeand to a predefined voltage between the floating nodeand a reference potential VSS. The reset switchswitches the floating nodeto the predefined initial potential during an autozero period. For example, the reset switchmay temporarily connect the floating nodeto a predefined potential, e.g., to the reference potential VSS of the pixel arrayor may temporarily short-circuit a feedback element of an amplifier circuit whose input is connected to the floating node.

121 121 121 126 126 121 The process of initializing the potential at the floating nodewill be referred to as autozero process in the following for ease of reading. The autozero process includes a partial or complete discharge of the floating node. When the potential at the floating nodehas reached the initial potential, the recess switchturns off. Turning off the recess switchtoo fast may cause significant charge injection into the floating node.

126 126 126 126 126 100 100 20 50 93 93 50 2 FIG. 1 FIG. Applying a comparatively slowly changing reset ramp signal to the gate of the recess switchto turn off the recess switchavoids turning off the recess switchtoo fast and mitigates resulting issues. If the recess switchis an n channel FET controlled by a reset ramp signal REFR changing between an inactive low level and an active high level, the recess switchturns on with a leading edge in the recess ramp signal REFR and turns off with the trailing edge in the recess ramp signal REFR. The trailing edge of the reset ramp signal REFR is significantly shallower (less steep) and falls or rises at a significantly lower rate, e.g., by at least one order of magnitude slower than other signals controlling the pixel circuitor output by the pixel circuit. For example, the trailing edge of the reset ramp signal REFR can be significantly shallower and can fall or rise at a significantly lower rate, e.g., by at least one order of magnitude slower than the leading edge of the reset ramp signal REFR rises. For example, the trailing edge of the reset ramp signal REFR might take a few microseconds, corresponding to a slope in the range of 0.1V/μs to 1V/μs. The leading edge of the reset ramp signal REFR and/or other control signals typically take 100 ns or less for a transition. The slope of the trailing edge may be fixed. Alternatively, the slope may be programmable. For example, the ramp signal circuitincludes a register whose output(s) affect the slope of the ramp, wherein the register can be set by the sensor control circuitofand/or by the control unitof. The control unitand/or the sensor control circuitmay change the register setting in response to a change in user setting, sensor internal conditions and/or illumination conditions.

20 10 20 100 100 10 100 100 100 100 100 10 The ramp signal circuitgenerates the reset ramp signal REFR with the shallow trailing edge and applies the reset ramp signal REFR to the pixel array. An output of the ramp signal circuitis electrically connected to each of the pixel circuitsof a first group of pixel circuitsin the pixel array. The first group of pixel circuitsmay include some or all pixel circuitsof one pixel row, some or all pixel circuitsof a plurality of neighboring pixel rows, some or all pixel circuitsof a plurality of not neighboring pixel rows, or all pixel circuitsof the pixel array.

100 100 Between the pixel circuitsof the same group no mismatches occur with respect to the length of the autozero period. Otherwise, such mismatch must be accounted for by a suitable safety margin for the length of the autozero period to ensure that each pixel circuitis properly reset after each event. With the embodiments, such a safety margin becomes obsolete or can be significantly reduced. A dead time during which the pixel circuit does not detect illumination changes can be reduced accordingly.

100 100 126 100 121 121 The pixel circuitsmay be configured such that for each pixel circuit, the reset ramp signal REFR is passed to the reset switchonly for a period of time after detection of a predefined change in illumination in the pixel circuitand before and end of setting the initial potential at the floating node, e.g., from a detection of a predefined change in illumination until an end of setting the initial potential at the floating node.

100 100 126 126 121 A pixel circuitis only reset under the condition that the pixel circuithas detected and output an event since the last readout. For example, the reset switchmay be or include an FET. An analog switch may pass the reset ramp signal REFR to a gate of the reset switchonly for the period of time from the detection of a predefined change in illumination to the setting of the initial potential at the floating node.

100 150 126 150 150 150 100 More particularly, each pixel circuitmay include an autozero enable switchfor temporarily disconnecting the gate of the reset switchfrom the reset ramp signal REFR. An autozero signal AZ controls the autozero enable switch. The autozero signal AZ may be a binary signal changing between an active level and an inactive level. The active level turns on the autozero enable switch. The inactive level turns off the autozero enable switch. The autozero signal AZ may image an internal state of the pixel circuitand allows a conditional autozero process.

150 100 150 The autozero signal AZ may be active and the autozero enable switchmay be on during a period from the output of an event by the pixel circuitto the end of the autozero period. During the rest of the time, the autozero signal AZ can be inactive and the autozero enable switchcan be off.

5 FIG. 2 FIG. 100 80 shows a block diagram of a pixel circuitfor an asynchronous image sensoras illustrated in.

110 120 130 120 130 140 A radiation sensitive circuitoutputs a pixel voltage signal VPR proportional to incoming light intensity. An event detection circuit includes a capacitive amplifier circuitand a pixel comparator circuit. The capacitive amplifier circuitgenerates an amplified voltage signal VBF. The pixel comparator circuitcompares the amplified voltage signal VBF with an upper reference voltage VTH and a lower reference voltage VTL. A pixel logic circuitoutputs pixel event signals ON, OFF based on a result of comparisons of the amplified voltage signal VBF with the upper reference voltage VTH and the lower reference voltage VTL.

110 111 111 The radiation sensitive circuitincludes a photoelectric conversion elementand outputs the pixel voltage signal VPR. A voltage level of the pixel voltage signal VPR depends on a photodetector current generated by the photoelectric conversion element.

110 111 112 111 More particularly, the radiation sensitive circuitincludes the photoelectric conversion elementand a photoreceptor circuit. The photoelectric conversion elementmay include or consist of a photodiode which by means of the photoelectric effect converts electromagnetic radiation incident on a detection surface into a photodetector current. The electromagnetic radiation may include visible light, infrared radiation and/or ultraviolet radiation. The amplitude of the photodetector current corresponds to the intensity of the incident electromagnetic radiation, wherein in the intensity range of interest the detector current increases approximately linearly with increasing intensity of the detected electromagnetic radiation.

112 The photoreceptor circuitconverts the photodetector current into the pixel voltage signal VPR. The voltage of the pixel voltage signal VPR is a function of the photodetector current, wherein in the voltage range of interest the voltage amplitude of the current photoreceptor signal VPR increases with increasing photodetector current. For example, the voltage of the pixel voltage signal VPR increases with the photodetector current logarithmically.

120 By subtracting a previously evaluated photoreceptor voltage VPT from the current pixel voltage signal VPR, the capacitive amplifier circuitobtains a floating voltage VSF. The amplified voltage signal VBF represents an amplified difference between the previously evaluated photoreceptor voltage VPT and the present voltage of the pixel voltage signal VPR.

130 120 The pixel comparator circuitreceives the amplified voltage signal VBF from the capacitive amplifier circuitand compares the amplified voltage signal VBF with the upper reference voltage VTH and the lower reference voltage VTL.

130 131 132 123 In the illustrated embodiment, the pixel comparator circuitincludes two comparators,for simultaneously comparing the output signal of the amplifier circuitwith the upper voltage threshold VTH and the lower voltage threshold VTL.

131 1 131 120 132 2 132 120 The first comparatoroutputs a first comparator output signal VCchanging between an active level and an inactive level. The first comparatoroutputs an active level (active first comparator output signal) only when the output signal of the capacitive amplifier circuitexceeds the upper voltage threshold VTH. The second comparatoroutputs a binary second comparator output signal VCchanging between an active level and an inactive level. The second comparatoroutputs an active level (active first comparator output signal) only when the output signal of the capacitive amplifier circuitfalls below the lower voltage threshold VTL.

130 120 120 According to another example, the pixel comparator circuitincludes a three-level comparator that outputs a combined comparator output signal changing between two different active levels and an inactive level. The three-level comparator outputs a first active level when the amplified voltage signal VBF received from the capacitive amplifier circuitexceeds the upper voltage threshold VTH, a second active level when the output signal of the capacitive amplifier circuitfalls below the lower voltage threshold VTL, and the inactive level otherwise.

130 According to another example, the pixel comparator circuitincludes one single comparator successively comparing the amplified voltage signal VBF with the upper voltage threshold VTH and the lower voltage threshold VTL. The single comparator outputs an active level in a first phase, when the amplified voltage signal VBF exceeds the upper voltage threshold VTH, an active level in a subsequent second phase, when the amplified voltage signal VBF falls below the lower voltage threshold VTL, and the inactive level otherwise.

140 130 10 140 30 140 100 2 FIG. The pixel logic circuitreceives the comparator output signals from the pixel comparator circuitand control signals from outside the pixel array. Based on the comparator output signals, the pixel logic circuitgenerates and outputs a request signal REQ for registering an event read out through the row arbiterof. The pixel logic circuitoutputs the request signal REQ through a request signal output RQO to a request signal line. The request signal output RQO may be an open collector output or any other output type allowing a plurality of pixel circuitsto be connected to the same request signal line.

140 140 150 100 150 121 2 FIG. The pixel logic circuitgenerates event data signals EVP, EVN on the basis of the comparator output signals and transmits the event data signals EVP, EVN in response to an active acknowledgement signal ACK received through an acknowledgement input ACI to the column readout circuit of. Further on the basis of the comparator output signals, the pixel logic circuitgenerates an active signal AZ and outputs an active autozero signal to the autozero enable switchin response to a received acknowledgement signal ACK, provided that the pixel circuithas detected an event since the last read out. The active autozero signal turns on the autozero enable switchfor the autozero period such that the voltage at the floating nodecan be reset to the initial voltage with the next active ramp signal.

6 FIG. 80 shows an embodiment with an image sensorusing a global reset ramp signal REFR.

30 100 100 The row arbiteroutputs a group select signal SEL<x> to a first group of the pixel circuitsin response to a group request signal REQ <x> received from any of the pixel circuitsof the first group.

100 100 100 100 Each group of pixel circuitsmay include some or all pixel circuitsof one pixel row, or some or all pixel circuitsof more than one pixel row. In the illustrated embodiment, each pixel group includes all pixel circuitsof the same pixel row.

100 100 In response to the group select signal SEL<x>, each pixel circuitof the selected group of pixel circuitshaving detected an event outputs event data and initiates autozeroing.

20 100 10 The ramp signal circuitis configured to output the reset ramp signal REFR for each pixel circuitof the pixel array.

20 100 20 10 20 100 The ramp signal circuitoutputs a single reset ramp signal REFR. Each pixel circuitreceives the same reset ramp signal REFR or a signal derived from the same reset ramp signal REFR. The ramp signal circuitmay include buffers (not illustrated) to distribute the reset ramp signal REFR across the pixel array. For example, the ramp signal circuitmay include a buffer circuit for each n pixel rows, e.g., one row buffer circuit for each single pixel row. All row buffer circuits receive the same original reset ramp signal and each pixel circuitof a pixel row receives a buffered reset ramp signal from the row buffer circuit.

20 100 10 10 The ramp signal circuittransmits the same reset ramp signal REFR to all pixel circuitsof the pixel arrayso that no mismatch occurs between the pixel circuits of the pixel arraywith respect to the length of the autozero period.

20 The ramp signal circuitmay be configured to output the reset ramp signal REFR at regular time intervals.

20 10 30 20 30 31 100 The reset ramp signal REFR is a periodic signal. The regular time intervals have the same length. The ramp signal circuitmay operate asynchronous with respect to control signals output by the pixel arrayand the row arbiter. Alternatively, the ramp signal circuitand the row arbitermay share a common clock signal or a common source for a clock signal for control signals transmitted on the control busesto the pixel circuits.

7 FIG. 6 FIG. 6 FIG. 6 FIG. 100 126 126 126 shows two periods of a global reset ramp signal REFR. One period of the reset ramp signal REFR defines an autozero interval with an interval length trmp. Each pixel circuitapplies the reset ramp signal REFR to the gate of reset switchof. Within each autozero interval, the reset ramp signal REFR changes once between a low level and a high level and once between the high level and the low level. The leading edge turns on the reset switchofand may be comparatively steep. The reset ramp signal REFR may maintain the reached level for some time. The trailing edge is typically less steep than the leading edge and turns off the reset switchof.

126 126 100 100 6 FIG. 6 FIG. In the illustrated embodiment, the reset switchofis an NFET (n channel field effect transistor). The leading edge of the reset ramp signal REFR is a rising edge, and the trailing edge is a falling edge. If the reset switchofis a PFET (p channel field effect transistor), the leading edge of the reset ramp signal REFR can be a falling edge, and the trailing edge a rising edge. The reset ramp signal REFR reaches the low level and remains at the low level for the rest of the autozero interval. The trailing edge changes at a significantly lower rate, e.g., by at least one order of magnitude slower than other signals controlling the pixel circuitor output by the pixel circuit. For example, the trailing edge of the reset ramp signal REFR can be significantly shallower and can change at a significantly lower rate, e.g., by at least one order of magnitude slower than the leading edge.

100 32 32 7 FIG. Within each pixel row x, the first pixel circuitdetecting an event sets the row request signal REQ<x> on a request signal lineto an active level. The active level is the low level if the request signal lineis terminated with a pull-up construction. In, the high level represents the active level for better legibility.

30 33 32 33 100 6 FIG. The row arbiterofselects one of the pixel rows with active request for readout and triggers the readout of the selected pixel row by setting a group select signal SEL<x> to an active level. In this case, the group select signal SEL<x> is a row select signal. The acknowledgement signal is transmitted on an acknowledgement signal linefor each pixel row. In the illustrated embodiment, the active level is the high level. The signals on the request signal lineand the acknowledgement signal lineare asynchronous with respect to the reset ramp signal REFR. All pixel circuitsof the selected pixel row that have detected an event are read out synchronously.

8 FIG. 5 FIG. 100 100 110 120 130 shows details of a configuration example of a pixel circuitfor an image sensor using a global reset ramp signal REFR. The pixel circuitincludes a radiation sensitive circuit, a capacitive amplifier circuitand a pixel comparator circuitoutputting pixel event signals ON, OFF as described with reference to.

100 180 Each of the pixel circuitsincludes a reset latch circuitconfigured to suppress an output of the request signal REQ for a period starting after information about the predefined change in illumination has been read out until an end of a following complete period of the reset ramp signal REFR.

180 140 4 FIG. 5 FIG. The reset latch circuitis part of the pixel logic circuitas described with reference toand. A period of the reset ramp signal REFR includes a transition from the inactive level to the active level and a following transition from the active level to the inactive level. The following complete period may be the next complete period when only a low number of pixel rows detects events per autozero interval. The following complete period may be another period when a high number of pixel rows detects events per autozero interval.

100 100 41 121 100 126 100 180 31 21 That is, after detecting an event, the pixel circuitrequests a readout. Upon receiving a confirmation from the row arbiter, the pixel circuitoutputs the ON signal or the OFF signal on the event data busand then waits until the reset of the floating nodeto the initial potential has been completed. To this purpose, the pixel circuitapplies the reset ramp signal REFR to the gate of the reset switchfor the next complete period of the reset ramp signal REFR or for another following period of the reset ramp signal REFR. The waiting time ends with the end of the period of the reset ramp signal REFR. Starting with the end of the waiting time, the pixel circuitcan request the next readout. For the temporary suppression of outputting the request signal, the reset latch circuitmay receive further control signals through the control busand/or through the ramp control bus.

180 The reset latch circuitmay also be configured to suppress a further output of event data for the period starting after information about the predefined change in illumination has been read out until the end of the following complete period of the reset ramp signal REFR. The following complete period may be the next complete period or another one of the following periods.

130 191 191 42 130 192 192 43 193 180 193 For example, a first output of the pixel comparator circuitoutputs an ON signal indicating an ON event and controlling a first output switch. A controlled path of the first output switchis between the first data signal lineand a common data node. A second output of the pixel comparator circuitoutputs an OFF signal indicating an OFF event and controlling a second output switch. A controlled path of the second output switchis between the second data signal lineand the common data node. The row select signal SEL<x> controls a third output switchwith a controlled path between the common data node and a reference potential VSS. The reset latch circuitmay temporarily suppress the output of event data by interrupting a connection between the third output switchand the reference potential VSS.

180 100 100 In particular, the reset latch circuitmay be configured to output a read done signal RDDN indicating that the pixel circuithas detected a predefined change in illumination, and that information about the predefined change in illumination has been read out from the pixel circuit.

The read done signal RDDN can be used to suppress the output of the request signal REQ and/or to generate a further signal indicating the autozero period.

180 100 In addition, the reset latch circuitmay be configured to output an autozero signal AZ indicating start and end of a complete period of the reset ramp signal REFR following the detection of a predefined change in illumination the pixel circuit.

126 100 100 100 Start and end of the active autozero signal AZ define the autozero interval. The reset ramp signal REFR is applied to the gate of the reset switchfrom the start of the autozero interval until the end of the autozero interval. The autozero signal AZ can be used to suppress the output of the request signal for the autozero interval and/or to suppress the output of the event data ON, OFF for the autozero interval. In other words, once a pixel circuithas detected an event by detecting a predefined change in illumination and has been read out, the read done signal RDDN and the autozero signal AZ can be used to prevent the pixel circuitfrom outputting an active request signal in a period starting with the pixel readout and ending at the end of the autozero interval used for autozeroing the pixel circuit.

9 FIG. 180 100 100 In, the reset latch circuitreceives a latch signal LAT and a reset latch signal RLAT to generate the read done signal RDDN and the autozero signal AZ. An active level of the reset latch signal RLAT follows an active level of the latch signal LAT. The leading edge of the reset ramp signal REFR follows the active reset latch signal RLAT. The latch signal LAT and the reset latch signal RLAT may be global signals applied to all pixel circuitssynchronously. Alternatively, the reset latch signal RLAT may be obtained by delaying the latch signal LAT in each pixel circuit.

21 31 23 The ramp control busor the control bustransmits the latch signal LAT on a latch signal lineand the reset latch signal RLAT on a reset latch signal line. The latch signal LAT and the reset latch signal RLAT are synchronous with respect to the reset ramp signal REFR.

7 FIG. 0 1 1 2 2 3 4 0 0 Referring again to, the latch signal LAT may be active between t=tand t=t. The reset latch signal RLAT becomes active later than the latch signal LAT, e.g., between t=tand t=t. The leading edge of the reset ramp signal REFR is not before t=t. The trailing edge starts at t=tand ends at t=t. The autozero interval starts at t=tand ends at t-tof the next autozero interval.

9 FIG. 180 181 Referring again to, the reset latch circuitgenerates an event signal EVT indicating that either an ON event or an OFF event is detected. For example, an OR gatemay combine the ON signal and the OFF signal to the event signal EVT.

180 182 42 43 182 100 100 184 182 The reset latch circuitincludes an edge sensitive (clocked) master-slave FF (flipflop)with a set input S, a reset input R, a clock input, and a non-inverting output Q. The event signal EVT indicates a predefined increase or decrease in illumination and is applied to the set input S. A row select signal SEL<x> is applied to the clock input. At the same time, the row select signal SEL<x> enables the output of the event data on the event data lines,. At the non-inverting output, the master-slave FFoutputs a read done signal RDDN. The read done signal RDDN changes between an inactive state and an active state. The active state of the read done signal RDDN indicates that the pixel circuithas received the row select signal ACK<x> and that the pixel circuithad detected an event before it has received the row select signal ACK<x>, and that the autozeroing has not yet ended. An invertergenerates the inverted read done signal XRDN by inverting the read done signal RDDN. Alternatively, the inverted read done signal may come from an inverting output of maser-slave FF.

180 183 183 183 183 The reset latch circuitmay further include a level-sensitive D-FFwith a data input D, a clock input, a non-inverting output Q and/or an inverting output/Q. The level-sensitive D-FFis controlled by the voltage level at the clock input. The read done signal RDDN is applied to the data input D. The latch signal LAT is applied to the clock input. The D-FFoutputs an autozero signal AZ at the non-inverting output Q. The D-FFoutputs an inverted autozero signal XAZ at the inverting output/Q. The autozero signal AZ changes between an inactive level and an active level. The inverted autozero signal XAZ changes between an inactive level and an active level.

182 A rising edge of the latch signal LAT indicates the start of an autozeroing interval. Shortly after the latch signal LAT has become active, the reset latch signal RLAT may become active and may reset the master-slave FF.

150 150 126 126 The autozero signal AZ and/or the inverted autozero signal XAZ control an autozero enable switch. When the autozero signal AZ is active and/or the inverted autozero signal XAZ is inactive, the autozero enable switchpasses the reset ramp signal REFR to the control electrode of the reset switch. The reset switchmay be an NFET and the control electrode the gate of the NFET.

100 The active level of the autozero signal AZ indicates that autozeroing is in process for a pixel circuitthat has detected an event and that has been read out.

180 185 185 100 The reset latch circuitfurther includes a switching circuitconfigured to disable the request signal REQ in case the autozero signal AZ and/or the read done signal RDDN is active. For example, the switching circuitdisables a transmission of the request signal REQ from the pixel circuitto the row arbiter when at least one of the autozero signal AZ and the read done signal RDDN is active.

194 194 32 185 185 32 185 185 194 185 185 a a a The event signal EVT is applied to a gate of a request output transistor. A controlled path of the request output transistoris between the request signal lineand a first controllable pathof the switching circuit. A pull-up resistor (not illustrated) terminates the request signal line. The first controllable pathof the switching circuitis electrically connected between the request output transistorand the reference potential VSS. The first controllable pathof the switching circuitcan be controlled to avoid a request during autozeroing.

185 185 b A second controllable pathof the switching circuitcan be used to avoid a second readout before autozeroing is completed.

9 FIG. 185 185 186 187 186 187 194 186 186 187 187 a a a a a a a a a. In, the first controllable pathof the switching circuitincludes a first NFETand a second NFET. Load paths of the first NFETand the second NFETare electrically connected in series between the controlled path of the request output transistorand the reference potential VSS. The inverted read done signal XRDDN is applied to the gate of the first NFETand controls the first NFET. The inverted autozero signal XAZ is applied to the gate of the second NFETand controls the second NFET

Both the inverted autozero signal XAZ and the inverted read done signal XRDDN must be active (and both the autozero signal AZ and the read done signal RDDN inactive) to enable the output of the request signal REQ.

185 185 186 187 186 187 193 186 186 187 187 b b b b b b b b b. The second controllable pathof the switching circuitincludes a third NFETand a fourth NFET. Load paths of the third NFETand the fourth NFETare electrically connected in series between the controlled path of the third output switchand the reference potential VSS. The inverted read done signal XRDDN is applied to the gate of the third NFETand controls the third NFET. The inverted autozero signal XAZ is applied to the gate of the fourth NFETand controls the fourth NFET

Both the inverted autozero signal XAZ and the inverted read done signal XRDDN must be active (and both the autozero signal AZ and the read done signal RDDN inactive) to enable output of event data.

10 FIG. 9 FIG. 100 100 shows a state diagram of the pixel circuitillustrated in. In an idle state, the pixel circuitwaits for events. When the voltage at the input of the pixel comparator circuit crosses the upper or lower threshold, the pixel circuit applies an active group request signal to the control bus. When the pixel circuit detects that a group select signal on the control bus becomes active, the pixel circuit applies the ON signal or the OFF signal to the event data bus. When the group select signal becomes inactive, the pixel circuit stops outputting the ON signal and the OFF signal, sets the read done signal RDDN to the active level and waits for an active latch signal. The active latch signal indicates the start of the next autozeroing interval. When the pixel circuit receives an active latch signal, the pixel circuit sets the autozero signal AZ to the active level, turns on and off the reset switch, and waits for an active reset latch signal. When the pixel circuit receives an active reset latch signal, the pixel circuit sets the read done signal RDDN to the inactive level and waits for the next active latch signal. When the pixel circuit receives the next active latch signal, the reset switch has opened smoothly. The pixel circuit sets the autozero signal AZ to the inactive level and returns to the idle state.

11 FIG. 100 100 shows an image sensor including groups of pixel circuits, wherein the pixel circuitsof each group share a common group ramp signal REFR<x>.

30 100 100 100 30 100 30 100 100 100 100 The row arbiteroutputs a group select signal SEL<x> to a first group of the pixel circuitsin response to a group request signal REQ<x> received from any of the pixel circuitsof the first group. That is, for each group of pixel circuits, the row arbitercan receive a group request signal REQ<x> from any of the pixel circuitsof the group and in response to the received group request signal REQ<x> the row arbiteroutputs a group select signal SEL<x> to each pixel circuitof the concerned group. Each group of pixel circuitsmay include some or all pixel circuitsof one pixel row, or some or all pixel circuitsof more than one pixel row.

20 100 100 The ramp signal circuitoutputs the reset ramp signal REFR<x> for the first group of the pixel circuitsin response to the group select signal SEL<x> for the first group of pixel circuits.

100 The reset ramp signal REFR<x> for the first group of the pixel circuitsis a group-specific reset ramp signal (“group reset ramp signal”) REFR<x>. The group select signal SEL<x> and the group-reset ramp signal REFR<x> have a fixed time relationship to each other, wherein the group select signal SEL<x> triggers the group reset ramp signal REFR<x>.

100 100 When the pixel circuitsare assigned to pixel rows and pixel columns, the first group of the pixel circuitscan be assigned to one of the pixel rows or to one of the pixel columns.

140 180 Each pixel logic circuitincludes a reset latch circuitthat controls the autozeroing process based on the group select signal SEL<x> and the group reset ramp signal REFR<x>.

100 In the illustrated embodiments, each pixel group includes all pixel circuitsof the same pixel row. Accordingly, the group select signal SEL<x> is denominated as row select signal SEL<x>, the group request signal REQ<x> is denominated as row request signal REQ<x>, and the group reset ramp signal REFR<x> is denominated as row reset ramp signal REFR<x>.

12 FIG. 11 FIG. 100 180 shows a pixel circuitwith a reset latch circuitsuitable for the image sensor of.

180 100 121 The reset latch circuitoutputs an autozero signal AZ indicating that the pixel circuithas detected a predefined change in illumination, information about the predefined change in illumination has been read out and initialization of the floating nodeis not complete.

126 100 126 100 100 100 The autozero signal AZ can be used to selectively pass the reset ramp signal REFR to the reset switchonly once the pixel circuithas detected the predefined change in illumination. The reset ramp signal REFR is not passed to the reset switchesof such pixel circuitsof the same group that have not detected a predefined change in illumination. Pixel circuitsof the same group that have not detected a predefined change in illumination remain unaffected from the readout and autozeroing of the pixel circuitsthat have requested an event data readout.

180 22 126 In addition to the autozero signal AZ, the reset latch circuitmay output the inverted autozero signal XAZ. The inverted autozero signal XAZ may also be used to control the transmission of the reset ramp signal REFR from a ramp signal lineto the control input of the reset switch.

13 FIG. 180 188 189 Inthe reset latch circuitincludes an OR gateand an edge sensitive master slave FF.

130 188 130 188 188 A first output of the pixel comparator circuitis connected to a first input of the OR gate. A second output of the pixel comparator circuitis connected to a second input of the OR gate. The OR gatecombines the ON signal and the OFF signal and outputs an event signal EVT. The event signal EVT is active when at least one of the ON signal and the OFF signal is active.

188 194 189 194 189 33 189 189 24 24 189 The output of the OR gateis connected to a gate of the request output transistorand a set input of the master slave FF. An active event signal EVT turns on the request output transistorand can set the master slave FF. The acknowledgment lineis connected to the clock input of the master slave FF. With the leading edge of an active row select signal SEL<x> the master slave FFcaptures the signal at the set input S. A reset latch lineis connected to the reset input R. An active reset latch signal RLAT<x> transmitted on the reset latch lineresets the master slave FF. The non-inverted output Q outputs the autozero signal AZ. The inverted output/Q outputs the inverted autozero signal AZ.

100 180 100 150 126 150 That is, each pixel circuitincludes a reset latch circuitthat outputs an autozero signal AZ in response to a predefined change in illumination. Each pixel circuitfurther includes an autozero enable switchto pass the reset ramp signal REFR to the reset switchin response to the autozero signal AZ. The autozero signal AZ can be used to control the autozero enable switch.

150 126 For example, the autozero enable switchreceives the reset ramp signal REFR and outputs an autozero switching signal AZSW obtained by gating the reset ramp signal REFR with the autozero signal AZ. The autozero switching signal AZSW is applied to the gate of the reset transistor.

14 FIG. 0 1 180 2 2 3 4 shows a time diagram for an event data readout and the subsequent autozero interval. At t=tone of the pixel circuits of a group of pixel circuits sets an active group request signal REQ<x> illustrated with active high level for simplicity. At t=tthe row arbiter sets the group select signal SEL<x> of the concerned group to the active level. In response to the active group select signal SEL<x>, the reset latch circuitswitches the group request signal REQ<x> to the inactive level. After the event data is read out, the row arbiter switches the group select signal SEL<x> to the inactive level at t=t. At t=tor later, the autozero interval starts by setting the reset ramp signal to an active level. The reset switch turns on and the floating node is set to the initial potential. Starting from t=t, the reset ramp signal falls at a comparatively low rate and reaches the inactive level at t=t.

While the leading edge of the reset ramp signal REFR can be as fast as the technology used for the image sensor allows, the slope of the trailing edge is controlled and longer (e.g. by at least one order of magnitude) than a minimum length given by technical limitations. The duration of the trailing edge can be controllable by device settings.

A trailing edge of the reset ramp signal REFR changes at a rate at least ten times slower than a leading edge of the group select signal SEL<x>.

4 189 6 For example, the trailing edge of the reset ramp signal REFR changes at a rate at least twenty, fifty or hundred times slower than the leading edge of the group select signal SEL<x>. The slow change at the gate causes the reset switch to turn off smoothly. At t=tor later the row arbiter changes the group reset latch signal RLAT<x> to an active level to reset the master slave FF. The autozero interval ends when the group reset latch signal RLAT<x> returns to the inactive level at t=t.

15 FIG. 13 FIG. 100 100 shows a state diagram of the pixel circuitillustrated in. In an idle state, the pixel circuitwaits for events. When the voltage at the input of the pixel comparator circuit crosses the upper or lower threshold, the pixel circuit applies an active group request signal to the control bus. When the pixel circuit detects that a group select signal SEL<x> on the control bus becomes active, the pixel circuit applies the ON signal or the OFF signal to the event data bus. When the group select signal SEL<x> becomes inactive, the pixel circuit stops outputting the ON signal and the OFF signal, sets the autozero signal AZ to the active level and waits for an active reset latch signal. The active autozero signal indicates the start of the autozeroing interval. When the pixel circuit receives an active reset latch signal, the reset switch has turned off smoothly. The pixel circuit sets the autozero signal AZ to the inactive level and returns to the idle state.

16 FIG. 110 111 shows a configuration example of a radiation sensitive circuitincluding a photoelectric conversion element, a multiple transistor feedback logarithmic amplifier circuit (LAC) and a source follower.

111 115 113 111 117 116 114 114 111 113 116 114 116 115 113 115 117 116 The anode of the photoelectric conversion elementis electrically connected to the reference potential VSS. The LAC includes a first amplifier NFETand a second amplifier NFETelectrically connected in series between a positive supply potential VDD and the cathode of the photoelectric conversion element. A pull-up PFET (p channel FET)with constantly biased gate, a third amplifier NFETand fourth amplifier NFETare electrically connected in series between the positive supply potential VDD and the reference potential VSS. The gate of the fourth amplifier NFETis connected to the cathode of the photoelectric conversion element. The gate of the second amplifier NFETis connected to a node between the third amplifier NFETand the fourth amplifier NFET. The gate of the third amplifier NFETis connected to a node between the first amplifier NFETand the second amplifier NFET. The gate of the first amplifier NFETis connected to a LAC output node between the pull-up PFETand the third amplifier NFET.

119 118 119 120 The source follower includes a source follower NFETand a load NFETwith constantly biased gate electrically connected in series between the positive supply potential VDD and the reference potential VSS. The LAC output node is electrically connected to the gate of the source follower NFET. The source follower outputs the pixel voltage signal VPR. The source follower forms a near-unity-gain voltage buffer that isolates the LAC from the capacitive amplifier circuit.

3 FIG. 910 920 910 111 920 117 915 910 920 As mentioned with reference to, the image sensor may include a radiation receiving chipand a processing chip. The radiation receiving chipcan include the photoelectric conversion elementand the NFETs of the logarithmic amplifier. The processing chipmay include the pull-up PFETand the source follower. One through contact viaper pixel circuit passes the signal from the radiation receiving chipto the processing chip.

110 111 111 Other examples of the radiation sensitive circuitmay be based on a basic configuration of a logarithmic amplifier with an inverting amplifier and a feedback element with logarithmic current-to-voltage relation that is connected between an input and an output of the inverting amplifier. The inverting amplifier ensures that a voltage across the photoelectric conversion elementis approximately constant. The pixel voltage signal VPR shows a logarithmic dependence on the photocurrent of the photoelectric conversion element.

17 FIG. 120 130 shows a configuration example of a combination of a capacitive amplifier circuitand a pixel comparator circuit.

120 122 125 126 122 125 126 129 128 129 128 129 121 128 1 129 128 122 125 5 FIG. The capacitive amplifier circuitincludes a switched capacitor amplifier including a storage capacitor, a feedback capacitor, a reset switchand an inverting amplifier circuit. As regards the storage capacitor, the feedback capacitorand the reset switch, reference is made to the description of. The inverting amplifier circuit includes a first PFETand a first load NFET, wherein load paths of the first PFETand the first load NFETare electrically connected in series between the positive supply potential VDD and the reference potential VSS. The gate of the first PFETis connected to the floating node. The gate of the first load NFETreceives a constant bias voltage bias. The inverting amplifier circuit outputs an amplified signal at the node between the first PFETand the first load NFET. A voltage gain of the inverting amplifier circuit is substantially larger than a ratio of the capacitance of the storage capacitorto the capacitance of the feedback capacitor.

130 131 132 139 The pixel comparator circuitincludes a first comparator, a second comparator, and an inverter circuit.

131 134 133 134 133 134 120 2 133 The first comparatorincludes a first comparator PFETand a first threshold NFET, wherein load paths of the first comparator PFETand the first threshold NFETare electrically connected in series between the positive supply potential VDD and the reference potential VSS. The gate of the first comparator PFETreceives the output signal of the capacitive amplifier circuit. A constant second bias voltage biasis applied to the gate of the first threshold NFET.

132 136 135 136 135 136 120 3 135 134 133 120 131 134 133 131 136 135 120 132 136 135 132 The second comparatorincludes a second comparator PFETand a second threshold NFET, wherein load paths of the second comparator PFETand the second threshold NFETare electrically connected in series between the positive supply potential VDD and the reference potential VSS. The gate of the second comparator PFETreceives the output signal of the capacitive amplifier circuit. A constant third bias voltage biasis applied to the gate of the second threshold NFET. The channel widths of the first comparator PFETand the first threshold NFETmay be selected such that when the output signal of the capacitive amplifier circuitrises above a certain threshold, the first comparatoroutputs a high voltage level active ON signal at a first output node between the first comparator PFETand the first threshold NFET. Otherwise, the first comparatoroutputs a low voltage level at the first output node. The channel widths of the second comparator PFETand the second threshold NFETare selected such that when the output signal of the capacitive amplifier circuitfalls below a certain threshold, the second comparatoroutputs a low-level voltage signal at an internal output node between the second comparator PFETand the second threshold NFET. Otherwise, the second comparatoroutputs a high voltage level at the internal output node.

134 136 133 135 2 3 133 135 120 131 134 133 120 132 136 135 129 134 136 Alternatively, the channel widths of the first comparator PFETand the second comparator PFETmay be equal, and the channel widths of the first threshold NFETand the second threshold NFETmay be equal, and the biases bias, biason the gates of the first threshold NFETand the second threshold NFETare chosen such that when the output signal of the capacitive amplifier circuitrises above a certain threshold, the first comparatoroutputs a high voltage level active ON signal at the first output node between the first comparator PFETand the first threshold NFET, and when the output signal of the capacitive amplifier circuitfalls below a certain threshold, the second comparatoroutputs a low-level voltage signal at the internal output node between the second comparator PFETand the second threshold NFET. The first pFETmay have the same channel width as the first comparator PFETand the second comparator PFET.

139 132 120 The inverter circuitinverts the signal at the internal output node such that the second comparatoroutputs an active high voltage level OFF signal when the output signal of the capacitive amplifier circuitfalls below the certain threshold.

18 FIG. 150 shows a configuration example of the autozero enable switch.

150 155 153 20 126 The autozero enable switchincludes an NFETand a PFETelectrically connected in parallel between an output of the ramp signal circuitand a control input of the reset switch.

155 153 155 153 153 155 More particularly, the controlled load paths between source and drain of the NFETand source and drain of the PFETare electrically connected in parallel. The NFETand the PFETare configured as transmission gate working as analog switch. The bulk of the PFETmay be connected to a positive potential. The bulk of the NFETmay be connected to the reference potential VSS.

155 189 155 153 189 153 13 FIG. 13 FIG. The autozero signal AZ is applied to the gate of the NFET. For example, the non-inverting output Q of the master slave FFofis connected to the gate of the NFET. The inverted autozero signal XAZ is applied to the gate of the PFET. For example, the inverting output /Q of the master slave FFofis connected to the gate of the PFET. At a first side of the parallel load paths, the group reset ramp signal REFR<x> is applied. At the second side of the parallel load paths, an autozero switch signal is obtained that is applied to the control electrode of the reset switch in the pixel circuit.

154 126 154 154 126 The controlled load path of an auxiliary NFETmay be connected between the control input of the reset switchand the reference potential VSS. The inverted autozero signal XAZ is applied to the gate of the auxiliary NFET. The auxiliary NFETholds the autozero switching signal AZSW fixed at the reference potential VSS when the autozero signal AZ has a low level and the inverted autozero signal XAZ has a high level, and prevents the reset switchfrom being inadvertently turned on.

19 FIG. 30 300 310 310 100 100 100 310 390 shows a row arbiterthat includes an arbitration circuitand a plurality of arbiter interface circuits, wherein each arbiter interface circuitis assigned to one group of pixel circuits, e.g., to all pixel circuitsof one pixel row. One group of pixel circuitsand the associated arbiter interface circuitform an interfaced pixel group.

310 312 311 32 32 100 312 312 315 300 The arbiter interface circuitincludes an inverting circuitand a request pull-up transistorterminating the request signal line. The request signal linetransmits an active low group request signal XRQY<m> from the pixel circuitsto the inverting circuit. The inverting circuitconverts the active low group request signal XRQY<m> into an active high group request signal RQY<m>. A group interface circuitreceives the active high group request signal RQY<m> and passes a group request signal REQ<m> to the arbitration circuit.

300 The arbitration circuitresponds to various group request signals REQ<m> by transmitting group acknowledgement signals ACK<m> in a sequence resulting from a predefined priority scheme.

315 In response to a received acknowledgement signal ACK<m>, the group interface circuitgenerates an unbuffered group select signal SEL<m>, an unbuffered group reset latch signal<m>, and a group autozero start signal AZP<m>.

313 33 314 24 20 22 A first buffer circuitreceives the unbuffered group select signal SEL<m> and outputs a buffered group select signal SELB<m> on the acknowledgement signal line. A second buffer circuitreceives the unbuffered group reset latch signal RLAT<m> and outputs a buffered group reset latch signal RLTB<m> on a reset latch signal line. The group autozero start signal AZP<m> controls the ramp signal circuitto start outputting the group reset ramp signal REFR<m> on the ramp signal line.

20 FIG. 19 FIG. 1 315 100 100 shows a time diagram for the signals in. A minimum read wait period Δtbetween the leading edge of the group request signal REQ<m> and the leading edge of the group select signal SEL<m> can be defined in the group interface circuitto give other pixel circuitsof the same group the opportunity to detect a predefined change in illumination. Then, more pixel circuitscan be read out in the same readout.

1 315 315 At t=tthe group interface circuitcan set the grout request signal REQ<m> to the inactive level simultaneously with the group select signal SEL<m> provided that the active high group request signal RQY<m> at the input of the group interface circuithas the low level.

2 315 The period Δtshows an example where the group interface circuitignores an active high group request signal RQY<m> until an ongoing autozeroing is completed as indicated by the trailing edge of an active pulse of the group reset latch signal RLAT<m>.

3 315 The period Δtbetween the trailing edge of the group autozero start pulse AZP<m> and the leading edge of the group reset latch signal RLAT<m> can be configurable. The widths of the active pulses of the group reset latch signal RLAT<m>, the group select signal SEL<m>, and the group autozero signal AZP<m> may be configurable in the group interface circuit.

4 Finally, the time diagram shows that during the autozeroing of pixel group m in period Δt, pixel group m+1 can be read out.

21 FIG. 19 FIG. 315 shows an exemplary state diagram for the operation of a group interface circuitas illustrated in.

315 315 The group interface circuit wakes up from an idle state by receiving an active high group request signal RQY<m>. The group interface circuit outputs an active group request signal REQ<m> to the arbitration circuit and starts a read wait timer. When the read wait timer is expired and a group acknowledgement signal ACK<m> is received, the group interface circuitsets the group select signal SEL<m> to the active level, starts a select timer and waits for that the active high group request signal RQY<m> gets inactive. When the select timer expires, the group interface circuitsets the group select signal SEL<m> inactive.

315 When the select timer expires before the active high group request signal RQY<m> gets inactive, the group interface circuitstarts an autozero pulse timer and sets the group autozero start signal AZP<m> when the active high group request signal RQY<m> gets inactive.

315 When the select timer expires after the active high group request signal RQY<m> gets inactive, the group interface circuitstarts an autozero pulse timer and sets the group autozero start signal AZP<m> when the select timer expires.

315 When the autozero pulse timer expires, the group interface circuitsets the group autozero start signal AZP<m> inactive and starts a reset latch delay timer.

315 When the reset latch delay timer expires, the group interface circuitsets the group reset latch signal RLAT<m> active and starts a reset latch pulse width timer.

315 When the reset latch pulse width timer expires, the group interface circuitsets the group reset latch signal RLAT<m> inactive and returns to the idle state.

22 FIG. is a block diagram depicting an example of schematic configuration of a vehicle control system as an example of a system to which the technology according to an embodiment of the present disclosure can be applied.

12000 12001 12000 12010 12020 12030 12040 12050 12051 12052 12053 12050 22 FIG. The vehicle control systemincludes a plurality of electronic control units connected to each other via a communication network. In the example depicted in, the vehicle control systemincludes a driving system control unit, a body system control unit, an outside-vehicle information detecting unit, an in-vehicle information detecting unit, and an integrated control unit. In addition, a microcomputer, a sound/image output section, and a vehicle-mounted network interfaceare illustrated as a functional configuration of the integrated control unit.

12010 12010 The driving system control unitcontrols the operation of devices related to the driving system of the vehicle in accordance with various kinds of programs. For example, the driving system control unitfunctions as a control device for a driving force generating device for generating the driving force of the vehicle, such as an internal combustion engine, a driving motor, or the like, a driving force transmitting mechanism for transmitting the driving force to wheels, a steering mechanism for adjusting the steering angle of the vehicle, a braking device for generating the braking force of the vehicle, and the like.

12020 12020 12020 12020 The body system control unitcontrols the operation of various kinds of devices provided to a vehicle body in accordance with various kinds of programs. For example, the body system control unitfunctions as a control device for a keyless entry system, a smart key system, a power window device, or various kinds of lamps such as a headlamp, a backup lamp, a brake lamp, a turn signal, a fog lamp, or the like. In this case, radio waves transmitted from a mobile device as an alternative to a key or signals of various kinds of switches can be input to the body system control unit. The body system control unitreceives these input radio waves or signals, and controls a door lock device, the power window device, the lamps, or the like of the vehicle.

12030 12000 12030 12031 12030 12031 12030 The outside-vehicle information detecting unitdetects information about the outside of the vehicle including the vehicle control system. For example, the outside-vehicle information detecting unitis connected with an imaging section. The outside-vehicle information detecting unitmakes the imaging sectionimaging an image of the outside of the vehicle, and receives the imaged image. On the basis of the received image, the outside-vehicle information detecting unitmay perform processing of detecting an object such as a human, a vehicle, an obstacle, a sign, a character on a road surface, or the like, or processing of detecting a distance thereto.

12031 12031 The imaging sectionmay be or may include an image sensor or a solid-state imaging device with an image sensor according to the embodiments of the present disclosure. The light received by the imaging sectionmay be visible light or may be invisible light such as infrared rays or the like.

12040 12040 12041 12041 12041 12040 The in-vehicle information detecting unitdetects information about the inside of the vehicle and may be or may include an image sensor or a solid-state imaging device with an image sensor according to the embodiments of the present disclosure. The in-vehicle information detecting unitis, for example, connected with a driver state detecting sectionthat detects the state of a driver. The driver state detecting section, for example, includes a camera that includes the solid-stage imaging device and that is focused on the driver. On the basis of detection information input from the driver state detecting section, the in-vehicle information detecting unitmay calculate a degree of fatigue of the driver or a degree of concentration of the driver or may determine whether the driver is dozing.

12051 12030 12040 12010 12051 The microcomputercan calculate a control target value for the driving force generating device, the steering mechanism, or the braking device on the basis of the information about the inside or outside of the vehicle which information is obtained by the outside-vehicle information detecting unitor the in-vehicle information detecting unit, and output a control command to the driving system control unit. For example, the microcomputercan perform cooperative control intended to implement functions of an advanced driver assistance system (ADAS) which functions include collision avoidance or shock mitigation for the vehicle, following driving based on a following distance, vehicle speed maintaining driving, a warning of collision of the vehicle, a warning of deviation of the vehicle from a lane, or the like.

12051 12030 12040 In addition, the microcomputercan perform cooperative control intended for automatic driving, which makes the vehicle to travel autonomously without depending on the operation of the driver, or the like, by controlling the driving force generating device, the steering mechanism, the braking device, or the like on the basis of the information about the outside or inside of the vehicle which information is obtained by the outside-vehicle information detecting unitor the in-vehicle information detecting unit.

12051 12020 12030 12051 12030 In addition, the microcomputercan output a control command to the body system control uniton the basis of the information about the outside of the vehicle which information is obtained by the outside-vehicle information detecting unit. For example, the microcomputercan perform cooperative control intended to prevent a glare by controlling the headlamp so as to change from a high beam to a low beam, for example, in accordance with the position of a preceding vehicle or an oncoming vehicle detected by the outside-vehicle information detecting unit.

12052 12061 12062 12063 12062 22 FIG. The sound/image output sectiontransmits an output signal of at least one of a sound or an image to an output device capable of visually or audible notifying information to an occupant of the vehicle or the outside of the vehicle. In the example of, an audio speaker, a display section, and an instrument panelare illustrated as the output device. The display sectionmay, for example, include at least one of an on-board display or a head-up display.

23 FIG. 12031 12031 12101 12102 12103 12104 12105 is a diagram depicting an example of the installation position of the imaging section, wherein the imaging sectionmay include imaging sections,,,, and.

12101 12102 12103 12104 12105 12100 12101 12105 12100 12102 12103 12100 12104 12100 12105 The imaging sections,,,, andare, for example, disposed at positions on a front nose, side-view mirrors, a rear bumper, and a back door of the vehicleas well as a position on an upper portion of a windshield within the interior of the vehicle. The imaging sectionprovided to the front nose and the imaging sectionprovided to the upper portion of the windshield within the interior of the vehicle obtain mainly an image of the front of the vehicle. The imaging sectionsandprovided to the side view mirrors obtain mainly an image of the sides of the vehicle. The imaging sectionprovided to the rear bumper or the back door obtains mainly an image of the rear of the vehicle. The imaging sectionprovided to the upper portion of the windshield within the interior of the vehicle is used mainly to detect a preceding vehicle, a pedestrian, an obstacle, a signal, a traffic sign, a lane, or the like.

23 FIG. 12101 12104 12111 12101 12112 12113 12102 12103 12114 12104 12100 12101 12104 Incidentally,depicts an example of photographing ranges of the imaging sectionsto. An imaging rangerepresents the imaging range of the imaging sectionprovided to the front nose. Imaging rangesandrespectively represent the imaging ranges of the imaging sectionsandprovided to the side view mirrors. An imaging rangerepresents the imaging range of the imaging sectionprovided to the rear bumper or the back door. A bird's-eye image of the vehicleas viewed from above is obtained by superimposing image data imaged by the imaging sectionsto, for example.

12101 12104 12101 12104 At least one of the imaging sectionstomay have a function of obtaining distance information. For example, at least one of the imaging sectionstomay be a stereo camera constituted of a plurality of imaging elements, imaging element having pixels for phase difference detection or may include a ToF module including an image sensor or a solid-state imaging device with an image sensor according to the embodiments of the present disclosure.

12051 12111 12114 12100 12101 12104 12100 12100 12051 For example, the microcomputercan determine a distance to each three-dimensional object within the imaging rangestoand a temporal change in the distance (relative speed with respect to the vehicleon the basis of the distance information obtained from the imaging sectionsto, and thereby extract, as a preceding vehicle, a nearest three-dimensional object in particular that is present on a traveling path of the vehicleand which travels in substantially the same direction as the vehicleat a predetermined speed (for example, equal to or more than 0 km/hour). Further, the microcomputercan set a following distance to be maintained in front of a preceding vehicle in advance, and perform automatic brake control (including following stop control), automatic acceleration control (including following start control), or the like. It is thus possible to perform cooperative control intended for automatic driving that makes the vehicle travel autonomously without depending on the operation of the driver or the like.

12051 12101 12104 12051 12100 12100 12100 12051 12051 12061 12062 12010 12051 For example, the microcomputercan classify three-dimensional object data on three-dimensional objects into three-dimensional object data of a two-wheeled vehicle, a standard-sized vehicle, a large-sized vehicle, a pedestrian, a utility pole, and other three-dimensional objects on the basis of the distance information obtained from the imaging sectionsto, extract the classified three-dimensional object data, and use the extracted three-dimensional object data for automatic avoidance of an obstacle. For example, the microcomputeridentifies obstacles around the vehicleas obstacles that the driver of the vehiclecan recognize visually and obstacles that are difficult for the driver of the vehicleto recognize visually. Then, the microcomputerdetermines a collision risk indicating a risk of collision with each obstacle. In a situation in which the collision risk is equal to or higher than a set value and there is thus a possibility of collision, the microcomputeroutputs a warning to the driver via the audio speakeror the display section, and performs forced deceleration or avoidance steering via the driving system control unit. The microcomputercan thereby assist in driving to avoid collision.

12101 12104 12051 12101 12104 12101 12104 12051 12101 12104 12052 12062 12052 12062 At least one of the imaging sectionstomay be an infrared camera that detects infrared rays. The microcomputercan, for example, recognize a pedestrian by determining whether or not there is a pedestrian in imaged images of the imaging sectionsto. Such recognition of a pedestrian is, for example, performed by a procedure of extracting characteristic points in the imaged images of the imaging sectionstoas infrared cameras and a procedure of determining whether or not it is the pedestrian by performing pattern matching processing on a series of characteristic points representing the contour of the object. When the microcomputerdetermines that there is a pedestrian in the imaged images of the imaging sectionsto, and thus recognizes the pedestrian, the sound/image output sectioncontrols the display sectionso that a square contour line for emphasis is displayed so as to be superimposed on the recognized pedestrian. The sound/image output sectionmay also control the display sectionso that an icon or the like representing the pedestrian is displayed at a desired position.

The example of the vehicle control system to which the technology according to an embodiment of the present disclosure is applicable has been described above. By applying an image sensor or a solid-state imaging device with an image sensor according to the embodiments of the present disclosure, the sensors have improved time resolution and sensing performance.

Additionally, embodiments of the present technology are not limited to the above-described embodiments, but various changes can be made within the scope of the present technology without departing from the gist of the present technology.

The image sensor according to the present disclosure may be any device used for analyzing and/or processing radiation such as visible light, infrared light, ultraviolet light, and X-rays. For example, a solid-state imaging device including an image sensor according to the embodiments may be any electronic device in the field of traffic, the field of home appliances, the field of medical and healthcare, the field of security, the field of beauty, the field of sports, the field of agriculture, the field of image reproduction or the like.

Specifically, in the field of image reproduction, the solid-state imaging device including an image sensor according to the embodiments may be a device for capturing an image to be provided for appreciation, such as a digital camera, a smart phone, or a mobile phone device having a camera function. In the field of traffic, for example, the solid-state imaging device including an image sensor according to the embodiments may be integrated in an in-vehicle sensor that captures the front, rear, peripheries, an interior of the vehicle, etc. for safe driving such as automatic stop, recognition of a state of a driver, or the like, in a monitoring camera that monitors traveling vehicles and roads, or in a distance measuring sensor that measures a distance between vehicles or the like.

In the field of home appliances, the image sensor according to the embodiments may be integrated in any type of sensor that can be used in devices provided for home appliances such as TV receivers, refrigerators, and air conditioners to capture gestures of users and perform device operations according to the gestures. Accordingly the image sensor according to the embodiments may be integrated in home appliances such as TV receivers, refrigerators, and air conditioners and/or in devices controlling the home appliances. Furthermore, in the field of medical and healthcare, the image sensor according to the embodiments may be integrated in any type of sensor, e.g. a solid-state image device, provided for use in medical and healthcare, such as an endoscope or a device that performs angiography by receiving infrared light.

In the field of security, the image sensor according to the embodiments can be integrated in a device provided for use in security, such as a monitoring camera for crime prevention or a camera for person authentication use. Furthermore, in the field of beauty, an image sensor according to the embodiments can be used in a device provided for use in beauty, such as a skin measuring instrument that captures skin or a microscope that captures a probe. In the field of sports, an image sensor according to the embodiments can be integrated in a device provided for use in sports, such as an action camera or a wearable camera for sport use or the like. Furthermore, in the field of agriculture, the image sensor can be used in a device provided for use in agriculture, such as a camera for monitoring the condition of fields and crops.

80 10 100 100 100 121 100 126 121 20 100 [1] An image sensor (), including: a pixel array () including pixel circuits (), wherein each pixel circuit () is configured to output a request signal in response to a predefined change in illumination, wherein each pixel circuit () includes a floating node () configured to temporally store charge as a function of a change of an illumination condition, and wherein each pixel circuit () includes a reset switch () configured to set the floating node () to a predefined initial potential in response to a reset ramp signal; and a ramp signal circuit () configured to output the reset ramp signal for at least a first group of the pixel circuits (). 100 100 126 100 121 [2] The image sensor according to [1], wherein the pixel circuits () are configured such that, for each pixel circuit (), the reset ramp signal is passed to the reset switch () only for a period of time after detection of a predefined change in illumination in the pixel circuit () and before an end of setting the initial potential of the floating node (). 20 [3] The image sensor according to any of [1] and [2], wherein the ramp signal circuit () is configured to output the reset ramp signal at regular time intervals. 20 100 10 [4] The image sensor according to any of [1] to [3], wherein the ramp signal circuit () is configured to output the reset ramp signal for each pixel circuit () of the pixel array (). 100 180 [5] The image sensor according to any of [1] to [4], wherein each of the pixel circuits () includes a reset latch circuit () configured to suppress an output of the request signal for a period starting after information about the predefined change in illumination has been read out until an end of a following complete period of the reset ramp signal. 180 100 100 [6] The image sensor according to [5], wherein the reset latch circuit () is configured to output a read done signal indicating that the pixel circuit () has detected a predefined change in illumination, and that information about the predefined change in illumination has been read out from the pixel circuit (). 180 100 [7] The image sensor according to any of [5] and [6], wherein the reset latch circuit () is configured to output an autozero signal indicating start and end of a complete period of the reset ramp signal following the detection of a predefined change in illumination the pixel circuit (). 100 185 [8] The image sensor according to any of [6] to [7], wherein each pixel circuit () includes a switching circuit () configured to disable the request signal in case the read done signal and/or the autozero signal is active. 30 100 100 [9] The image sensor according to [1], further including: a row arbiter circuit () configured to output a group select signal for a first group of the pixel circuits () in response to a group request signal received from any of the pixel circuits () of the first group. 20 100 100 [10] The image sensor according to [9], wherein the ramp signal circuit () is configured to output the reset ramp signal for the first group of the pixel circuits () in response to the group select signal for the first group of pixel circuits (). 100 100 [11] The image sensor according to any of [9] and [10], wherein the pixel circuits () are assigned to pixel rows and pixel columns, and wherein the first group of the pixel circuits () are assigned to one of the pixel rows or to one of the pixel columns. 180 100 121 [12] The image sensor according to any of [9] to [11], wherein the reset latch circuit () is configured to output an autozero signal indicating that the pixel circuit () has detected a predefined change in illumination, information about the predefined change in illumination has been read out and initialization of the floating node () is not complete. [13] The image sensor according to any of [9] to [12], wherein a trailing edge of the reset ramp signal changes at a rate at least ten times slower than a leading edge of the group select signal. 100 180 150 150 126 180 [14] The image sensor according to any of [1] to [13], wherein each pixel circuit () further includes a reset latch circuit () and an autozero enable switch (), wherein the autozero enable switch () is configured to pass the reset ramp signal to the reset switch () in response to an autozero signal, and wherein the reset latch circuit () is configured to output the autozero signal in response to the predefined change in illumination. 150 151 152 20 126 [15] The image sensor according to [14], wherein the autozero enable switch () includes an NFET () and a PFET () electrically connected in parallel between an output of the ramp signal circuit () and a control input of the reset switch (). The present technology can also be configured as described below: