Apparatus and Method for Performing a Read Operation in a Memory Device

This patent application claims the benefit of Korean Patent Application No. 10-2025-0020650, filed on Feb. 18, 2025, the entire disclosure of which is incorporated herein by reference.

Embodiments of the present disclosure described herein relate to a memory system, and more particularly, to an apparatus and a method for performing a read operation in a memory device.

A data processing system includes a memory system or a data storage device. The data processing system can be developed to store more voluminous data in the data storage device, store data in the data storage device faster, and read data stored in the data storage device faster. The memory system or the data storage device can include non-volatile memory cells and/or volatile memory cells for storing data. In order to improve operational safety of an internal operation associated with a command transmitted from an external device, the memory system can control an operation for reading data stored in the memory cells.

Various embodiments of the present disclosure are described below with reference to the accompanying drawings. Elements and features of this disclosure may be configured or arranged differently to form other embodiments, which may be variations of any of the disclosed embodiments.

In this disclosure, references to various features (e.g., elements, structures, modules, components, steps, operations, characteristics, etc.) included in “one embodiment,” “example embodiment,” “an embodiment,” “another embodiment,” “some embodiments,” “various embodiments,” “other embodiments,” “alternative embodiment,” and the like are intended to mean that any such features are included in one or more embodiments of the present disclosure, but may or may not necessarily be combined in the same embodiments.

In this disclosure, the terms “comprise,” “comprising,” “include,” and “including” are open-ended. As used in the appended claims, these terms specify the presence of the stated elements and do not preclude the presence or addition of one or more other elements. Furthermore, the terms in a claim do not foreclose the apparatus from including additional components, e.g., an interface unit, circuitry, etc.

In this disclosure, various units, circuits, or other components may be described or claimed as “configured to” perform a task or tasks. In such contexts, “configured to” is used to connote structure by indicating that the blocks/units/circuits/components include structure (e.g., circuitry) that performs one or more tasks during operation. As such, the block/unit/circuit/component can be said to be configured to perform the task even when the specified block/unit/circuit/component is not currently operational, e.g., is not turned on nor activated. The block/unit/circuit/component used with the “configured to” language may include hardware, for example, circuits, memory storing program instructions executable to implement the operation, etc. Additionally, “configured to” can include a generic structure (e.g., generic circuitry) that is manipulated by software and/or firmware (e.g., an FPGA or a general-purpose processor executing software) to operate in a manner capable of performing the task(s) at issue. “Configured to” may also include adapting a manufacturing process (e.g., a semiconductor fabrication facility) to fabricate devices (e.g., integrated circuits) that are adapted to implement or perform one or more tasks.

As used in this disclosure, the term ‘circuitry’ or ‘logic’ refers to all of the following: (a) hardware-only circuit implementations (such as implementations in only analog and/or digital circuitry) and (b) combinations of circuits and software (and/or firmware), such as (as applicable): (i) to a combination of processor(s) or (ii) to portions of processor(s)/software (including digital signal processor(s)), software, and memory(ies) that work together to cause an apparatus, such as a mobile phone or server, to perform various functions and (c) circuits, such as a microprocessor(s) or a portion of a microprocessor(s), that require software or firmware for operation, even if the software or firmware is not physically present. This definition of ‘circuitry’ or ‘logic’ applies to all uses of this term in this application, including in any claims. As a further example, as used in this application, the term “circuitry” or “logic” also covers an implementation of merely a processor (or multiple processors) or portion of a processor and its (or their) accompanying software and/or firmware. The term “circuitry” or “logic” also covers, for example, and if applicable to a particular claim element, an integrated circuit for a storage device.

As used herein, the terms “first,” “second,” “third,” and so on are used as labels for nouns that they precede, and do not imply any type of ordering (e.g., spatial, temporal, logical, etc.). The terms “first” and “second” do not necessarily imply that the first value must be written before the second value. Further, although the terms may be used herein to identify various elements, these elements are not limited by these terms. These terms are used to distinguish one element from another element that otherwise have the same or similar names. For example, a first circuitry may be distinguished from a second circuitry.

Further, the term “based on” is used to describe one or more factors that affect a determination. This term does not foreclose additional factors that may affect a determination. That is, a determination may be solely based on those factors or based, at least in part, on those factors. Consider the phrase “determine A based on B.” While in this case, B is a factor that affects the determination of A, such a phrase does not foreclose the determination of A from also being based on C. In other instances, A may be determined based solely on B.

Herein, a data entry, an entry of data, an item of data, or a data item may be a sequence of bits. For example, the data entry may include the contents of a file, a portion of the file, a page in memory, an object in an object-oriented program, a digital message, a digital scanned image, a part of a video or audio signal, metadata or any other entity which can be represented by a sequence of bits. According to an embodiment, the data entry may include a discrete object. According to another embodiment, the data entry may include a unit of information processed or handled for a data input/output operation. According to another embodiment, the data entry may include a unit of information within a transmission packet between two different components.

Embodiments in the present disclosure can provide a memory system, a data processing system, and an operation process or a method, which may quickly and reliably process data into a memory device by reducing operational complexity and performance degradation of the memory system, thereby enhancing usage efficiency of the memory device.

Embodiments of the present disclosure may solve an issue that an amount of current flowing through a bit line corresponding to data stored in a memory cell decreases in a three-dimensional high-density memory device, making it difficult to detect or sense the data, by arranging a current mirror between a bit line and a sense line and allowing an increased current to flow through the sense line for a limited time range, the increase current being greater than the current flowing in the bit line, thereby improving operating characteristics of the memory device.

In addition, because an embodiment of the present disclosure can increase an amount of the current through the current mirror even if a current flowing in the bit line coupled to the memory cell is small, power consumption of the memory device may be reduced and the memory device may operate even in a low-power environment.

Further, an embodiment of the present disclosure is a memory device including a current mirror for increasing an amount of the current flowing, in response to data stored in a non-volatile memory cell, through a bit line coupled to the non-volatile memory cell and transmitting the increased current to a page buffer, so that a reduction in the amount of the current flowing through the non-volatile memory cell in the memory device formed with a plurality of stacks may be overcome without an improvement in the design or fabricating process, thereby improving production efficiency and production cost.

In an embodiment, a memory device may include at least one memory cell configured to store at least one bit of data; at least one page buffer configured to store data read from the at least one memory cell; and a current mirror arranged between the at least one memory cell and the at least one page buffer, the current mirror having a current gain which is adaptively adjustable or controllable.

The memory device may further include a word line connected to the at least one memory cell; a bit line connected to the at least one memory cell; and a sensing line connected to the at least one page buffer. The current mirror may connect the bit line to the sensing line. The current gain may be greater than 1.

In the memory device, an operation for reading data stored in the at least one memory cell may include a precharge period, an evaluation period, and a sensing period. The current mirror may be configured to generate, during the evaluation period, an amount of a second current flowing through the sensing line greater than an amount of a first current flowing through the bit line.

The at least one memory cell may be configured to store multi-bit data. The first current flowing through the at least one memory cell and the bit line may be determined in response to one of plural levels of a read voltage supplied through the word line.

The at least one page buffer may be configured to store a binary value that is determined based whether the second current is detected.

The current gain of the current mirror may have different values during a read operation and a program operation. A connection time between the at least one memory cell and the at least one page buffer may vary during the read operation and the program operation.

The current gain of the current mirror may be determined during a test process performed after manufacturing of the memory device.

The current gain of the current mirror may vary depending on a wear degree of the at least one memory cell.

The current mirror may include P-channel metal-oxide-semiconductor (PMOS) transistors each having one side connected to a power supply voltage.

The current mirror may include N-channel metal-oxide-semiconductor (NMOS) transistors each having one side connected to a ground voltage.

The current mirror may include inductors each having one side connected to a power supply voltage.

In another embodiment, a non-volatile memory device may include a cell string including a plurality of memory cells connected in series; a bit line connected to the cell string; a current mirror connected to the bit line; and at least one page buffer connected to the current mirror.

In the non-volatile memory device, an amount of current flowing through the cell string and the bit line may be determined when voltages of different levels are applied through a plurality of word lines respectively connected to each of the plurality of memory cells. The current mirror may be configured to increase the current by N times, and flow the increased current to the at least one page buffer, N being a positive number greater than 1.

The at least one page buffer may be configured to store a binary value that is determined based on whether the increased current output from the current mirror is detected.

The current mirror may include PMOS transistors each having one side connected to a power supply voltage.

The current mirror may include NMOS transistors each having one side connected to a ground voltage.

The current mirror may include inductors each having one side connected to a power supply voltage.

The bit line and the at least one page buffer may be not directly electrically connected.

In another embodiment, a method for operating a memory device may include applying a read voltage to a word line connected to a memory cell; precharging a sensing line connected to a page buffer; operating a current mirror to increase an amount of a current, flowing through a bit line connected to the memory cell, by N times and flow the increased current to the precharged sensing line, N being a positive number greater than 1; and storing, in the page buffer, a binary value that is determined based on whether the current flowed to the sensing line by from the current mirror is detected.

The binary value may be stored in the page buffer after the current mirror is disconnected from the sensing line.

An embodiment described herein can provide an apparatus and a method for improving a data input/output operation of a memory system or a data processing system.

Embodiments will now be described with reference to the accompanying drawings, wherein like numbers reference like elements.

1 FIG. illustrates the structure and operation of a memory device according to an embodiment of the present disclosure.

1 FIG. 342 344 342 344 342 344 344 342 344 342 344 342 Referring to, a conventional memory device can include a memory cell (cell)and a page buffer (PB). The memory celland the page buffermay be electrically directly connected. In this context, being directly connected means that a current path is connected through which a current flowing through the memory cellcan flow to the page buffer. A power voltage (Vcore) may be connected to the page buffer, and a ground voltage may be connected to the memory cell. The current path can be formed to pass through the page bufferand the memory cellbetween the power voltage (Vcore) and the ground voltage. The page buffermay store a binary value in response to whether or not a cell current flowing through the memory cellis detected (e.g., store a value dependent on whether a cell current is detected).

344 344 344 344 344 A memory device may be formed with a plurality of memory cells, and the plurality of memory cells may be formed as a three-dimensional structure. In a three-dimensional structure in which dozens or more layers/dies are stacked, each layer/die including the plurality of memory cells arranged in an array form, the cell current may decrease as the number of layers/dies in the stack increases. Therefore, in a first stack 5XX-LAYER, the cell current may be greater than an amount of cell current (Itrip), for example, 15 nA, which may be detectable by the page buffer, so that it may not be difficult for the page bufferto detect the cell current. However, in a second stack 6XX-LAYER, the cell current may be not greater than the amount of cell current (Itrip), for example, 15 nA, which can be detectable by the page buffer, so that it may be difficult for the page bufferto detect the cell current. The page buffercould not sense or detect the cell current when the cell current is too small (e.g., less than 15 nA). For this reason, a margin of the read operation performed in the memory device having the second stack might be lengthened, and an additional operation may be required to increase the amount of cell current in the second stack. The sensing as configured may be unable to detect the cell current.

346 348 346 348 342 344 346 348 346 348 346 344 346 344 Further, a memory device according to an embodiment of the present disclosure may include a memory cell (cell)and a page buffer (PB). The memory celland the page buffermay be structurally identical to the memory celland the page buffer. However, the memory celland the page bufferin the memory device may not be directly connected through a single current path. Different current paths are formed individually through the memory celland the page buffer. The memory device may copy a current flowing through the memory cellto be N (where N is a positive number greater than 1) times larger and cause N times current to flow through the page buffer. That is, a page buffer current (e.g., PB Current) N times the cell current (e.g., Cell current) flowing through the memory cellmay flow through the page buffer.

348 348 In the case of the first stack 5XX-LAYER in the three-dimensional structure of the conventional memory device, the amount of cell current may be sufficient, but the amount of cell current may be not sufficient in the second stack 6XX-LAYER. On the other hand, in the memory device according to one embodiment of the present disclosure, the page buffer current (e.g., PB Current) that increases the cell current by N times can flow through the page bufferin the second stack 6XX-LAYER. Through this scheme, a detection margin (e.g., Itrip sensing margin) may be secured through the page buffer current (e.g., PB Current) corresponding to the cell current in the second stack 6XX-LAYER because the page buffer current may be detected (is detectable) by the page buffer.

348 346 Meanwhile, the page buffercan detect the page buffer current (e.g., PB Current) that increases the cell current, flowing through the memory cell, by N times, faster than detecting the cell current, because the page buffer current has a greater amount than the cell current. Accordingly, the margin for the read operation of the memory device may be reduced, and the data input/output performance of the memory device could be improved.

2 FIG. illustrates a memory system according to an embodiment of the present disclosure.

2 FIG. 100 102 110 102 110 Referring to, the data processing systemmay include a hostengaged or coupled with a memory system, such as memory system. For example, the hostand the memory systemmay be coupled to each other via a data bus, a host cable, and the like, to perform data communication.

110 150 130 150 130 110 150 130 The memory systemmay include a memory deviceand a controller. The memory deviceand the controllerin the memory systemmay be considered components or elements physically separated from each other. The memory deviceand the controllermay be connected via at least one data path. For example, the data path may include a channel and/or a way.

150 130 150 130 130 130 150 130 According to an embodiment, the memory deviceand the controllermay be components or elements functionally divided. Further, according to an embodiment, the memory deviceand the controllermay be implemented with a single chip or a plurality of chips. The controllermay perform a data input/output operation in response to a request input from the external device. For example, when the controllerperforms a read operation in response to a read request input from an external device, data stored in a plurality of non-volatile memory cells included in the memory deviceis transferred to the controller.

2 FIG. 150 152 154 156 152 154 156 152 154 156 As shown in, the memory devicemay include a plurality of memory blocks,,. The memory blocks,,may be understood as a group of non-volatile memory cells in which data is removed together by a single erase operation. Although not illustrated, the memory block,,may include a page which is a group of non-volatile memory cells that store data together during a single program operation or output data together during a single read operation. For example, one memory block may include a plurality of pages.

150 For example, the memory devicemay include a plurality of memory planes or a plurality of memory dies. According to an embodiment, the memory plane may be considered a logical or a physical partition including at least one memory block, a driving circuit capable of controlling an array including a plurality of non-volatile memory cells, and a buffer that can temporarily store data input to, or output from, non-volatile memory cells.

130 130 In addition, according to an embodiment, the memory die may include at least one memory plane. The memory die may be understood to be a set of components implemented on a physically distinguishable substrate. Each memory die may be connected to the controllerthrough a data path. Each memory die may include an interface to exchange an item of data and a signal with the controller.

150 152 154 156 150 110 1 2 FIGS.and 2 FIG. According to an embodiment, the memory devicemay include at least one memory block,,, at least one memory plane, or at least one memory die. The internal configuration of the memory deviceshown inmay be different according to the configuration, performance, and/or design of the memory system. An embodiment of the present disclosure is not limited to the internal configuration shown in.

2 FIG. 150 170 152 154 156 170 152 154 156 170 152 154 156 170 170 152 154 156 170 Referring to, the memory devicemay include a voltage supply circuitcapable of supplying at least some voltage into the memory block,,. The voltage supply circuitmay supply a read voltage Vrd, a program voltage Vprog, a pass voltage Vpass, or an erase voltage Vers into a non-volatile memory cell included in the memory block. For example, during a read operation for reading data stored in the non-volatile memory cell included in the memory block,,, the voltage supply circuitmay supply the read voltage Vrd into a selected non-volatile memory cell. During the program operation for storing data in the non-volatile memory cell included in the memory block,,, the voltage supply circuitmay supply the program voltage Vprog into a selected non-volatile memory cell. Also, during a read operation or a program operation performed on the selected nonvolatile memory cell, the voltage supply circuitmay supply a pass voltage Vpass into a non-selected nonvolatile memory cell. During the erasing operation for erasing data stored in the non-volatile memory cell included in the memory block,,, the voltage supply circuitmay supply the erase voltage Vers into the memory block.

150 152 154 156 152 154 156 150 The memory devicemay store information regarding various voltages which are supplied to the memory block,,based on which operation is performed. For example, when a non-volatile memory cell in the memory block,,can store multi-bit data, plural levels of the read voltage Vrd for recognizing or reading the multi-bit data entry may be required. The memory devicemay include a table including information corresponding to plural levels of the read voltage Vrd, corresponding to the multi-bit data entry. For example, the table may include bias values stored in a register, each bias value corresponding to a specific level of the read voltage Vrd. The number of bias values for the read voltage Vrd that is used for a read operation may be limited to a preset range. Also, the bias values may be quantified (or quantized).

102 The hostmay include a portable electronic device, e.g., a mobile phone, an MP3 player, a laptop computer, etc., or a non-portable electronic device, e.g., a desktop computer, a game player, a television, a projector, etc.

102 102 102 110 110 102 The hostmay also include at least one operating system (OS), which may control functions and operations performed in the host. The OS may provide interoperability between the hostengaged operatively with the memory systemand a user who intends to store data in the memory system. The OS may support functions and operations corresponding to user's requests. By way of example but not limitation, the OS may be classified into a general operating system and a mobile operating system according to mobility of the host. The general operating system may be further classified into a personal operating system and an enterprise operating system according to system requirements or a user environment. As compared with the personal operating system, the enterprise operating systems can be specialized for securing and supporting high performance computing.

102 102 110 102 110 110 The mobile operating system may be subject to support services or functions for mobility, e.g., a power saving function. The hostmay include a plurality of operating systems. The hostmay execute multiple operating systems interlocked with the memory system, corresponding to a user's request. The hostmay transmit a plurality of commands corresponding to the user's requests into the memory system, thereby performing operations corresponding to the plurality of commands within the memory system.

130 110 150 102 130 150 102 102 150 130 A controllerin the memory systemmay control a memory devicein response to a request or a command input from the host. For example, the controllermay perform a read operation to provide data read from the memory deviceto the hostand may perform a write operation (or a program operation) to store data input from the hostin the memory device. In order to perform data input/output (I/O) operations, the controllermay control and manage internal operations of reading data, programming data, erasing data, or the like.

130 132 134 138 140 142 144 130 110 2 FIG. According to an embodiment, the controllermay include a host interface, a processor, an error correction circuitry (ECC), a power management unit (PMU), a memory interface (I/F), and a memory. Components included in the controlleras illustrated inmay vary according to structures, functions, operation performance, or the like, implemented in (or associated with, configured for) the memory system.

110 102 130 110 For example, the memory systemmay be implemented with any of various types of storage devices, which may be electrically coupled with the host, according to a protocol of a host interface. Non-limiting examples of suitable storage devices include a solid state drive (SSD), a multimedia card (MMC), an embedded MMC (eMMC), a reduced size MMC (RS-MMC), a micro-MMC, a secure digital (SD) card, a mini-SD, a micro-SD, a universal serial bus (USB) storage device, a universal flash storage (UFS) device, a compact flash (CF) card, a smart media (SM) card, a memory stick, and the like. Components may be added to or omitted from the controlleraccording to implementation of the memory system.

102 110 132 110 102 102 The hostand the memory systemeach may include a controller or an interface for transmitting and receiving signals, data, and the like, in accordance with one or more predetermined protocols. For example, the host interfacein the memory systemmay include an apparatus capable of transmitting signals, data, and the like to the hostor receiving signals, data, and the like from the host.

132 130 102 102 110 102 110 132 102 132 The host interfaceincluded in the controllermay receive signals, commands (or requests), and/or data input from the hostvia a bus. For example, the hostand the memory systemmay use a predetermined set of rules or procedures for data communication or a preset interface to transmit and receive data therebetween. Examples of sets of rules or procedures for data communication standards or interfaces supported by the hostand the memory systemfor sending and receiving data include Universal Serial Bus (USB), Multi-Media Card (MMC), Parallel Advanced Technology Attachment (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), Peripheral Component Interconnect Express (PCIe or PCI-e), Serial-attached SCSI (SAS), Serial Advanced Technology Attachment (SATA), Mobile Industry Processor Interface (MIPI), and the like. According to an embodiment, the host interfacemay be a type of layer for exchanging data with the hostand may be implemented with, or driven by, firmware such as a host interface layer (HIL). According to an embodiment, the host interfacemay include a command queue.

102 110 110 102 110 110 110 An Integrated Drive Electronics (IDE) interface or an Advanced Technology Attachment (ATA) interface may be used as one of the interfaces for transmitting and receiving data and, for example, may use a cable including 40 wires connected in parallel to support data transmission and data reception between the hostand the memory system. When a plurality of memory systemsare connected to a single host, the plurality of memory systemsmay be divided into a master and a slave by using a position or a dip switch to which the plurality of memory systemsare connected. The memory systemset as the master may be used as a main memory device. The IDE (ATA) may include, for example, Fast-ATA, ATAPI, or Enhanced IDE (EIDE).

102 102 102 102 110 102 102 110 102 A Serial Advanced Technology Attachment (SATA) interface is a type of serial data communication interface that is compatible with various ATA standards of parallel data communication interfaces which are used by Integrated Drive Electronics (IDE) devices. The 40 wires in the IDE interface can be reduced to six wires in the SATA interface. For example, 40 parallel signals for the IDE may be converted into 6 serial signals for the SATA interface. The SATA interface has been widely used because of its faster data transmission and reception rate and its less resource consumption in the hostused for data transmission and reception. The SATA interface may connect up to 30 external devices to a single transceiver included in the host. In addition, the SATA interface may support hot plugging that allows an external device to be attached to or detached from the host, even while data communication between the hostand another device is being executed. Thus, the memory systemcan be connected or disconnected as an additional device, like a device supported by a universal serial bus (USB) even when the hostis powered on. For example, in the hosthaving an eSATA port, the memory systemmay be freely attached to or detached from the hostin the manner of (attaching and detaching) an external hard disk.

102 110 102 110 102 102 Small Computer System Interface (SCSI) is a type of serial data communication interface used for connecting a computer or a server with other peripheral devices. The SCSI can provide a high transmission speed, as compared with other interfaces such as IDE and SATA. In (combined) systems that implement SCSI, the hostand at least one peripheral device (e.g., memory system) are connected in series, but data transmission and reception between the hostand each peripheral device may be performed through parallel data communication (or a parallel data connection). In the systems that implement SCSI, devices such as the memory systemmay be easily (for example, with stability and/or minimal processing or adjustment required) connected to or disconnected from the host. The SCSI can support connections of 15 other devices to a single transceiver included in host.

102 102 102 102 Serial Attached SCSI (SAS) may be understood to be a serial data communication version of the SCSI. In the SAS, the hostand a plurality of peripheral devices are connected in series, and data transmission and reception between the hostand each peripheral device may be performed (or executed) in a serial data communication scheme. The SAS may support connection between the hostand the peripheral device through a serial cable instead of a parallel cable, to easily (for example, in a timely manner without additional processes, protocol or devices, etc.) manage equipment using the SAS and enhance or improve operational reliability and communication performance. The SAS may support connections of eight external devices to a single transceiver included in the host.

102 110 102 110 110 The Non-volatile memory express (NVMe) is a type of interface based at least on a Peripheral Component Interconnect Express (PCIe) designed to increase performance and design flexibility of the host, servers, computing devices, and the like equipped with the non-volatile memory system. The PCIe may use a slot or a specific cable for connecting a computing device (e.g., host) and a peripheral device (e.g., memory system). For example, the PCIe may use a plurality of pins (e.g., 18 pins, 32 pins, 49 pins, or 82 pins) and at least one wire (e.g., x1, x4, x8, or x16) to achieve high speed data communication over several hundred MB per second (e.g., 250 MB/s, 500 MB/s, 984.6250 MB/s, or 1969 MB/s). According to an embodiment, the PCIe scheme may achieve bandwidths of tens to hundreds of Giga bits per second. The NVMe may support an operation speed of the non-volatile memory system, such as an SSD, that is faster than a hard disk.

102 110 102 110 102 According to an embodiment, the hostand the memory systemmay be connected through a universal serial bus (USB). The Universal Serial Bus (USB) is a type of scalable, hot-pluggable plug-and-play serial interface that can provide cost-effective standard connectivity between the hostand peripheral devices such as a keyboard, a mouse, a joystick, a printer, a scanner, a storage device, a modem, a video camera, and the like. A plurality of peripheral devices such as the memory systemmay be coupled to a single transceiver included in the host.

2 FIG. 138 150 150 150 150 130 150 150 138 138 150 138 Referring to, the error correction circuitrymay correct error bits of data read from the memory device, and may include an error correction code (ECC) encoder and an ECC decoder. The ECC encoder may perform error correction encoding of data to be programmed in the memory deviceto generate encoded data into which a parity bit is added, and store the encoded data in the memory device. The ECC decoder may detect and correct error bits contained in the data read from the memory devicewhen the controllerreads the data stored in the memory device. For example, after performing error correction decoding on the data read from the memory device, the error correction circuitrydetermines whether the error correction decoding has succeeded or not, and outputs an instruction signal, e.g., a correction success signal or a correction fail signal, based on a result of the error correction decoding. The error correction circuitrymay use a parity bit, which has been generated during the ECC encoding process for the data stored in the memory device, in order to correct the error bits of the read data entries. When the number of the error bits is greater than or equal to the number of correctable error bits, the error correction circuitrymay not correct the error bits and may instead output the correction fail signal indicating a failure in correcting the error bits.

138 138 According to an embodiment, the error correction circuitrymay perform an error correction operation based on a coded modulation such as a low density parity check (LDPC) code, a Bose-Chaudhuri-Hocquenghem (BCH) code, a turbo code, a Reed-Solomon (RS) code, a convolution code, a recursive systematic code (RSC), a trellis-coded modulation (TCM), a Block coded modulation (BCM), or the like. The error correction circuitrymay include all circuits, modules, systems, and/or devices for performing the error correction operation based on at least one of the above-described codes.

150 150 For example, the ECC decoder may perform hard decision decoding or soft decision decoding on data transmitted from the memory device. The hard decision decoding can be understood as one of two methods broadly classified for error correction. The hard decision decoding may include an operation of correcting an error bit by reading digital data of ‘0’ or ‘1’ from a non-volatile memory cell in the memory device. Because the hard decision decoding handles a binary logic signal, the circuit/algorithm design or configuration may be simpler than the soft decision decoding, and a processing speed may be faster than the soft decision decoding.

150 130 150 The soft decision decoding may quantize a threshold voltage of a non-volatile memory cell in the memory deviceby two or more quantized values, e.g., multiple bit data, approximate values, an analog value, and the like, in order to correct an error bit based on the two or more quantized values. The controllermay receive two or more alphabets or quantized values from a plurality of non-volatile memory cells in the memory device, and then perform a decoding based on information generated by characterizing the quantized values as a combination of information such as conditional probability or likelihood.

150 150 According to an embodiment, the ECC decoder may use a low-density parity-check and generator matrix (LDPC-GM) code among methods designed for the soft decision decoding. The low-density parity-check (LDPC) code uses an algorithm that can read values of data from the memory devicein several bits according to reliability, not simply data of 1 or 0 in the manner of the hard decision decoding, and iteratively repeats the process through a message exchange in order to improve reliability of the values. Then, the values are finally determined as data of 1 or 0. For example, a decoding algorithm using LDPC codes can be understood as probabilistic decoding. In the hard decision decoding, a value output from a non-volatile memory cell may be decoded as 0 or 1. Compared to the hard decision decoding, the soft decision decoding can determine the value stored in the non-volatile memory cell based on the stochastic information. Regarding bit-flipping which may be considered an error that can occur in the memory device, the soft decision decoding may provide improved probability of correcting the error and recovering data, as well as providing reliability and stability of corrected data. The LDPC-GM code may have a scheme in which internal LDGM codes can be concatenated in series with high-speed LDPC codes.

According to an embodiment, the ECC decoder may use, for example, low-density parity-check convolutional codes (LDPC-CCs) for the soft decision decoding. The LDPC-CCs may have a scheme using a linear time encoding and a pipeline decoding based on a variable block length and a shift register.

According to an embodiment, the ECC decoder may use, for example, a Log Likelihood Ratio Turbo Code (LLR-TC) for the soft decision decoding. A Log Likelihood Ratio (LLR) may be calculated as a non-linear function for a distance between a sampled value and an ideal value. In addition, a Turbo Code (TC) may include a simple code, for example, a Hamming code, in two or three dimensions and repeat decoding in a row direction and a column direction to improve reliability of values.

140 130 140 110 130 130 140 110 110 140 The power management unit (PMU)may control electrical power provided to the controller. The PMUmay monitor the electrical power supplied to the memory system, e.g., a voltage supplied to the controller, and provide the electrical power to components included in the controller. The PMUmay not only detect power-on or power-off, but also generate a trigger signal to enable the memory systemto urgently back up a current state when the electrical power supplied to the memory systemis unstable. According to an embodiment, the PMUmay include a device or a component capable of accumulating electrical power that may be used in an emergency.

142 130 150 130 150 102 142 150 150 134 150 The memory interface (I/F)may serve as an interface for handling commands and data transferred between the controllerand the memory device, in order to allow the controllerto control the memory devicein response to a command or a request input from the host. The memory interfacemay generate a control signal for the memory deviceand may process data input to, or output from, the memory deviceunder the control of the processorin a case when the memory deviceis a flash memory.

150 142 142 130 150 142 150 For example, when the memory deviceincludes a NAND flash memory, the memory interfaceincludes a NAND flash controller (NFC). The memory interfacecan provide an interface for handling commands and data between the controllerand the memory device. In accordance with an embodiment, the memory interfacecan be implemented through, or driven by, firmware called a Flash Interface Layer (FIL) for exchanging data with the memory device.

142 150 130 150 According to an embodiment, the memory interfacemay support an open NAND flash interface (ONFi), a toggle mode, or the like, for data input/output with the memory device. For example, the ONFi may use a data path (e.g., a channel, a way, etc.) that includes at least one signal line capable of supporting bi-directional transmission and reception in a unit of 8-bit or 16-bit data. Data communication between the controllerand the memory devicecan be achieved through at least one interface regarding an asynchronous single data rate (SDR), a synchronous double data rate (DDR), a toggle double data rate (DDR), or the like.

144 110 130 110 130 144 150 102 102 130 102 144 150 130 150 130 150 110 144 The memorymay be used as a working memory of the memory systemor the controller, while temporarily storing transactional data for operations performed in the memory systemand the controller. For example, the memorymay temporarily store read data entries output from the memory devicein response to a read request from the hostbefore the read data entries are output to the host. In addition, the controllermay temporarily store write data entries input from the hostin the memorybefore programming the write data entries in the memory device. When the controllercontrols operations, such as a data read operation, a data write or program operation, a data erase operation, etc., of the memory device, data transmitted between the controllerand the memory deviceof the memory systemmay be temporarily stored in the memory.

144 102 150 144 130 144 144 In addition to the read data entries or write data entries, the memorymay store information, e.g., map data, read requests, program requests, etc. used for inputting or outputting data between the hostand the memory device. According to an embodiment, the memorymay include one or more of a command queue, a program memory, a data memory, a write buffer/cache, a read buffer/cache, a data buffer/cache, a map buffer/cache, and so on. The controllermay allocate some storage space in the memoryfor a component which is established to carry out a data input/output operation. For example, the write buffer established in the memorymay be used to temporarily store target data subject to a program operation.

144 144 144 130 144 130 144 144 130 2 FIG. In an embodiment, the memorymay be implemented with a volatile memory. For example, the memorymay be implemented with a static random access memory (SRAM), a dynamic random access memory (DRAM), or both. Althoughillustrates, for example, the memorydisposed within the controller, embodiments are not limited thereto. The memorymay be located within or external to the controller. For instance, the memorymay be embodied by an external volatile memory having a memory interface transferring data and/or signals between the memoryand the controller.

134 110 134 150 102 134 110 134 3 4 FIGS.and The processormay control the overall operations of the memory system. For example, the processormay control a program operation or a read operation of the memory devicein response to a write request or a read request entered from the host. According to an embodiment, the processormay execute firmware to control the program operation or the read operation in the memory system. Herein, the firmware may be referred to as a flash translation layer (FTL). An example of the FTL will be described in detail, referring to. According to an embodiment, the processormay be implemented with a microprocessor, a central processing unit (CPU), or the like.

110 110 110 According to an embodiment, the memory systemmay be implemented with at least one multi-core processor. The multi-core processor is a type of circuit or chip in which two or more cores, which are considered distinct processing regions, are integrated. For example, when a plurality of cores in the multi-core processor drive or execute a plurality of flash translation layers (FTLs) independently, a data input/output speed (or performance) of the memory systemmay be improved. According to an embodiment, the data input/output (I/O) operations in the memory systemmay be independently performed through different cores in the multi-core processor.

134 130 102 110 102 130 102 130 102 130 150 102 102 130 The processorin the controllermay perform an operation corresponding to a request or a command input from the host. Further, the memory systemmay perform an operation independent from a command or a request input from the host. In one case, an operation performed by the controllerin response to the request or the command input from the hostmay be considered a foreground operation, while an operation performed by the controllerindependently from the request or the command input from the hostmay be considered a background operation. The controllermay perform foreground or background operations for reading, writing, or erasing data in the memory device. In addition, a parameter set operation corresponding to a set parameter command or a set feature command as a set command transmitted from the hostmay be considered a foreground operation. Background operations that can be performed without a command transmitted from the hostby the controllerinclude garbage collection (GC), wear leveling (WL), bad block management for identifying and processing bad blocks, or the like.

110 102 110 102 According to an embodiment, substantially similar operations may be performed as both the foreground operation and the background operation. For example, when the memory systemperforms garbage collection in response to a request or a command input from the host(e.g., Manual GC), the garbage collection can be considered a foreground operation. When the memory systemperforms garbage collection independently of the host(e.g., Auto GC), the garbage collection can be considered a background operation.

150 130 102 110 150 142 130 150 130 110 110 When the memory deviceincludes a plurality of dies (or a plurality of chips) each including a plurality of non-volatile memory cells, the controllermay perform parallel processing regarding plural requests or commands input from the hostin order to improve performance of the memory system. For example, the transmitted requests or commands may be divided into plural groups including at least some of a plurality of planes, a plurality of dies, or a plurality of chips included in the memory device, and the plural groups of requests or commands may be processed individually or in parallel in each plane, each die or each chip. The memory interfacein the controllermay be connected to the plurality of dies or chips in the memory devicethrough at least one channel and at least one way. When the controllerdistributes and stores data in the plurality of dies through each channel or each way in response to requests or commands associated with a plurality of pages including non-volatile memory cells, a plurality of operations corresponding to the requests or the commands can be performed simultaneously or in parallel in the plurality of dies or planes. Such a processing method or scheme can described as an interleaving method. Because a data input/output speed of the memory systemincreases by operating with the interleaving method, data I/O performance of the memory systemcan be improved.

130 150 130 130 150 150 130 By way of example but not limitation, the controllermay recognize statuses of a plurality of channels (or ways) associated with the plurality of dies included in the memory device. The controllermay determine a status of each channel or each connection as one of a busy status, a ready status, an active status, an idle status, a normal status, and an abnormal status. The determination of which channel or connection an instruction (and/or a data) is delivered through by the controller can be associated with a physical block address. The controllermay refer to descriptors delivered from the memory device. The descriptors may include a block or page of parameters describing something about the memory device. The descriptors can have a predetermined format or structure. For instance, the descriptors may include device descriptors, configuration descriptors, unit descriptors, and the like. The controllermay refer to, or use, the descriptors to determine which channel(s) or way(s) is used to exchange an instruction or data.

2 FIG. 150 110 152 154 156 152 154 156 152 154 156 152 154 156 Referring to, the memory devicein the memory systemmay include a plurality of memory blocks,,. Each of the plurality of memory blocks,,includes a plurality of non-volatile memory cells. According to an embodiment, the memory block,,can be a group of non-volatile memory cells erased together. The memory block,,may include a plurality of pages which is a group of non-volatile memory cells read or programmed together.

152 154 156 150 152 154 156 150 110 According to an embodiment, each memory block,, ormay have a three-dimensional stack structure for a high integration. Further, the memory devicemay include a plurality of dies, each die including a plurality of planes, each plane including the plurality of memory blocks,,. A configuration of the memory devicemay be changed depending on performance of the memory system.

2 FIG. 150 152 154 156 152 154 156 illustrates the memory devicethat includes the plurality of memory blocks,, and. The plurality of memory blocks,, andmay be any of single-level cell (SLC) memory blocks, multi-level cell (MLC) memory blocks, or the like, according to the number of bits that can be stored in one memory cell. An SLC memory block includes a plurality of pages implemented by memory cells, each memory cell storing one bit of data. An SLC memory block may have higher data I/O operation performance and higher durability than the MLC memory block. The MLC memory block includes a plurality of pages implemented by memory cells, each memory cell storing multi-bit data, e.g., two or more bits of data. The MLC memory block may have larger storage capacity for the same space compared to the SLC memory block. The MLC memory block can be highly integrated in a view of storage capacity.

150 150 According to an embodiment, the memory devicemay be implemented with MLC memory blocks such as a double level cell (DLC) memory block, a triple-level cell (TLC) memory block, a quadruple-level cell (QLC) memory block, and a combination thereof. The DLC memory block may include a plurality of pages implemented by memory cells, each memory cell capable of storing 2-bit data. The TLC memory block can include a plurality of pages implemented by memory cells, each memory cell capable of storing 3-bit data. The QLC memory block may include a plurality of pages implemented by memory cells, each memory cell capable of storing 4-bit data. In another embodiment, the memory devicemay be implemented with a block including a plurality of pages implemented by memory cells, each memory cell capable of storing five or more bits of data.

130 150 130 130 110 According to an embodiment, the controllermay use an MLC memory block included in the memory deviceas an SLC memory block that stores one-bit data in one memory cell. A data input/output speed of the multi-level cell (MLC) memory block can be slower than that of the SLC memory block. That is, when the MLC memory block is used as the SLC memory block, a margin for a read or program operation can be reduced. For example, the controllermay perform a data input/output operation with a higher speed when the MLC memory block is used as the SLC memory block. Thus, the controllermay use the MLC memory block as a SLC buffer to temporarily store data because the buffer may require a high data input/output speed for improving performance of the memory system.

130 150 130 130 Further, according to an embodiment, the controllercan program data in an MLC a plurality of times without performing an erase operation on a specific MLC memory block included in the memory device. In general, non-volatile memory cells do not support data overwrite. However, the controllermay program 1-bit data in the MLC a plurality of times using a feature in which the MLC is capable of storing multi-bit data. For an MLC overwrite operation, the controllermay store the number of program times as separate operation information when 1-bit data is programmed in an MLC. According to an embodiment, an operation for uniformly levelling threshold voltages of the MLCs may be carried out before another 1-bit data is programmed in the same MLCs, each having stored 1-bit data.

150 150 According to an embodiment, the memory devicemay be embodied as a non-volatile memory such as a flash memory, for example, a NAND flash memory, a NOR flash memory, or the like. In another embodiment, the memory devicemay be implemented by at least one of a programmable ROM (PROM), an erasable ROM (EPROM), an electrically erasable ROM (EEPROM), a phase change RAM (PRAM), a magnetic RAM (MRAM), a Resistive RAM (RRAM) a phase change random access memory (PCRAM), a ferroelectrics random access memory (FRAM), a spin transfer torque random access memory (STT-RAM), and a spin transfer torque magnetic random access memory (STT-MRAM), or the like.

3 FIG. 3 FIG. 2 FIG. 300 300 150 illustrates a memory deviceaccording to an embodiment of the present disclosure. The memory devicedescribed incan be understood as an example of the memory devicedescribed in.

3 FIG. 2 FIG. 300 300 300 130 Referring to, the memory devicecan include at least one memory die. The memory devicecan receive or output a plurality of control signals chip enable CE #, command latch enable CLE, address latch enable ALE, write enable WE #, read enable RE #, write protect WP #, ready/busy R/B #, and receive or transmit data or operation information through channels I/O [7:0], I/O [15:0]. For example, a predetermined amount of data (e.g., 1 byte (8 bits) or 2 bytes (16 bits)) can be transmitted and received according to a channel (e.g., I/O [7:0], I/O [15:0]) connecting the memory deviceand a controller such as the controllershown in.

300 310 300 According to an embodiment, the memory devicemay include a plurality of pins or pads. For example, the plurality of control signals CE #, CLE, ALE, WE #, RE #, WP #, R/B #can be transmitted or received through exclusively allocated pins. The control signals may include a chip enable signal CE #, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal WE #, a read enable signal RE #, a write protect signal WP #, a status signal R/B #indicating a ready state or a busy state, and the like. The control signals CE #, CLE, ALE, WE #, RE #, WP #, R/B #can be controlled (transmitted and received) by control circuitryincluded in the memory device.

310 300 310 300 130 300 310 130 310 2 FIG. A control circuitmay perform preset operation mechanisms in response to commands and addresses input to the memory device. For example, when a read command is received, the control circuitmay manage and control components in the memory deviceto sequentially perform operations or tasks corresponding to the read command. In addition, when the controllerdescribed intransmits a command to check an operation status of the memory device, the control circuitmay check information regarding the operation status and output the information to the controller. The control circuitmay be configured to perform an operation or task corresponding to a specific command or a specific interrupt according to a preset procedure in response to an input command or the interrupt, and then transmit a result of the operation or task.

300 320 320 320 300 372 374 376 340 330 The memory devicecan include an input and output (input/output (I/O)) control circuit. The input/output control circuitcan be connected to other devices or components (e.g., a controller) through the channels I/O [7:0], I/O [15:0]. The input/output control circuitin the memory devicecan be coupled to a plurality of registers,,and a cache registercoupled to a cell array.

320 300 According to an embodiment, the input/output control circuitcan include a chip select decoder, while the memory devicemay include a plurality of memory chips. Chip select function may be used to activate one of the plurality of memory chips included in or connected to a memory system or a data processing system. Depending on the embodiment, the chip select decoder may be implemented with combinational logic gates that activate one specific output line in response to an input binary code. The memory system or the data processing system can use an activated output line to activate or “select” a specific chip or device from multiple devices connected to the memory system or the data processing system. For example, if there are multiple memory chips on a same bus (such as flash memory chips in solid state drives (SSDs)), for most operations it is impossible to communicate with all memory chips simultaneously because data entries or commands sent across the bus could be routed to all memory chips. Instead, a chip select signal can be used to select which chip to communicate with at any given time. The chip select decoder can manage and control data communication between multiple devices (e.g., the multiple memory chips) that share the same bus or connection lines in a system by activating one specific device based on an input select code or signal.

300 340 372 374 376 340 300 340 330 300 340 372 330 376 300 374 300 300 374 320 300 310 According to an embodiment, the memory devicecan include the cache register, an address register, a status information register, and a command register. The cache registercan temporarily store data. When the memory deviceperforms a read operation, the cache registercan store a read data entry output from the cell array. When the memory deviceperforms a write operation or a program operation, the cache registercan store a write data entry. The address registercan store an address indicating a location of the cell arraywhere a read operation or a write operation is to be performed. The command registercan store a command to be executed by the memory device. The status information registercan store status information such as a result (failure/success) of an operation performed in the memory deviceor readiness for performing an operation. For example, when a plurality of memory planes is included in a memory die in the memory device, the status information registercan store status information regarding each of the plurality of memory planes. Data, commands, and information transmitted or received through the input/output control circuitin the memory devicecan be controlled (e.g., transmitted, moved, or output) by the control circuitry.

300 334 332 330 372 310 330 338 338 340 340 320 320 During a read operation in the memory device, a row decoderand a column decodercan select one or more memory cells in the cell arraybased on an address stored in the address registerand a control signal from the control circuitry. During a read operation, a read data entry output from the cell arraymay be stored in the data registerand then transferred from the data registerto the cache register. The read data entry stored in the cache registermay be transferred to the input/output control circuitthrough input/output lines. The read data entry transmitted to the input/output control circuitmay be output to the controller through the channels I/O [7:0], I/O [15:0].

300 334 332 330 372 310 320 340 340 338 338 330 310 During a write operation or a program operation in the memory device, the row decoderand the column decodercan select one or more memory cells in the cell arrayin response to an address stored in the address registerand a control signal from the control circuitry. During the write operation, the write data entry transferred from the controller to the input/output control circuitthrough the channels I/O [7:0], I/O [15:0] can be stored in the cache register. Thereafter, the write data entry may be transferred from the cache registerto the data register. The write data entry stored in the data registercan be programmed in selected memory cells in the cell arrayby the control circuitry.

338 340 300 338 340 340 338 320 340 The data registerand the cache registercan be included in a read/write circuit comprising a sense amplifier, a page buffer, or the like. According to an embodiment, page buffers or data latches included in the memory devicecan correspond to the data registerand/or the cache register. Further, the cache registeris configured to temporarily store data transmitted between the data registerand the input/output control circuit. The cache registermay have a pipe latch structure depending on the embodiment.

320 340 300 A pipeline (or pipelining) system including at least one pipe latch can include an apparatus that can parallelize a plurality of data entries input and output serially. According to an embodiment, the pipeline system is applicable to the input/output control circuitor the cache register. Further, according to an embodiment, the pipeline system may be used to compensate for delays and noise occurring in a data transmission process as a data path through which data is transmitted within the memory deviceof the memory system becomes longer.

330 330 330 3 FIG. The cell arrayshown incan have a two-dimensional or three-dimensional structure. Hereinafter, various structures of the cell arrayand an operation for programming data or verifying programmed data in a plurality of memory cells included in the cell arraywill be specifically described.

4 FIG. 330 illustrates a structure of a first cell arrayA according to an embodiment of the present disclosure.

4 FIG. 330 0 1 7 0 1 7 0 1 7 0 1 7 Referring to, the first cell arrayA can include a plurality of cell strings SG, SG, . . . , SG. The plurality of cell strings SG, SG, . . . , SGcan be coupled to a bit line BL. The connection between each of the plurality of cell strings SG, SG, . . . , SGand the bit line BL can be determined through (each of corresponding) drain select lines DSL, DSL, . . . , DSL.

0 1 7 0 0 Among the plurality of cell strings SG, SG, . . . , SG, a first cell string SGcan include a plurality of memory cells, each memory cell capable of storing one-bit data or multi-bit data, a switching transistor coupled to a first drain select line DSL, and a switching transistor coupled to a source select line SSL for controlling connection to a source line SL. According to an embodiment, each switching transistor can include plural transistors.

180 330 Plural memory cells can be coupled to plural word lines Main_WL. A single memory cell can be connected to a single word line among the plural word lines Main_WL. Based on the bit line BL and one of the plural word lines Main_WL, the control circuitrycan select a specific memory cell in a selected cell string within the first cell arrayA.

0 1 7 0 1 7 330 0 7 0 1 7 0 170 7 170 0 1 7 For example, the word line Main_WL can be coupled to one memory cell included in each of the plurality of cell strings SG, SG, . . . , SG. As the number of the plurality of cell strings SG, SG, . . . , SGcoupled to the word line Main_WL increases, the data storage capacity of the first cell arrayA can increase. Due to a delay (e.g., RC delay, etc.), voltages of various levels transmitted through the word line Main_WL can reach the first cell string SGand the eighth cell string SGat different times. As the number of the plurality of cell strings SG, SG, . . . , SGcoupled to the word line Main_WL increases, the times at which the voltage is applied to a cell string (e.g., the first cell string SG) closest to the voltage supply circuitand a cell string (e.g., the eighth cell string SG) farthest from the voltage supply circuitcan differ more significantly. According to an embodiment of the present disclosure, a memory device and an operating method of the memory device capable of avoiding or resolving an issue caused based on a phenomenon that the times differ at which the voltage is applied to each of the plurality of cell strings SG, SG, . . . , SGcoupled to the word line Main_WL will be described below.

5 FIG. 330 illustrates a structure of a second cell arrayB according to an embodiment of the present disclosure.

5 FIG. 330 1 330 1 2 3 2 3 1 2 3 Referring to, the second cell arrayB can have a structure including portions or layers stacked in a vertical direction D. The second cell arrayB can include at least one memory block. Hereinafter, a direction substantially perpendicular to the upper surface of the substrate may be defined as a first direction D, and two directions parallel to the upper surface of the substrate and intersecting each other may be defined as the second direction Dand the third direction D, individually. For example, the second direction Dand the third direction Dmay intersect each other substantially perpendicularly. The first direction Dmay be referred to as a vertical direction, the second direction Dmay be referred to as a row direction, and the third direction Dmay be referred to as a column direction. The direction indicated by the arrow in the drawing and the direction opposite to it are described as the same direction.

5 FIG. 1 For convenience of description,shows NAND strings or cell strings SGto SGk connected to one bit line BL and one common source line CSL among the cell strings included in the memory block.

1 1 0 1 1 2 3 The memory block may include a plurality of cell strings SGto SGk connected between the same bit line (BL) and the common source line CSL. Each of the cell strings SGto SGk can include at least one source select transistor SST controlled by a source select line SSL, plural memory cells controlled by word lines WL (shown as WL, WL, WL(n−1), WLn, WL(n+1), WL(n+2), WL(q−1), and WLq), a central switching transistor CST disposed in an intermediate boundary layer IBL and controlled by a central switching word line CSWL, and a drain select transistor DST controlled by each drain select line DSL, DSL, DSL, . . . , DSLK.

1 2 1 1 2 330 5 FIG. According to an embodiment, plural memory cells connected to at least one word line located at both ends of first and second stacks ST, STin the first direction Dmay be dummy cells. Any data may not be stored in the dummy cells. Further, according to an embodiment, the dummy cells may be used to store data having a smaller number of bits than other memory cells. According to an embodiment, the intermediate boundary layer IBL may include at least one gate line. One gate line corresponds to the central switching word line CSWL which can simultaneously control switching operations of the central switching transistors CST connected thereto. Althoughillustrates a structure in which the first and second stacks ST, STare stacked, three or more stacks may be vertically stacked in the second cell arrayB. When a plurality of stacks are stacked, an intermediate boundary layer IBL may be formed and disposed between each two stacked stacks. The intermediate boundary layer IBL may include at least one switching transistor configured to couple memory cells in one stack of the two stacks to other memory cells in the other stack.

5 FIG. 1 shows an embodiment in which the source select transistors SST included in the plurality of cell strings SGto SGk are connected to the common select line CSL. However, according to an embodiment, a certain (for example, predetermined) number of source select transistors may be coupled to each of plural source ground select lines.

4 5 FIGS.to 3 FIG. 330 330 1 2 3 310 300 310 Referring to, the first or second cell arrayA,B can include a plurality of memory blocks arranged along a plurality of directions D, D, D. In an embodiment, a memory block may be selected by the control circuitincluded in the memory deviceshown in. For example, a read voltage, a program voltage, or an erase voltage may be applied to a memory block and a word line selected by the control circuit.

1 1 1 5 FIG. Each of the cell strings SGto SGk may include a plurality of switch transistors as well as a plurality of memory cells capable of storing data. Here, the plurality of switch transistors can include a drain select transistor DST, a source select transistor SST, and a central switching transistor CST.shows an embodiment in which each of the cell strings SGto SGK includes one drain select transistor DST, one source select transistor SST, and one central switching transistor CST, respectively. However, according to an embodiment, each of the cell strings SGto SGk may include a plurality of drain select transistors DST, a plurality of source select transistors SST, or a plurality of intermediate switching transistors CST.

6 FIG. 330 illustrates a structure of a third cell arrayC according to an embodiment of the present disclosure.

5 6 FIGS.and 5 FIG. 6 FIG. 330 1 1 2 330 Referring to, the third cell arrayC may be stacked in the vertical direction (D, Z) through a plurality of stacks ST, ST, as described in, and non-volatile memory cells can be placed in three-dimensional (3D) space. Specifically,illustrates the third cell arrayC in a 3D non-volatile memory device according to an embodiment of the present disclosure.

330 1 2 3 1 2 3 1 2 3 330 1 4 1 4 1 1 2 3 1 2 3 1 4 1 1 4 1 4 The third cell arrayC may include a plurality of memory cells MC arranged in a cell string STR in a plurality of memory layers (e.g., three memory layers L, L, L). The memory layers L, L, Lmay be respectively connected to a plurality of bit lines BL, BL, BLthrough a first end of the plurality of channel lines CL and to the common source line CSL through a second end of the plurality of channel lines CL. The third cell arrayC may include a plurality of source select lines SSLto SSLconnected to source select transistors SSTto SST. In addition, a plurality of word lines WLto WLn and a ground select line GSL (illustrated as, respectively, GSL, GSL, GSL) may be connected to each of the memory layers L, L, L. The plurality of source select lines SSLto SSL, the plurality of word lines WLto WLn, and the ground select line GSL may be arranged in a direction that intersects a plurality of channel lines CL. Each of the plurality of channel lines may be described as the cell string STR. Each of the cell strings STR may include the source select transistors SSTto SSTrespectively connected to the plurality of source select lines SSLto SSL. The ground select line GSL may be grounded to turn off the ground selection transistor GST.

1 1 3 1 The plurality of word lines WLto WLn may each be connected to control gates of memory cells arranged in a column direction. Each of the plurality of bit lines BLto BLmay be connected to one end of the source select transistors. A plurality of memory cells having control gate electrodes connected to each word line WLto WLn in the row direction can configure a page, which is a unit for storing data or a data entry. The number of pages could be changed or determined depending on a storage capacity of the memory cells.

7 FIG. illustrates a memory device according to an embodiment of the present disclosure.

1 FIG. 7 FIG. 346 348 346 248 346 348 Referring toand, the memory device can form different current paths in the memory celland the page buffer. A cell current (e.g., Cell Current) can flow through the memory cell, and a page buffer current (e.g., PB Current) can flow in the page buffer. The memory device can include a current mirror between the memory celland the page buffer.

7 FIG. illustrates a case where the current gain is 4 times so that the page buffer current (e.g., PB Current) can be compensated for a reduction rate (i.e., ¼) of the cell current (e.g., Cell Current). By generating the page buffer current (e.g., PB Current) in the evaluation period (approximately up to 600 ns) during the read process, the size of the consumption current (Icc) representing the current consumption in the NAND flash memory could be reduced. The current gain (A) of the current mirror can be defined as follows.

2 2 1 1 The widths (W) and lengths (L) of the channels of the transistors constituting the current mirror can affect the current gain. For example, the larger the width/length (W/L) ratio of the transistor, the greater the current flow capability of the transistor. When the width/length (W/L) ratios of the input transistor and the output transistor included in the current mirror are different, the output current might not be the same as the input current. When the width/length (W/L) ratio of the output transistor is larger than the width/length (W/L) ratio of the input transistor, the output current could be larger than the input current as follows.

7 FIG. 348 The current mirror described incan generate the page buffer current (e.g., PB Current) that is four times the cell current (e.g., Cell Current), so that the page buffercan secure an operating margin due to the increased page buffer current (e.g., PB Current).

7 FIG. Herein, the current mirror is a circuit for creating or generating a constant current source, and has a function of outputting an arbitrary input current or reference current 1 to 1 or 1 to N times. The performance of the current mirror can be determined by a current output terminal with infinite impedance, a current up-conversion terminal with zero impedance, and an ability/capability to replicate current 1 to 1 and amplify arbitrary current. The current mirror described incan have a high input impedance and a low output impedance, and therefore may have a disadvantage in that it may not be capable of performing high-precision current replication and amplification. According to an embodiment, the memory device can include a Wilson current mirror and a regulated cascade current mirror to increase the output impedance.

8 FIG. 8 FIG. 7 FIG. illustrates a memory device according to an embodiment of the present disclosure.illustrates one example of the current mirror described in.

8 FIG. Referring to, the current mirror can include two P-channel metal-oxide-semiconductor (PMOS) transistors having one side connected to a power supply voltage VCORE. The current gain of the current mirror can be (the value) “α”. For example, the gain may be expressed as

7 FIG. similarly as described with respect to the current mirror of.

The page buffer current (e.g., PB Current) copied through the current mirror can be generated only in the evaluation period (Eval.). At this time, the switch SW located on the output side of the current mirror can be turned on, and the page buffer current (e.g., PB Current) can flow in the sensing line SO. The switch SW can be turned off before the evaluation period (Eval.), e.g., a precharge period, and after the evaluation period (Eval.), e.g., a sensing period. After the evaluation section (Eval.), the sensing line SO can be kept in a floating state at its potential because the connection between the current mirror and the sensing line SO is electrically cut off.

The potential of the sensing line SO can be different during an erase operation and a program operation. Due to the current mirror including two PMOS transistors having one side connected to the power supply voltage VCORE, the potential (ERS) of the sensing line SO during the erase operation could be higher than the potential (PGM) of the sensing line SO during the program operation.

9 FIG. 9 FIG. 7 FIG. illustrates a memory device according to an embodiment of the present disclosure.illustrates one example of the current mirror described in.

9 FIG. Referring to, the current mirror can include two N-channel metal-oxide-semiconductor (NMOS) transistors having on side connected a ground voltage GND. The current gain of the current mirror can be the value “α”, which may be a whole number or any number greater than 1.

The page buffer current (e.g., PB Current) copied through the current mirror can be generated only in the evaluation period (Eval.). During this period, the switch SW located on the output side of the current mirror may be turned on, and the page buffer current (e.g., PB Current) may flow through the sensing line SO. The switch SW may be turned off before the evaluation period (Eval.), e.g., the precharge period, and after the evaluation period (Eval.), e.g., the sensing period. After the evaluation section (Eval.), the sensing line SO can be maintained in a floating state because the connection between the current mirror and the sensing line SO is electrically cut off.

The sensing line SO may have different potentials during the erase operation and the program operation. Due to the current mirror including two NMOS transistors having one side connected to the ground voltage GND, the potential (ERS) of the sensing line SO during the erase operation can be lower than the potential (PGM) of the sensing line SO during the program operation.

Further, when the memory device includes a current mirror including two NMOS transistors having one side connected to the ground voltage GND, the memory device may have an advantage of reducing a consumption current (Icc) compared to the current mirror including two PMOS transistors having one side connected to the power supply voltage VCORE.

10 FIG. 10 FIG. 7 FIG. illustrates a memory device according to an embodiment of the present disclosure.illustrates one example of the current mirror described in.

10 FIG. 1 2 1 2 1 2 Referring to, the current mirror can include two inductors L, Lconnected to one side of a power supply voltage VCORE. The current gain of the current mirror can be the value “α”. The inductors L, Lmay be components that form a magnetic field when current flows and have the property of resisting changes in current. The inductors L, Lmay be implemented in the form of a wire in which at least a part of a bit line BL connected to a memory cell and a sensing line SO connected to a page buffer are wound in a coil shape. When the current mirror uses an inductor, there is no need to additionally place a transistor in the memory device.

The page buffer current (e.g., PB Current) copied through the current mirror can be generated only in the evaluation section (Eval.). During this period, the switch SW located on the output side of the current mirror is turned on, and the page buffer current (e.g., PB Current) can flow through the sensing line SO. The switch SW can be turned off before the evaluation period (Eval.), e.g., the precharge period, and after the evaluation period (Eval.), e.g., the sensing period. After the evaluation period (Eval.), the sensing line SO can be maintained in a floating state with a potential because the connection between the current mirror and the sensing line SO is electrically cut off.

11 FIG. illustrates a memory device according to an embodiment of the present disclosure.

11 FIG. 7 10 FIGS.to 544 546 548 544 548 544 Referring to, the memory device can include a current mirrorbetween a memory cell regionand a page buffer. The current mirrorcan generate a page buffer current (e.g., PB Current) flowing through the page bufferin response to a cell current (e.g., Cell Current) flowing through a bit line BL. As described in, the current mirrormay have a preset current gain.

544 544 According to an embodiment, the current mirrormay have different current gains and operation times during a read operation and a program operation for at least one memory cell. In addition, the current gain of the current mirrorcan be determined during a post-manufacturing test process.

544 544 544 544 544 546 548 According to an embodiment, the memory device may further include a switching element that directly connects the input side and the output side of the current buffer. The switching element can be turned on or off in response to the detection control signal SASENSE. For example, during a read operation, the memory device can turn off the switching element and generate a page buffer current (e.g., PB Current) through the current mirror. On the other hand, during a write operation, the memory device can turn on the switching element and electrically disconnect the connection of the current mirror. Meanwhile, according to an embodiment, the operation of the switching element can be determined through a post-manufacturing test process. In addition, according to an embodiment, the current gain of the current mirrorcan be made different during a read operation and a program operation for at least one memory cell, or a connection time between the current mirrorand the memory cell areaor the page buffermay be made different.

546 In addition, according to an embodiment of the present disclosure, the current gain of the current mirror can vary depending on the wear degree of at least one memory cell in the memory cell area.

Hereinafter, the operation and configuration of the memory device will be described with a focus on the read operation.

546 A plurality of memory cells in the memory cell areamay be connected to the bit line BL. At least one of the plurality of bit lines can be selected by a bit line selection signal SELBL.

544 The memory device connects the bit line BL to the current mirrorthrough the page buffer detection signal PBSENSE. According to an embodiment, a switching element operated by the detection control signal SASENSE can be turned off during a read operation.

544 In a conventional memory device, the bit line BL is directly connected to the sensing line SO through the page buffer detection signal PBSENSE. However, the bit line BL and the sensing line SO in the memory device according to an embodiment of the present disclosure can be indirectly connected through the current mirror. The memory device can have different and distinguishable current paths in the bit line BL and the sensing line SO.

546 In response to a precharge signal BLPRECH_N, the memory device can precharge the bit line BL. After the bit line BL is precharged to a preset level based on the precharge signal BLPRECH_N, the cell current (e.g., Cell Current) can be determined when a read voltage is applied to a memory cell in the memory cell area.

The sensing line SO can be precharged to a preset level in response to a detection precharge signal SA_PRE_N.

544 544 In response to an evaluation signal EVAL_N, the memory device can connect the current mirrorto the sensing line SO. In response to the evaluation signal EVAL_N, the page buffer current (e.g., PB Current) generated in the current mirrorcan flow through the sensing line SO.

548 The page buffercan transfer a potential of the sensing line SO to a latch internally in response to a detection discharge signal SA_DISCH.

548 548 548 548 340 320 3 FIG. The page buffercan include a latch structure capable of storing data in two nodes QS, QS_N. During a read operation, a binary value determined by detecting a page buffer current (i.e., PB Current) can be stored in the two nodes QS, QS_N in the page buffer. The two nodes QS, QS_N in the page buffercan be initialized through a page buffer reset signal PBRST, a set signal SSET, and a reset signal SRST before storing data and after outputting the data. The data temporarily stored in the two nodes QS, QS_N in the page buffercan be transferred to another component (e.g., a cache register, an input/output control circuit, shown in) in the memory device in response to a data output signal TRANS_N.

12 FIG. 11 FIG. 12 FIG. 11 FIG. 544 illustrates an operation of the memory device described in. Specifically,describes the read operation using the current mirrorin the memory device described in.

12 FIG. Referring to, the memory cell can have one of the erase state (ERASE) and the program state (PGM). According to an embodiment, the memory cell can store multi-bit data. However, for the convenience of explanation, the memory cell having only the two cases of the erase state (ERASE) and the program state (PGM) are described as an example.

The read operation can include a bit line precharge period (BL Precharge), an evaluation period (Evaluation), and a sensing period (Sensing). According to an embodiment, the evaluation period (Evaluation) during the read operation can be set as an initial period of the sensing period (Sensing).

11 12 FIGS.and 544 546 544 546 546 546 Referring to, when the page buffer detection signal PBSENSE and the precharge signal BLPRECH_N can be applied during a read operation, the bit line BL and the current mirrorcan be connected. When a read voltage and a pass voltage, etc. are applied through a plurality of word lines connected to a plurality of memory cells in a memory cell area, a cell current (e.g., Cell Current) can flow from the current mirrorto the memory cell area. For example, when a memory cell to which a read voltage is applied in the memory cell areais in an erase state (ERASE), the cell current (e.g., Cell Current) can flow at about 50 nA. On the other hand, when a memory cell to which a read voltage is applied in the memory cell areais in a program state (PGM), a cell current (e.g., Cell Current) can flow at about 5 nA.

544 546 546 The current mirrorcan generate a page buffer current (e.g., PB Current) that is four times the cell current (e.g., Cell Current) in response to a preset current gain (e.g., four times). For example, when a memory cell to which a read voltage is applied in the memory cell areais in an erase state (ERASE), the page buffer current (e.g., PB Current) of 200 nA can be generated in response to the cell current (e.g., Cell Current) of 50 nA. On the other hand, when a memory cell to which a read voltage is applied in the memory cell areais in a program state (PGM), the page buffer current (e.g., PB Current) of 20 nA can be generated in response to the cell current (e.g., Cell Current) of 5 nA.

544 546 546 The evaluation signal EVAL_N can be activated during the evaluation period (Evaluation) between the bit line precharge period (BL Precharge) and the sensing period (Sensing). The potential of the sensing line SO can rise by the page buffer current (e.g., PB Current) generated by the current mirror. The potential of the sensing line SO can rise in response to the page buffer current (e.g., PB Current) of 200 nA when the memory cell to which the read voltage is applied in the memory cell areais in the erase state (ERASE). On the other hand, the potential can rise in response to the page buffer current (e.g., PB Current) of 20 nA when the memory cell to which the read voltage is applied in the memory cell areais in the program state (PGM). The potential of the sensing line SO can be distinguishable in response to an amount of the page buffer current (e.g., PB Current).

548 548 548 548 546 548 546 548 The page buffercan be initialized by a detection discharge signal SA_DISCH and a reset signal SRST. The page buffercan sense data in response to the potential of the sensing line SO. The node (QS) in the page buffercan be initialized to a logical high level (e.g., 1.9 V). In the sensing period (Sensing) after the evaluation period (Evaluation), a determination whether the node (QS) in the page bufferflips in response to the potential of the sensing line SO is made. For example, when a memory cell to which a read voltage is applied in the memory cell areais in an erase state (ERASE), the node (QS) in the page buffercan flip. On the other hand, when a memory cell to which a read voltage is applied in the memory cell areais in a program state (PGM), the node (QS) in the page buffermight not flip.

330 150 544 As described above, as the cell arrayin the memory devicebecomes more highly integrated and the number of layers in the stack increases, the cell current can decrease. Issues such as a lack of sensing margin or deterioration of distribution can occur due to the decrease in the cell current. In order to avoid or prevent the decrease in the cell current, the problem due to the decrease in the cell current can be solved by generating a page buffer current (e.g., PB Current) that increases the cell current by N times (where N is a positive number greater than 1) using the current mirror.

As above described, a memory device or a memory system according to an embodiment of the present disclosure can reduce a phenomenon of distribution deterioration or lack of sensing margin during a read operation due to a decrease in cell current within a high-density memory device, thereby improving the data input/output performance of the memory device or the memory system.

A memory device or a memory system according to an embodiment of the present disclosure can have an advantage of improving the read performance of the memory device or the memory system by increasing an amount of the current flowing on the memory cell and the bit line by N (where N is a positive number greater than 1) times through a current mirror, thereby allowing a page buffer linked to the memory cell to easily detect the current flowing on the memory cell and the bit line.

The methods, processes, and/or operations described herein may be performed by code or instructions to be executed by a computer, processor, controller, or other signal processing device. The computer, processor, controller, or other signal processing device may be those described herein or one in addition to the elements described herein. Because the algorithms that form the basis of the methods (or operations of the computer, processor, controller, or other signal processing device) are described in detail, the code or instructions for implementing the operations of the method embodiments, may transform the computer, processor, controller, or other signal processing device into a special-purpose processor for performing the methods herein.

Also, another embodiment may include a computer-readable medium, e.g., a non-transitory computer-readable medium, for storing the code or instructions described above. The computer-readable medium may be a volatile or non-volatile memory or other storage device, which may be removably or fixedly coupled to the computer, processor, controller, or other signal processing device which is to execute the code or instructions for performing the method embodiments or operations of the apparatus embodiments herein.

The controllers, processors, control circuitry, devices, modules, units, multiplexers, logic, interfaces, decoders, drivers, generators and other signal generating and signal processing features of the embodiments disclosed herein may be implemented, for example, in non-transitory logic that may include hardware, software, or both. When implemented at least partially in hardware, the controllers, processors, control circuitry, devices, modules, units, multiplexers, logic, interfaces, decoders, drivers, generators and other signal generating and signal processing features may be, for example, any of a variety of integrated circuits including but not limited to an application-specific integrated circuit, a field-programmable gate array, a combination of logic gates, a system-on-chip, a microprocessor, or another type of processing or control circuit.

When implemented at least partially in software, the controllers, processors, control circuitry, devices, modules, units, multiplexers, logic, interfaces, decoders, drivers, generators and other signal generating and signal processing features may include, for example, a memory or other storage device for storing code or instructions to be executed, for example, by a computer, processor, microprocessor, controller, or other signal processing device. The computer, processor, microprocessor, controller, or other signal processing device may be those described herein or one in addition to the elements described herein. Because the algorithms that form the basis of the methods (or operations of the computer, processor, microprocessor, controller, or other signal processing device) are described in detail, the code or instructions for implementing the operations of the method embodiments, may transform the computer, processor, controller, or other signal processing device into a special-purpose processor for performing the methods described herein.

While the present teachings have been illustrated and described with respect to specific embodiments, it will be apparent to those skilled in the art in light of the present disclosure that various changes and modifications may be made without departing from the spirit and scope of the disclosure as defined in the following claims. Furthermore, the embodiments may be combined to form additional embodiments.