A storage device includes a shared memory and a memory controller. The shared memory stores first data received from a first computing node and second data received from a second computing node. The memory controller performs an instruction on the first data and the second data, stores third data, which is a result of performing the instruction, in the shared memory, and transmits the third data to the first computing node and the second computing node.
Legal claims defining the scope of protection, as filed with the USPTO.
a shared memory storing first data received from a first computing node and second data received from a second computing node; and perform an instruction on the first data and the second data; store third data, which is a result of performing the instruction, in the shared memory; and transmit the third data to the first computing node and the second computing node. a memory controller configured to: . A storage device, comprising:
claim 1 . The storage device of, wherein the first data is application data corresponding to the first computing node, and wherein the second data is application data corresponding to the second computing node.
claim 1 . The storage device of, wherein the memory controller communicates with the first computing node and the second computing node via a Compute Express Link (CXL) interface.
claim 1 . The storage device of, wherein the memory controller performs the instruction based on a Message Passing Interface (MPI) protocol.
claim 1 . The storage device of, wherein the memory controller includes a Near Data Processing (NDP) engine performing the instruction on the first data and the second data.
claim 1 . The storage device of, wherein the memory controller performs an operation including at least one of Max, Min, Sum, Multiply, AND, OR, Bitwise AND, or Bitwise OR operation in the instruction.
a plurality of computing nodes; and receive input data including data corresponding to each of the plurality of computing nodes from the plurality of computing nodes; perform an instruction on the input data; and transmit output data which is a result of performing the instruction to the plurality of computing nodes. a storage device configured to: . A computing system, comprising:
claim 7 . The computing system of, wherein the input data includes application data corresponding to each of the plurality of computing nodes.
claim 7 . The computing system of, wherein the storage device communicates with the plurality of computing nodes via a Compute Express Link (CXL) interface.
claim 7 . The computing system of, wherein the storage device performs the instruction based on a Message Passing Interface (MPI) protocol.
claim 7 . The computing system of, wherein the storage device includes a Near Data Processing (NDP) engine performing the instruction on the input data.
claim 7 . The computing system of, wherein the storage device includes a shared memory shared by the plurality of computing nodes and storing the input data.
claim 7 . The computing system of, wherein the storage device performs an operation including at least one of Max, Min, Sum, Multiply, AND, OR, Bitwise AND, or Bitwise OR operation in the instruction.
receiving first data from a first computing node and second data from a second computing node; storing the first data and the second data in the shared memory; performing an instruction on the first data and the second data; and storing third data, which is a result of performing the instruction, in the shared memory. . A method of operating a storage device including a shared memory, the method comprising:
claim 14 . The method of, further comprising transmitting the third data to the first computing node and the second computing node.
claim 14 . The method of, wherein the first data is application data corresponding to the first computing node, and wherein the second data is application data corresponding to the second computing node.
claim 14 . The method of, wherein the storage device communicates with the first computing node and the second computing node via a Compute Express Link (CXL) interface.
claim 14 . The method of, wherein the instruction is performed based on a Message Passing Interface (MPI) protocol.
claim 14 . The method of, wherein the instruction is performed by a Near Data Processing (NDP) engine of the storage device.
claim 14 . The method of, wherein performing the instruction includes performing an operation including at least one of Max, Min, Sum, Multiply, AND, OR, Bitwise AND, or Bitwise OR operation on the first data and the second data.
Complete technical specification and implementation details from the patent document.
The present application claims priority under 35 U.S.C. §119(a) to Korean patent application number 10-2025-0022900, filed on February 21, 2025, in the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference.
Various embodiments of the present disclosure generally relate to an electronic device, and more particularly, to a computing system and an operating method thereof.
In a cluster environment which includes a plurality of computing nodes, data may be processed in parallel at respective computing nodes for efficient data processing. The respective computing nodes may communicate with each other and perform data processing based on a Message Passing Interface (MPI).
Various embodiments of the present disclosure are directed to a computing system including a plurality of computing nodes and processing an MPI operation by utilizing shared memory and a Near Data Processing (NDP) engine, and an operating method thereof.
A storage device according to an embodiment of the present disclosure may include a shared memory and a memory controller. The shared memory may store first data received from a first computing node and second data received from a second computing node. The memory controller may perform an instruction on the first data and the second data, may store third data, which is a result of performing the instruction, in the shared memory, and may transmit the third data to the first computing node and the second computing node.
A computing system according to an embodiment of the present disclosure may include a plurality of computing nodes and a storage device. The storage device may receive input data including data corresponding to each of the plurality of computing nodes from the plurality of computing nodes, may perform an instruction on the input data, and may transmit output data which is a result of performing the instruction to the plurality of computing nodes.
A method of operating a storage device including a shared memory according to an embodiment of the present disclosure may include receiving first data from a first computing node and receiving second data from a second computing node; storing the first data and the second data in the shared memory; performing an instruction on the first data and the second data; and storing third data, which is a result of performing the instruction, in the shared memory.
Specific structural or functional descriptions disclosed herein are merely illustrative for the purpose of describing embodiments according to the concepts of the present disclosure. However, embodiments according to the concepts of the present disclosure may be implemented in various forms and should not be construed as being limited to the specific embodiments set forth herein.
1 FIG. is a diagram illustrating a computing system according to an embodiment of the present disclosure.
1 FIG. 10 100 200 Referring to, a computing systemmay include a plurality of computing nodesand a network.
100 200 100 200 The plurality of computing nodesmay communicate with each other using a Message Passing Interface (MPI) on the network. The MPI may be a library that enables communication and synchronization between the computing nodesvia the network.
MPI operations (i.e., operations using an MPI) may include point-to-point communication, collective communication, synchronization, data partitioning and aggregation, an asynchronous operation, environment initialization and management, and the like.
100 100 100 100 Point-to-point communication may be an operation in which one computing nodesends or receives data to another computing node(i.e., MPI_Send, MPI_Recv). Collective communication may be an operation in which multiple computing nodesreduce or broadcast data (i.e., MPI_Reduce, MPI_Bcast). Synchronization may be an operation that synchronizes a state of operations across all computing nodesto ensure the performance of aligned operations at a specific point in time (i.e., MPI_Barrier). Data partitioning and aggregation may be an operation of dividing data into task units, processing the divided data in parallel, and aggregating the results upon completion of the processing. An asynchronous operation may be an operation of supporting asynchronous data transfer to reduce network latency and increase work efficiency (i.e., MPI_Isend, MPI_Irecv). Environment initialization and management may be an operation of managing a process rank and the number of computing nodes, and initializing and finalizing an MPI environment (i.e., MPI_Init, MPI_Finalize).
The above-described operations may help high-performance computing (HPC) optimize parallel processing of data and effectively perform large-scale distributed operations.
2 2 FIGS.A andB 1 FIG. are diagrams illustrating an MPI operation performed in a computing system of.
2 2 FIGS.A andB 101 104 Referring to, processes associated with an MPI operation among first to fourth computing nodestoare illustrated.
ta a a a a b b b b c c c c d d d d 1 101 1 4 1 4 101 102 1 4 1 4 102 103 1 4 1 4 103 104 1 4 1 4 104 In a process, a first computing nodestorestodata, and thetodata may be application data of the first computing node. The second computing nodestorestodata, and thetodata may be application data of the second computing node. The third computing nodestorestodata, and thetodata may be application data of the third computing node. The fourth computing nodestorestodata, and thetodata may be application data of the fourth computing node.
ta ta 1 7 Through processes fromto, the application data of each computing node may be aggregated and specific operations may be performed.
ta a d b a c b d c 2 101 1 102 4 104 102 2 103 1 101 103 3 104 2 102 104 4 101 3 103 For example, in a process, the first computing nodemay transmit thedata to the second computing nodeand receive thedata from the fourth computing node. The second computing nodemay transmit thedata to the third computing nodeand receive thedata from the first computing node. The third computing nodemay transmit thedata to the fourth computing nodeand receive thedata from the second computing node. The fourth computing nodemay transmit thedata to the first computing nodeand receive thedata from the third computing node.
ta a d c d a b a d b c a b c d b c 3 101 4 4 102 3 3 104 102 1 1 103 4 4 101 103 2 2 104 1 1 102 104 3 3 101 2 2 103 In a process, the first computing nodemay transmit theanddata to the second computing nodeand receive theanddata from the fourth computing node. The second computing nodemay transmit theanddata to the third computing nodeand receive theanddata from the first computing node. The third computing nodemay transmit theanddata to the fourth computing nodeand receive theanddata from the second computing node. The fourth computing nodemay transmit theanddata to the first computing nodeand receive theanddata from the third computing node.
ta a c d b c d a b d a c d a b c a b d b c d a b c 4 101 3 3 3 102 2 2 2 104 102 4 4 4 103 3 3 3 101 103 1 1 1 104 4 4 4 102 104 2 2 2 101 1 1 1 103 In a process, the first computing nodemay transmit the,, anddata to the second computing nodeand receive the,, anddata from the fourth computing node. The second computing nodemay transmit the,, anddata to the third computing nodeand receive the,, anddata from the first computing node. The third computing nodemay transmit the,, anddata to the fourth computing nodeand receive the,, anddata from the second computing node. The fourth computing nodemay transmit the,, anddata to the first computing nodeand receive the,, anddata from the third computing node.
ta a b , c d a b c d a b c d a b c d a b c d a b c d a b c d a b c d 5 101 2 2 2 2 102 1 1 1 1 104 102 3 3 3 3 103 2 2 2 2 101 103 4 4 4 4 104 3 3 3 3 102 104 1 1 1 1 101 4 4 4 4 103 In a process, the first computing nodemay transmit the,, anddata to the second computing nodeand receive the,,, anddata from the fourth computing node. The second computing nodemay transmit the,,, anddata to the third computing nodeand receive the,,, anddata from the first computing node. The third computing nodemay transmit the,,, anddata to the fourth computing nodeand receive the,,, anddata from the second computing node. The fourth computing nodemay transmit the,,, anddata to the first computing nodeand receive the,,, anddata from the third computing node.
ta a b c d a b c d a b c d a b c d 6 101 1 1 1 1 102 2 2 2 2 103 3 3 3 3 104 4 4 4 4 In a process, the first computing nodemay have the,,, anddata. The second computing nodemay have the,,, anddata. The third computing nodemay have the,,, anddata. The fourth computing nodemay have the,,, anddata.
ta ta 1 6 Through the processes fromto, application data distributed to the respective computing nodes may be redistributed to the respective computing nodes.
ta 7 In a process, an MPI operation may be performed on the data redistributed to each computing node. During the MPI operation, each computing node may perform an operation including at least one of Max, Min, Sum, Multiply, AND, OR, Bitwise AND, or Bitwise OR operation.
101 1 1 1 1 1 102 2 2 2 2 2 103 3 3 3 3 3 104 4 4, 4 4 4 a b c d z a b c d z a b c z a b c d z For example, the first computing nodemay perform an MPI operation on the,,, anddata and obtaindata. The second computing nodemay perform an MPI operation on the,,, anddata and obtaindata. The third computing nodemay perform an MPI operation on the,,, and ddata and obtaindata. The fourth computing nodemay perform an MPI operation on the,, anddata and obtaindata.
3 FIG. 1 FIG. is a diagram illustrating an MPI operation performed in a computing system of.
3 FIG. tb tb 1 4 Referring to, processes in which each computing node shares data obtained after performing an MPI operation with another computing node through processes fromtomay be described.
tb z z z z 1 101 1 102 102 2 103 103 3 104 104 4 101 For example, in the process, the first computing nodemay transmit thedata to the second computing node. The second computing nodemay transmit thedata to the third computing node. The third computing nodemay transmit thedata to the fourth computing node. The fourth computing nodemay transmit thedata to the first computing node.
tb z z z z 2 101 4 102 102 1 103 103 2 104 104 3 101 In the process, the first computing nodemay transmit thedata to the second computing node. The second computing nodemay transmit thedata to the third computing node. The third computing nodemay transmit thedata to the fourth computing node. The fourth computing nodemay transmit thedata to the first computing node.
tb z z z z 3 101 3 102 102 4 103 103 1 104 104 2 101 In the process, the first computing nodemay transmit thedata to the second computing node. The second computing nodemay transmit thedata to the third computing node. The third computing nodemay transmit thedata to the fourth computing node. The fourth computing nodemay transmit thedata to the first computing node.
tb z z 4 101 104 1 4 In the process, all of the first to fourth computing nodestomay equally have thetodata.
tb tb 1 4 Through the processes fromto, each computing node may share the operation result it has performed with another computing node and receive the operation result from another computing node. As such, parallel processing of data may be performed at each computing node.
4 FIG. is a diagram illustrating a computing system according to an embodiment of the present disclosure.
4 FIG. 10 100 300 Referring to, a computing systemmay include a plurality of computing nodesand a storage device.
300 The storage devicemay be a device storing data, and may include volatile memory and non-volatile memory. Volatile memory may include Static Random Access Memory (SRAM) or Dynamic RAM (DRAM). Non-volatile memory may include a Solid State Drive (SSD), a hard disk, a multimedia card in the form of a MultiMedia card (MMC), an embedded MMC (eMMC), a Universal Serial Bus (USB) storage device, a Universal Flash Storage (UFS) device, a Peripheral Component Interconnect (PCI), a PCI Express (PCI-e) card type storage device, or the like.
300 100 The storage devicemay communicate with the computing nodeusing at least one of various communication methods such as Universal Serial Bus (USB), Serial AT Attachment (SATA), Serial Attached SCSI (SAS), High Speed Interchip (HSIC), Small Computer System Interface (SCSI), Peripheral Component Interconnect (PCI), PCI Express (PCI-e), NonVolatile Memory express (NVMe), Universal Flash Storage (UFS), Secure Digital (SD), MultiMedia Card (MMC), embedded MMC (eMMC), Dual In-line Memory Module (DIMM), Registered DIMM (RDIMM), and Load Reduced DIMM (LRDIMM) communication methods.
300 310 320 In an embodiment, the storage devicemay include a memory controllerand a shared memory.
310 100 310 100 310 The memory controllermay communicate with the plurality of computing nodes. For example, the memory controllermay communicate with the plurality of computing nodesvia a Compute Express Link (CXL) interface. The memory controllermay be a controller which controls a CXL memory device.
310 100 100 100 The memory controllermay receive input data, including data corresponding to each of the plurality of computing nodes, from the plurality of computing nodes. The input data may include application data corresponding to each of the plurality of computing nodes.
310 320 310 320 100 The memory controllermay store the input data in the shared memoryand perform an instruction on the input data. The memory controllermay store output data, which is the result of performing the instruction, in the shared memory, and transmit the output data to the plurality of computing nodes.
320 100 320 The shared memorymay be memory which is shared and accessed by the plurality of computing nodes. In an embodiment, the shared memorymay be pooled memory.
310 311 311 320 311 311 320 The memory controllermay include a Near Data Processing (NDP) engine. The NDP enginemay perform the instruction on the input data stored in the shared memorybased on a Message Passing Interface (MPI) protocol. The NDP enginemay perform an operation including at least one of Max, Min, Sum, Multiply, AND, OR, Bitwise AND, or Bitwise OR operation in the instruction. The NDP enginemay store the output data, which is the result of performing the instruction, in the shared memory.
5 5 FIGS.A andB 4 FIG. are diagrams illustrating an MPI operation performed in a computing system of.
5 5 FIGS.A andB 101 104 300 Referring to, an MPI operation process of first to fourth computing nodestovia a storage devicemay be described.
tc a a a a b b b b c c c c d d d d 1 101 1 4 1 4 101 102 1 4 1 4 102 103 1 4 4 103 104 1 4 1 4 104 For example, in a process, the first computing nodestores thetodata, and thetodata may be application data of the first computing node. The second computing nodestores thetodata, and thetodata may be application data of the second computing node. The third computing nodestores thetodata, and the1 todata may be application data of the third computing node. The fourth computing nodestores thetodata, and thetodata may be application data of the fourth computing node.
tc a a b b c c d d 2 300 1 4 101 1 4 102 1 4 103 1 4 104 In a process, the storage devicemay receive thetodata from the first computing node, thetodata from the second computing node, thetodata from the third computing node, and thetodata from the fourth computing node.
320 1 4 1 4 1 4 1 4 a a b b c c d d The shared memorymay store input data including theto,to,to, andtodata received from the respective computing nodes.
tc 3 311 320 311 In a process, the NDP enginemay perform an instruction on the input data stored in the shared memory. The NDP enginemay perform an operation including at least one of Max, Min, Sum, Multiply, AND, OR, Bitwise AND, or Bitwise OR operation on the input data in the instruction.
tc z z 4 311 320 1 4 300 In a process, the NDP enginemay store output data, which is the result of performing the instruction, in the shared memory. The output data may include thetodata. The storage devicemay transmit the output data to each computing node.
2 2 FIGS.A,B 5 5 FIGS.A andB 3 320 311 Compared to an MPI operation described with reference to, and, an MPI operation described with reference toutilizes the shared memoryand the NDP engine, so that overhead due to unnecessary data movement and copying may be reduced.
6 FIG. is a diagram illustrating a method of operating a storage device according to an embodiment of the present disclosure.
6 FIG. 601 Referring to, in step S, a storage device may receive first data from a first computing node and receive second data from a second computing node. The first data may be application data of the first computing node, and the second data may be application data of the second computing node.
603 In step S, the storage device may perform an instruction on the first data and the second data by using a Near Data Processing (NDP) engine. The instruction may be performed based on a Message Passing Interface (MPI) protocol.
605 In step S, the storage device may store third data, which is the result of performing the instruction, in a shared memory.
607 In step S, the storage device may transmit the third data to a plurality of computing nodes.
7 FIG. is a diagram illustrating a method of operating a computing system according to an embodiment of the present disclosure.
7 FIG. 701 Referring to, in step S, a computing system may receive input data including data corresponding to each of a plurality of computing nodes.
703 In step S, the computing system may store the input data in a shared memory.
705 In step S, the computing system may perform an instruction on the input data using a Near Data Processing (NDP) engine.
707 In step S, the computing system may store output data, which is the result of performing the instruction, in the shared memory.
709 In step S, the computing system may transmit the output data to the plurality of computing nodes.
According to some embodiments of the present disclosure, a computing system including a plurality of computing nodes and processing an MPI operation by utilizing a shared memory and a Near Data Processing (NDP) engine, and an operating method thereof are provided.
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August 14, 2025
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