Semiconductor Device and Power Conversion Apparatus

The present disclosure relates to a semiconductor device, and more particularly, to the driving of a power semiconductor element.

One of the problems related to the reliability of a power semiconductor element is a gate false turn-on. When a gate false turn-on occurs, the high-voltage power supply on the upper arm and the low-voltage power supply on the lower arm of one phase of a power inverter in which the false turn-on occurs are short-circuited. As a result, a large short-circuit current flows between the power supplies, which may increase electrical loss of the power inverter, and may lead to a thermal runaway in the worst case.

As a countermeasure against the gate false turn-on, there is widely known an approach of applying a negative bias voltage between the gate and the source of a power semiconductor element. The gate false turn-on is caused by a displacement current generated by the turn-on operation of the power semiconductor element on the opposing arm. Since the displacement current is proportional to the voltage change rate of the power conversion element on the opposing arm, the displacement current increases as the switching speed becomes higher, and as a result, the false turn-on of the switching-side element is likely to occur. However, when a negative bias voltage is applied at a timing when a false turn-on occurs, it is possible to prevent a short circuit from occurring in the upper and lower arm elements without exceeding the gate threshold voltage, and the larger the negative bias voltage is, the greater the effect of preventing the false turn-on will be.

On the other hand, when a negative bias voltage is applied between the gate and the source, during the OFF operation of a conventional power semiconductor element, the gate is driven with a constant application of the negative bias voltage. When the negative bias has been applied for a long period of time, the gate oxide film of the power semiconductor element suffers from a stress. In a report on a silicon nitride-based metal oxide semiconductor field effect transistor (SiC-MOSFET: Metal-Oxide-Semiconductor Field-Effect Transistor), it was reported that a great stress on the gate oxide film may cause characteristic degradation or failure of a power semiconductor element. As a result, the entire reliability of the power inverter is reduced.

PTL 1: Japanese Patent Laying-Open No. 2013-219874

NPL 1: Andreas Marz, et al., Comparison of SiC MOSFET gate-drive concepts to suppress parasitic turn-on in low inductance power modules, EPE, 2017.

In PTL 1, the gate terminal of the power semiconductor element is applied with two voltages, i.e., a first voltage and a second voltage lower than the first voltage. The turn-off operation of the power semiconductor device is performed at the first voltage, but the first voltage is generally not greater than the negative bias voltage applied to the gate terminal. In other words, the switching loss of the power semiconductor element increases as compared with the case when the second voltage is used. On the other hand, when the first voltage is increased, the switching loss is improved by speeding up the turn-on operation, but a negative bias voltage (for example, the second voltage) greater than the first voltage must be continuously applied to the gate until the end of the turn-on operation of the power semiconductor element on the opposing arm, including a dead time after the turn-off operation. Therefore, this leads to the aforementioned problem of stress on the gate oxide film, which reduces the entire reliability of the power converter.

In NPL 1, a negative bias voltage is applied to the gate terminal of a self-arm element over a period from the start of the turn-off operation of the power semiconductor element to the end of the turn-on operation of the power semiconductor element on the opposing arm. In other words, the negative bias voltage is continuously applied to the gate terminal of the self-arm element during the dead time period and the switching period. Therefore, in a system or the like in which the dead time is set to a large value, there is a concern that the effect of reducing the stress on the gate oxide film may be insufficient.

It is an object of the present disclosure to provide a semiconductor device and a power conversion apparatus capable of improving the reliability of a power semiconductor element.

A semiconductor device according to an embodiment includes: a gate voltage control circuit that applies an on-bias voltage and an off-bias voltage to a gate terminal of a power semiconductor element according to a first drive signal; and an off-bias voltage control circuit that adjusts a voltage level of the off-bias voltage according to the first drive signal and a second drive signal and controls a period of applying the adjusted off-bias voltage.

A power conversion apparatus according to an embodiment includes: a first power semiconductor element; a second power semiconductor element provided on an opposing arm which is connected in series to the first power semiconductor element; a first gate drive circuit provided for the first power semiconductor element and configured to drive the first power semiconductor element according to a first drive signal; and a second gate drive circuit provided for the second power semiconductor element and configured to drive the second power semiconductor element according to a second drive signal. Each of the gate drive circuits includes: a gate voltage control circuit that applies an on-bias voltage and an off-bias voltage to a gate terminal of a corresponding power semiconductor element according to a corresponding drive signal; and an off-bias voltage control circuit that adjusts a voltage level of an off-bias voltage according to the first and second drive signals and controls a period of applying the adjusted off-bias voltage.

According to the semiconductor device and the power conversion apparatus of the present disclosure, it is possible to improve the reliability of a power semiconductor element.

Hereinafter, a gate drive circuit of a power semiconductor device, which is an example of the present disclosure, will be described.

1 FIG. 100 is a block diagram illustrating a gate drive circuitaccording to a first embodiment.

1 FIG. 100 10 1 2 100 10 With reference to, the gate drive circuitcontrols the gate of a power semiconductor elementconnected between DC high-voltage power supplies according to the input of an external drive signal INand an external drive signal IN. Specifically, the gate drive circuitcontrols an on/off operation, i.e., a switching operation of the power semiconductor element.

10 10 10 1 The power semiconductor elementcorresponds to a switching element of a main circuit in an inverter circuit of a power conversion apparatus. For example, the power semiconductor elementis an element of a 2-in-1 half bridge circuit, a 4-in-1 full bridge circuit, or a 6-in-1 three-phase inverter. In these circuit configurations, since the output voltage of the inverter is generated according to a PWM control, a high voltage of several hundred volts or more is applied between the drain and the source of the element during the OFF operation. In addition, a large current flows through the element during the ON operation according to the system of the power conversion apparatus. In these operation states, the gate voltage for turning on or turning off the power semiconductor elementis controlled according to the external drive signal IN.

100 20 30 The gate drive circuitincludes a gate voltage control circuitand an off-bias voltage control circuit.

20 10 The gate voltage control circuitcontrols an on-bias voltage and an off-bias voltage of the gate of the power semiconductor element.

20 21 22 The gate voltage control circuitincludes a first control circuitand a first switching circuit.

21 10 1 10 10 The first control circuitcontrols a gate control signal so that a desired switching operation of the power semiconductor elementis performed according to the input external drive signal IN. Specifically, the gate control signal is set to “1” during a period when the power semiconductor elementshould be turned on, and the gate control signal is set to “0” during a period when the power semiconductor elementshould be turned off. These binary voltage signals can be obtained by generating a pulse wave using a communication signal source such as a 5V system or a 3.3V system in a logic circuit.

22 10 21 22 32 The first switching circuitis disposed between the gate of the power semiconductor elementand the first control circuit. The high side of the first switching circuitis connected to a positive voltage source Vdd, and the low side thereof is connected to a second switching circuit.

22 22 22 22 The first switching circuitincludes an NPN transistorA, a PNP transistorB, and a resistance elementC.

22 22 The NPN transistorA and the PNP transistorB are connected in series.

22 The NPN transistorA is connected to the positive voltage source Vdd, and is connected to an output node.

22 32 The PNP transistorB is connected to the output node and an output node of the second switching circuit.

22 22 21 22 The gate of the NPN transistorA and the gate of the PNP transistorB are connected to the first control circuitvia the resistance elementC.

22 21 10 22 10 10 The first switching circuitcan switch the current path according to a gate control signal output from the first control circuit. As a result, the current path through which the gate current flows in the power semiconductor elementis changed, which is equivalent to switching between gate charging and gate discharging. Therefore, the first switching circuitswitches a gate voltage to be applied to the gate of the power semiconductor elementto control the on/off operation of the power semiconductor element.

30 10 1 2 30 10 10 The off-bias voltage control circuitcontrols the voltage level of an off-bias voltage applied to the gate during the OFF operation of the power semiconductor elementaccording to the external drive signal INand the external drive signal IN. Specifically, the off-bias voltage control circuitsets the voltage level during the off operation of the power semiconductor elementto always be below 0 V because if the voltage level is a positive value, it may exceed the gate threshold voltage of the power semiconductor element.

In addition, the number of voltage levels of the off-bias voltage to be switched is two, for example.

1 2 1 21 In the present embodiment, the external drive signal INand the external drive signal INare used to switch the two voltage levels of the off-bias voltage. The external drive signal INis the same as the input signal to the first control circuit.

2 100 10 2 1 The external drive signal INis required to provide the gate drive circuitwith time information of a gate false turn-on (also referred to as a self-turn-on phenomenon) of the power semiconductor element, which will be described later. The external drive signal INis provided as a means different from the external drive signal IN.

30 31 32 The off-bias voltage control circuitincludes a second control circuitand a second switching circuit.

31 10 1 2 The second control circuitoutputs an off-bias voltage control signal capable of arbitrarily adjusting a voltage level of an off-bias voltage applied to the gate of the power semiconductor elementand an application period of the off-bias voltage based on the input of the external drive signal INand the external drive signal IN. A specific scheme will be described later.

32 31 22 10 The second switching circuitis connected to the second control circuit, the first switching circuit, and the source electrode of the power semiconductor element.

32 10 The high side of the second switching circuitis connected to a source electrode of the power semiconductor element, and the low side thereof is connected to a negative voltage source Vneg.

32 32 32 32 The second switching circuitincludes an NPN transistorA, a PNP transistorB, and a resistance elementC.

32 32 The NPN transistorA and the PNP transistorB are connected in series.

32 10 22 The NPN transistorA is connected to the source electrode of the power semiconductor elementand is connected to an output node. The output node is connected to the first switching circuit.

32 The PNP transistorB is connected to the output node and the negative voltage source Vneg.

32 32 31 32 The gate of the NPN transistorA and the gate of the PNP transistorB are connected to the second control circuitvia the resistance elementC.

32 31 10 10 10 The second switching circuitswitches the off-bias voltage level of the gate according to an off-bias voltage control signal generated by the second control circuit. Specifically, the second switching circuit switches a reference potential Vs which is based on the source potential of the power semiconductor elementand the negative voltage source Vneg are switched. In other words, the voltage level of an off-bias voltage to be applied to the gate of the power semiconductor elementis switched by switching the source potential of the power semiconductor element.

Hereinafter, the state in which the reference potential Vs is connected may be referred to as a “shallow off-bias voltage”, and the state in which the negative voltage source Vneg is connected may be referred to as a “deep off-bias voltage” where appropriate.

10 10 10 32 22 10 10 20 30 However, the shallow off-bias voltage and the deep off-bias voltage applied to the gate of the power semiconductor elementare premised on the OFF operation of the power semiconductor element. Therefore, the shallow off-bias voltage and the deep off-bias voltage to be applied to the gate of the power semiconductor elementare not uniquely determined by the operation of the second switching circuit, but switched by the first switching circuitonly during the OFF operation of the power semiconductor element. In other words, the voltage level of the off-bias voltage applied to the gate of the power semiconductor elementis controlled based on the state of the gate voltage control circuitand the off-bias voltage control circuit.

21 31 21 31 The first control circuitor the second control circuitmay include a passive element such as a resistor, a capacitor or a diode, and an RC filter as components not shown in the figure. The first control circuit or the second control circuit may include a Schmitt trigger element configured to tailor a transmission signal. The first control circuitincludes a delay line (which can be realized by a delay IC or a buffer circuit) that delays the transmission signal by a certain amount of time, and the second control circuitincludes a logical operation circuit that performs a logical operation such as a logical OR or a logical AND on the transmission signal.

22 32 Further, the first switching circuitand the second switching circuithave a totem pole circuit structure in which switching elements are disposed on the upper and lower arms as components not shown in the figure, and may perform a two-stage control on outputs according to an input gate control signal. Specifically, the circuit may be configured as a push-pull circuit where the high-side element is an NPN transistor and the low-side element is a PNP transistor as described above, or may have any other configuration.

2 FIG. 21 31 is a diagram illustrating a specific configuration of the first control circuitand the second control circuitaccording to the first embodiment.

2 FIG. 21 21 21 With reference to, the first control circuitincludes a control unitA and a delay circuitB.

21 1 21 The control unitA receives the external drive signal INas an input signal and generates a tailored signal. For example, the control unitA may be realized by a capacitor for holding a voltage, a diode element for preventing reverse conduction, and a Schmitt trigger element for tailoring the transmission signal.

21 21 21 The delay circuitB receives an output signal from the control unitA, delays the output signal by a certain amount of time, and generates a delay signal. For example, the delay circuitB may be a delay line that delays the transmission signal by a certain amount of time, and the delay line may be constituted by a logic IC or a buffer element.

21 22 1 22 10 10 1 FIG. By constituting the first control circuitin this manner, the gate control signal input to the first switching circuitillustrated inis delayed by a certain amount of time based on the external drive signal IN. The operation of the first switching circuitcan also be delayed by the same amount of time in response to the amount of delay of the gate control signal. Therefore, the switching operation of the power semiconductor elementis also delayed by the same amount of time. Further, the gate delay amount of the power semiconductor elementcan be set variable by providing a plurality of terminals for each of the logic IC and the buffer element constituting the delay line, by setting different delay amounts for the logic IC and the buffer element, or by using a jumper pin to switch the connection point of the circuit.

31 31 31 0 1 0 1 The second control circuitincludes delay circuitsA andB, inverters IVand IV, AND circuits ADand AD, and a NOR circuit NR.

1 31 1 0 The AND circuit ADO receives the external drive signal INvia the delay circuitA and the external drive signal INvia the inverter IV, and outputs an AND logic operation result to the NOR circuit NR.

1 2 31 1 2 The AND circuit ADreceives the external drive signal INvia the delay circuitB and the inverter IVand the external drive signal INdirectly, and outputs an AND logic operation result to the NOR circuit NR.

0 1 The NOR circuit NR receives inputs from the AND circuits ADand AD, and outputs a NOR logic operation result.

31 31 31 31 The delay circuitsA andB are configured to generate a delay signal. For example, the delay circuit may be an RC filter which is a general delay time adjustment circuit, or may include a Schmitt trigger element for tailoring a transmission signal. The delay amount of the delay circuitA may be different from the delay amount of the delay circuitB.

The NOR circuit NR normally outputs an off-bias voltage control signal (“1”).

32 32 As a result, the NPN transistorA of the second switching circuitis turned on.

1 0 31 32 32 On the other hand, when the external drive signal INchanges from “1” to “0”, the AND circuit ADoutputs a one-shot pulse signal proportional to the delay amount of the delay circuitA. In response, the NOR circuit NR turns on the PNP transistorB of the second switching circuitduring the period of the one-shot pulse signal.

2 1 31 32 32 When the external drive signal INchanges from “0” to “1”, the AND circuit ADoutputs a one-shot pulse signal proportional to the delay amount of the delay circuitB. In response, the NOR circuit NR turns on the PNP transistorB of the second switching circuitduring the period of the one-shot pulse signal.

31 1 2 The second control circuitis a logical operation circuit that receives two signals of the external drive signals INand IN, performs a logical operation such as a logical OR or a logical AND on the two signals, and generates a single off-bias voltage control signal from the two output signals. For example, the second control circuit may be constituted by a discrete IC element incorporated with only one element, or may be constituted by a 2-in-1 logic IC having two logic functions. The second control circuit may include at least one AND element and at least one OR element for logical operation.

31 31 1 2 Due to the provision of the delay circuitsA andB, it is possible to generate an off-bias voltage control signal according to the external drive signal INand the external drive signal IN, and it is possible to adjust the time of the off-bias voltage control signal.

10 31 31 31 31 10 Specifically, it is possible to determine a timing and a period of applying the deep off-bias voltage Vneg to the gate of the power semiconductor elementin response to the delay amount of the delay circuitsA andB. The resistor or the capacitor in the RC filter of each of the delay circuitsA andB may be a variable resistor or a variable capacitor. With such a configuration, it is possible to variably set a timing and a period of applying the deep off-bias voltage Vneg to the power semiconductor element.

21 21 21 20 31 31 31 30 10 10 According to the first embodiment, since the control unitA and the delay circuitB are provided in the first control circuitincluded in the gate voltage control circuit, and the delay circuitsA andB are provided in the second control circuitincluded in the off-bias voltage control circuit, it is possible to generate an appropriate off-bias level control signal, and it is possible to determine the timing and the period of applying the deep off-bias voltage Vneg to the power semiconductor element. As a result, the reliability of the power semiconductor elementis improved.

100 Next, a specific operation of the gate drive circuitaccording to the first embodiment will be described.

3 FIG. 100 10 is a diagram illustrating a timing chart when the gate drive circuitaccording to the first embodiment controls the gate of the power semiconductor element.

3 FIG. 100 1 2 10 With reference to, operation differences between the gate drive circuitaccording to the first embodiment and the comparative example are illustrated. The horizontal axis represents time, and the vertical axis represents an external drive signal IN, an external drive signal IN, and a gate voltage Vgs of the power semiconductor element.

0 1 100 10 10 At time t, the external drive signal INchanges from “1” to “0”, and in response, the gate drive circuitbegins to discharge the gate of the power semiconductor element. In other words, the power semiconductor deviceis turned off. Since the charges of the gate charged during the ON operation are discharged, the gate voltage Vgs of the power semiconductor element begins to drop.

10 First, the gate voltage Vgs drops sharply from an on-bias voltage Vdd. Next, while a drain-source voltage Vds (not shown) of the power semiconductor elementbegins to rise, the gate voltage Vgs is maintained at a certain constant voltage value. This period is referred to as a mirror period, and continues until the gate-drain parasitic capacitance, which depends on the drain-source voltage Vds, ceases to change (in general, the mirror period is very short for SiC-MOSFET). After the mirror period ends, the gate voltage Vgs begins to drop again, and reaches the deep off-bias voltage Vneg, which terminates the turn-off operation. Thus, there are great differences between the gate drive circuit according to the first embodiment and the comparative example (the configuration described in PTL 1).

The most significant difference is the presence or absence of the deep off-bias voltage Vneg.

100 10 0 Since the gate drive circuitaccording to the first embodiment is provided with a function of applying the deep off-bias voltage Vneg to the gate, the speed of turning off the power semiconductor elementis faster than the comparative example which is not provided with the function of applying the deep off-bias voltage. In the interval from time to tthe start of the mirror period and from the end of the mirror period to the end of the turn-off operation, the absolute value of a change rate dVgs/dt of the gate voltage Vgs is larger in the configuration according to the first embodiment than in the configuration of the comparative example.

10 This effect makes it possible to reduce the turn-off loss of the power semiconductor device, which has the advantages of suppressing heat generation of the power conversion apparatus and reducing the size of the cooler.

10 On the other hand, in the configuration according to the comparative example, since the turn-off operation is performed by the shallow off-bias voltage Vs, it is concerned that the reduction of the turn-off loss of the power semiconductor elementis not sufficient. Furthermore, there are differences in the behavior of the gate voltage Vgs after the end of the turn-off operation.

Since the configuration according to the first embodiment has the deep off-bias voltage Vneg, the gate voltage Vgs drops from the shallow off-bias voltage Vs to the deep off-bias voltage Vneg.

100 10 1 In the gate drive circuitaccording to the first embodiment, the turn-off operation of the power semiconductor elementis completed at time twhen the gate voltage Vgs reaches the deep off-bias voltage Vneg.

100 10 1 1 2 10 According to the configuration of the gate drive circuitaccording to the first embodiment, since the deep off-bias voltage Vneg is applied to the gate of the power semiconductor elementfrom time t, which may cause characteristic degradation or failure due to the stress on the gate oxide film as described above, but the period from time tto time tat which the deep off-bias voltage Vneg begins to return to the shallow off-bias voltage Vs is sufficiently shorter than a dead time period Td (both the upper arm and the lower arm are turned off) set in the inverter circuit of the power conversion apparatus. In other words, the actual stress on the gate oxide film is very small. Therefore, high reliability of the power semiconductor elementcan be ensured.

10 0 2 2 In the present embodiment, the deep off-bias voltage Vneg is applied to the gate of the power semiconductor elementin the period from time tto time t. This period is defined as a first period. Next, the operations after time twill be described.

10 1 2 During the dead time period Td, the gate voltage Vgs of the power semiconductor elementis set to the shallow off-bias voltage Vs, and the external drive signal INand the external drive signal INare both set to “0”.

2 10 In the present embodiment, the external drive signal INhas a function of notifying the timing of a false turn-on of the gate of the power semiconductor element, in other words, the turn-on timing of the opposing arm element.

2 Thus, the external drive signal INchanges from “0” to “1” at the end of the dead time period Td.

100 10 2 10 10 10 The gate drive circuitdetermines that it is time to turn on the opposing arm element of the power semiconductor elementbased on the change of the external drive signal IN, and changes the gate voltage Vgs of the power semiconductor elementfrom the shallow off-bias voltage Vs to the deep off-bias voltage Vneg. Then, the opposing arm element is turned on, and thereby the gate voltage Vgs of the power semiconductor elementis raised from the deep off-bias voltage Vneg. Since the deep off-bias voltage Vneg is set larger than the raised voltage value of the gate voltage Vgs, the gate voltage Vgs does not exceed 0 V. In other words, there is a sufficient margin for the gate threshold voltage of the power semiconductor element.

3 10 10 10 The period from time tto time ton at which the opposing arm element of the power semiconductor elementactually starts the turn-on operation coincides with the delay amount of the gate control signal to the opposing arm element. Since it takes time for the deep off-bias voltage Vneg to be applied to the gate voltage Vgs of the power semiconductor element, a delay of the gate control signal to the opposing arm element is inserted. This makes it possible to reliably prevent a false turn-on of the gate of the power semiconductor device.

4 10 10 10 3 4 10 10 3 4 At time tafter the turn-on operation of the opposing arm element of the power semiconductor elementis completed, the gate voltage Vgs of the power semiconductor elementagain begins to return from the deep off-bias voltage Vneg to the shallow off-bias voltage Vs. In other words, the stress on the gate oxide film of the power semiconductor elementis very small. In other words, during the period from time tto time t, the deep off-bias voltage Vneg is applied to the gate of the power semiconductor element. In the present embodiment, the period from the end of the dead time period Td until the shallow off-bias voltage is applied to the gate of the power semiconductor elementis defined as a second period. In other words, the period from time tto time tis included in the second period.

100 10 10 The gate drive circuitaccording to the first embodiment can reduce the switching loss by applying a deep off-bias voltage to the power semiconductor device, and can improve the reliability of the power semiconductor elementby limiting the application time of the deep off-bias voltage to a limited interval within the first period and the second period. As a result, the service life of the power semiconductor element can be prolonged, which makes the power converter system economical.

101 40 10 22 In a second embodiment, the operation of a gate drive circuitthat includes a gate resistance control circuitdisposed between the power semiconductor elementand the first switching circuitwill be described.

4 FIG. 101 is a diagram illustrating the gate drive circuitaccording to the second embodiment.

4 FIG. 101 100 40 10 22 With reference to, the gate drive circuitis different from the gate drive circuitaccording to the first embodiment in that the gate resistance control circuitis disposed between the power semiconductor elementand the first switching circuit. Since the other configurations are the same, the detailed description thereof will not be repeated.

40 41 42 41 The gate resistance control circuitincludes a gate resistorand a bypass switching elementconnected in parallel to both ends of the gate resistor.

41 10 The gate resistoradjusts a switching speed, specifically, a turn-on speed and a turn-off speed of the power semiconductor element.

41 41 When the resistance value of the gate resistoris large, the surge voltage of the drain-source voltage Vds and the electromagnetic noise at the time of switching can be reduced, but the switching loss increases. Conversely, when the resistance value of the gate resistoris small, the relationship between the surge voltage of the drain-source voltage Vds, the electromagnetic noise and the switching loss is opposite to the case where the resistance value is large.

42 42 41 42 42 41 The bypass switching elementperforms a turn-on operation and a turn-off operation in response to an ON/OFF command of the gate control signal. The bypass switching elementis connected in parallel to the gate resistor. After the bypass switching elementis turned on, a gate current flows through the bypass switching element, and after the bypass switching element is turned off, the gate current flows through the gate resistor.

42 41 The timing at which the bypass switching elementaccording to the second embodiment is turned on to bypass the gate resistorcorresponds to the timing at which the off-bias voltage level of the gate is switched between the deep off-bias voltage Vneg and the shallow off-bias voltage Vs.

42 10 42 10 Specifically, during the first period, the bypass switching elementis maintained in the OFF state until the turn-off operation of the power semiconductor elementis completed, and the bypass switching elementis turned on after the turn-off operation of the power semiconductor elementis completed and the off-bias voltage is switched from the deep off-bias voltage Vneg to the shallow off-bias voltage Vs.

42 1 2 As an example, the bypass switching elementis turned on during the period from time Tbto time Tb.

42 41 Similarly, the timing at which the bypass switching elementaccording to the second embodiment is turned off and switched to the path via the gate resistoris a period from the time when the dead time period Td ends to a time prepared for the turn-on operation of the opposing arm element, in other words, a period from a time when the shallow off-bias voltage Vs is switched to the deep off-bias voltage Vneg to the start of the turn-on operation of the opposing arm element.

42 42 Specifically, during the second period, the bypass switching elementis maintained in the ON state until the shallow off-bias voltage Vs is switched to the deep off-bias voltage Vneg, and the bypass switching elementis turned off before the turn-on operation of the opposing arm element.

42 3 3 For example, the bypass switching elementis turned on during the period from time Tto time Tb.

42 41 10 By operating the bypass switching elementas described above, the bypass path without the gate resistoris utilized only for switching the deep off-bias voltage Vneg and the shallow off-bias voltage Vs to be applied to the gate of the power semiconductor element.

32 22 10 41 41 10 As mentioned above in the first embodiment, the second switching circuitoperates in conjunction with the first switching circuit. In other words, the speed of switching the deep off-bias voltage Vneg and the shallow off-bias voltage Vs depends on the circuit constant of the discharge path of the power semiconductor element. In short, if the resistance of the gate resistoris large, the speed of switching the deep off-bias voltage Vneg and the shallow off-bias voltage Vs becomes slow accordingly. In the second embodiment, the bypass path without the gate resistormakes it possible to increase the speed of switching the deep off-bias voltage Vneg and the shallow off-bias voltage Vs. In other words, it is possible to suitably control the level and timing of the off-bias voltage applied to the gate of the power semiconductor element.

41 41 10 42 41 Further, the gate resistoris effective against the gate false turn-on. This is because if the gate resistoris small (for example, 0 Ω), an oscillation may occur due to a floating inductance component of the gate wiring of the power semiconductor element, which may cause a gate false turn-on. In addition, the susceptibility to electromagnetic noise may trigger the gate false turn-on. As a countermeasure against these phenomena, when a gate false turn-on occurs, in other words, when the opposing arm element is turned on, the bypass switching elementis turned off to establish a path via the gate resistor.

101 Next, a specific operation of the gate drive circuitaccording to the second embodiment will be described.

5 FIG. 101 is a diagram illustrating a timing chart when the gate drive circuitaccording to the second embodiment controls the gate of the power semiconductor element.

5 FIG. 101 100 With reference to, since the basic operation of the gate drive circuitaccording to the second embodiment is the same as the basic operation of the gate drive circuitaccording to the first embodiment, the detailed description thereof will not be repeated.

0 10 10 1 2 At time t, the power semiconductor elementis turned on. As illustrated in the figure, the gate voltage of the power semiconductor deviceis lowered to the deep off-bias voltage Vneg, and the deep off-bias voltage Vneg is established at time t. Thereafter, at time t, the off-bias voltage is switched from the deep off-bias voltage Vneg to the shallow off-bias voltage Vs so as to shorten the application time of the deep off-bias voltage Vneg.

100 42 1 1 2 1 10 2 2 42 The difference from the gate drive circuitaccording to the first embodiment is that the bypass switching elementis turned on at time tbin an interval between time tand time tincluded in the first period. With the addition of the operation at time tbin the present embodiment, the gate voltage of the power semiconductor elementchanges at time t. Specifically, the speed switching from the deep off-bias voltage Vneg to the shallow off-bias voltage Vs is increased, and it is possible to quickly return to the shallow off-bias voltage Vs as illustrated in the figure. Since the off-bias voltage Vs is quickly returned to the shallow off-bias voltage Vs, the application time of the deep off-bias voltage Vneg can be reliably shortened as compared with that in the first embodiment. It should be noted that at time tb, the bypass switching elementis turned off.

2 3 After the dead time period Td has elapsed, the external drive signal INindicating the timing of the turn-on operation of the opposing arm element changes from “0” to “1”. In other words, the dead time period Td ends at time t.

3 10 At time t, the gate voltage of the power semiconductor elementis switched again from the shallow off-bias voltage Vs to the negative bias voltage Vneg.

3 42 41 10 At time t, the bypass switching elementis turned on. Thus, the gate resistoris bypassed, and as a result, the speed of switching from the shallow off-bias voltage Vs to the deep off-bias voltage Vneg becomes faster than that in the first embodiment, and as illustrated in the figure, it is possible to quickly apply the deep off-bias voltage Vneg to the gate of the power semiconductor element.

3 42 Then, at time tb, the bypass switching elementis turned off.

10 42 3 3 Subsequently, at time ton, the opposing arm element is turned on, and a gate false turn-on of the power semiconductor elementoccurs. In the present embodiment, the bypass switching elementis turned off at time tbwithin an interval between time tand time ton included in the second period.

40 3 10 42 41 As described above, with the addition of the operation of the gate resistance control circuitaccording to the second embodiment at time tb, it is possible to prevent the gate false turn-on of the power semiconductor elementfrom being caused by the floating inductance and the electromagnetic noise. Specifically, by turning off the bypass switching elementto switch to the gate resistor, it is possible to obtain a gate false turn-on tolerance equivalent to that of the first embodiment as illustrated in the figure.

2 10 40 42 41 41 10 10 In the dead time period Td after time tb, in other words, in the off-bias period of the power semiconductor element, the gate resistance control circuitturns off the bypass switching elementto connect the gate resistor. As described above, by keeping the gate resistorconnected even during the OFF operation of the power semiconductor element, it is possible to dampen the oscillation of the gate caused by external factors. As a result, the gate false turn-on of the power semiconductor elementcan be prevented.

1 2 3 3 42 0 1 1 2 42 The ON operation period (tb-tb, t-tb) of the bypass switching elementcan be set by the components described in the first embodiment. Specifically, it can be realized by combining the RC filter that delays the period from time tto time tb, and the logic operation circuit described in the first embodiment that generates a one-shot pulse using the external drive signal INand the external drive signal IN. Further, the ON operation period (bypass period) of the bypass switching elementcan also be set arbitrarily, and the ON operation and the OFF operation can also be switched over a plurality of places.

41 10 41 42 10 42 The gate resistormay be constituted by a circuit element such as a general lead resistor or a chip resistor as long as it has a circuit constant or a power capacity in accordance with the switching operation condition of the power semiconductor element, the number of circuit elements constituting the gate resistormay be single or multiple, and the circuit configuration may be serial or parallel. The bypass switching elementmay be an inexpensive discrete circuit element as long as it can cope with the gate capacitance of the power semiconductor element. The bypass switching elementdesirably has a higher high-speed response. The trade-off relationship holds that the higher the gate threshold voltage, the lower the risk of malfunction, but the lower the high-speed response; on the other hand, the lower the gate threshold voltage, the higher the high-speed response, but the higher the risk of malfunction.

101 40 10 22 10 10 The gate drive circuitaccording to the second embodiment includes a gate resistance control circuitdisposed between the power semiconductor elementand the first switching circuit, which makes it possible to further shorten the period of the deep off-bias voltage Vneg applied to the gate of the power semiconductor element. Furthermore, by speeding up the switching from the shallow off-bias voltage Vs to the deep off-bias voltage Vneg, it is possible to further improve the reliability of the power semiconductor element.

10 Therefore, it is possible to further prolong the service life of the power semiconductor element, which makes the power converter system economical.

In a third embodiment, a switching circuit having a configuration different from that of the first embodiment will be described.

6 FIG. 100 is a block diagram illustrating a gate drive circuit# of the power semiconductor device according to the third embodiment.

6 FIG. 100 100 20 20 30 30 With reference to, the gate drive circuit# differs from the gate drive circuitin that the gate voltage control circuitis replaced with a gate voltage control circuit# and the off-bias voltage control circuitis replaced with an off-bias voltage control circuit#.

100 Since the other configurations are the same as those of the gate drive circuitaccording to the first embodiment, the detailed description thereof will not be repeated.

20 20 21 21 22 22 The gate voltage control circuit# differs from the gate voltage control circuitin that the first control circuitis replaced with a first control circuit# and the first switching circuitis replaced with a first switching circuit#.

30 30 31 31 32 32 The off-bias voltage control circuit# differs from the off-bias voltage control circuitin that the second control circuitis replaced with a second control circuit# and the second switching circuitis replaced with a second switching circuit#.

22 22 22 The first switching circuit# includes a PMOSFETP on the high side and an NMOSFETN on the low side.

22 22 The PMOSFETP and the NMOSFETN are connected in series.

22 The PMOSFETP is connected to the positive voltage source Vdd and is connected to an output node.

22 32 The NMOSFETN is connected to the output node and an output node of the second switching circuit.

32 32 32 The second switching circuit# includes a PMOSFETP on the high side and an NMOSFETN on the low side.

32 32 The PMOSFETP and the NMOSFETN are connected in series.

32 10 22 The PMOSFETP is connected to the source electrode of the power semiconductor elementand is connected to the output node. The output node is connected to the first switching circuit#.

32 The NMOSFETN is connected to the output node and the negative voltage source Vneg. The switching circuit according to the third embodiment is particularly effective for a power conversion apparatus to which, for example, a wide bandgap semiconductor is applied and which is applied to a high frequency drive application.

22 22 32 32 A CMOS circuit constituted by the PMOSFETP and the NMOSFETN and the PMOSFETP and the NMOSFETN according to the third embodiment will be described.

Since both the elements of the upper and lower arms are constituted by MOSFETs, the power consumption is lower than that in the case where these elements are constituted by bipolar transistors. In addition, as the switching frequency of the power inverter increases, the number of times of switching the gate drive circuit also increases accordingly. In other words, it is very useful for the high-frequency drive applications described above.

22 22 22 100 The output line of the PMOSFETP and the NMOSFETN swings between the power supply voltage Vdd applied to the high side of the PMOSFETP and the potential (the shallow off-bias voltage Vs or the deep off-bias voltage Vneg) applied to the low side. Further, a constant drive capability can be obtained regardless of the difference between the input voltage from the power supply voltage and the output voltage of the output line. With such a drive output, it is possible to realize the gate drive circuit# with high drive capability and high stability.

On the other hand, in a general push-pull circuit, the swing range of the output line is narrowed by the gate threshold voltage of the transistor elements on the upper and lower arms. In other words, when the output voltage is outside the swing range, the output of the push-pull circuit becomes floating, indicating an unstable operation.

100 10 In the gate drive circuit# according to the third embodiment, the switching circuit is realized by a CMOS circuit, it is possible to obtain high drive capability and high stability. These effects are expected to improve the characteristics of the power semiconductor deviceand prevent oscillation from being caused by fluctuations in the gate potential.

100 Although the advantages of the CMOS circuit have been described above, the CMOS circuit may also have disadvantages. At the time of switching the upper and lower arm elements, a through current may flow between the power supply voltage of the high side and the reference potential of the low side. This through current may increase the power consumption of the gate drive circuit. The increase in the power consumption makes the CMOS circuit inappropriate for the high-frequency drive operation, which contradicts the above-described advantages.

22 22 32 32 22 22 32 32 Therefore, a dead time period between the upper and lower arms may be generated before the PMOSFETP and the NMOSFETN and the PMOSFETP and the NMOSFETN. By providing an appropriate dead time period, it is possible to reduce a through current flowing into the CMOS circuit. For example, the signals applied to the gates of the PMOSFETP and the NMOSFETN and the PMOSFETP and the NMOSFETN may be controlled independently.

7 FIG. 2 FIG. 21 31 21 31 is a diagram illustrating a specific configuration of a first control circuit# and a second control circuit# according to the third embodiment. Since the basic element configuration and the like are the same as those of the first control circuitand the second control circuitillustrated in, the description thereof will not be repeated.

7 FIG. 21 21 21 With reference to, the first control circuit# includes a control unitA # and a delay circuitB #.

31 31 31 The second control circuit# includes delay circuitsA # andB #, an inverter IV, an AND circuit AD, and an OR circuit OR.

2 31 2 The AND circuit AD receives the external drive signal INvia the delay circuitB # and the inverter IV or receives the external drive signal INwithout any elements or additional circuits, and outputs an AND logic operation result to the OR circuit OR.

1 31 The OR circuit OR receives the external drive signal INvia the delay circuitA # or receives an input from the AND circuit AD, and outputs an OR logic operation result.

31 31 31 31 The delay circuitsA # andB # are configured to generate a delay signal. For example, the delay circuit may be an RC filter which is a general delay time adjustment circuit, or may include a Schmitt trigger element for tailoring a transmission signal. The delay amount of the delay circuitA # may be different from the delay amount of the delay circuitB #.

10 The OR circuit OR outputs an off-bias voltage control signal (“1”) when the power semiconductor elementis in a steady ON state with no switching operation, and outputs an off-bias voltage control signal (“0”) when the power semiconductor element is in a steady OFF state with no switching operation.

32 32 As a result, the PMOSFETP of the second switching circuit# repeats the ON operation and the OFF operation at a constant cycle.

1 31 32 32 On the other hand, the output of the off-bias voltage control signal changes complicatedly during the transient time of the switching operation. When the external drive signal INchanges from “1” to “0”, the OR circuit OR maintains the output of “1” for a period proportional to the delay amount of the delay circuitA #. In response, the OR circuit OR turns on the NMOSFETN of the second switching circuit# in response to the period where the output is maintained at “1”.

2 31 32 32 When the external drive signal INchanges from “0” to “1”, the AND circuit AD outputs a one-shot pulse signal proportional to the delay amount of the delay circuitB #. Accordingly, the OR circuit OR turns on the NMOSFETN of the second switching circuit# in response to the one-shot pulse signal.

22 22 21 20 32 32 31 30 10 According to the present embodiment, the PMOSFETP and the NMOSFETN are provided in the first control circuitincluded in the gate voltage control circuit, and the PMOSFETP and the NMOSFETN are provided in the second control circuitincluded in the off-bias voltage control circuit. As a result, it is possible to suppress gate oscillation or the like in high-frequency applications, while maintaining high characteristics of the power semiconductor element.

40 The configuration of the gate resistance control circuitaccording to the second embodiment may be further applied.

10 In a fourth embodiment, the voltage level control of the off-bias voltage applied to the gate of the power semiconductor elementwill be described.

8 FIG. 100 is a diagram illustrating a waveform of the gate voltage Vgs of the SiC-MOSFET to which the gate drive circuitof the present disclosure is applied.

8 FIG. illustrates a case where the period of applying the deep off-bias voltage is adjusted.

In the present embodiment, the on-bias voltage of the gate is set to +20 V, the shallow off-bias voltage Vs is set to 0 V, and the deep off-bias voltage Vneg is set to −5 V. The drive conditions were the same except for the period of the deep off-bias voltage Vneg.

The waveform LA shows a case where the application period of the off-bias voltage is shorter than that of the waveform LB. In other words, the two waveforms have different periods of the deep off-bias voltage Vneg.

30 The period of the deep off-bias voltage Vneg is adjusted by adjusting the time constant of the RC filter constituting the delay circuit included in the off-bias voltage control circuit.

Specifically, the delay amount of the delay circuit is adjusted by adjusting the capacitance of the capacitor, thereby adjusting the period during which the off-bias voltage is applied.

Specifically, in the case where two types of capacitance of 470 pF and 680 pF are provided as the capacitance of the capacitor in the delay circuit, the period of the deep off-bias voltage Vneg can be set to a shorter period by setting the capacitance of the capacitor to “470 pF”. Thus, it is possible to further reduce the stress on the gate oxide film.

For example, if the capacitor is a variable capacitor, it is possible to adjust the period of the off-bias voltage Vneg to an optimum period by setting the capacitance of the capacitor to an optimum capacitance.

100 40 In a fifth embodiment, another aspect relating to the operation of the gate drive circuitincluding the gate resistance control circuitaccording to the second embodiment will be described.

9 FIG. 101 is a diagram illustrating a timing chart when a gate drive circuitaccording to the fifth embodiment controls the gate of the power semiconductor element.

9 FIG. 101 100 With reference to, the basic operation of the gate drive circuitaccording to the fifth embodiment is the same as that of the gate drive circuitaccording to the second embodiment, and therefore the detailed description thereof will not be repeated.

5 FIG. 3 FIG. 42 40 4 5 4 As compared with the timing chart of, the bypass switching elementincluded in the gate resistance control circuitdescribed with reference tois turned on during an interval between time tband time tbwithin the period between time ton and time t.

9 FIG. 10 10 By this operation, as illustrated in, the gate voltage Vgs of the power semiconductor elementis quickly switched from the deep off-bias voltage Vneg to the shallow off-bias voltage Vs. As a result, the period of applying the deep off-bias voltage Vneg to the gate of the power semiconductor elementis reliably shortened.

4 42 10 4 10 10 Time tbat which the bypass switching elementis turned on is set to be between the time when the turn-on operation of the opposing arm element of the power semiconductor elementis completed and time t. With this setting, it is possible to suppress oscillation of the gate of the power semiconductor elementduring the turn-on period of the opposing arm element, and to avoid the risk of causing a false turn-on. In addition, it is also possible to obtain the effect of shortening the period of applying the deep off-bias voltage Vneg to the power semiconductor element.

4 FIG. 40 41 3 42 The present embodiment can be realized by providing additional elements to the configuration of. The additional element is provided with a function to control the gate resistance control circuitso as to reduce the value of the gate resistor, and to determine time tbat which the bypass switching elementis turned on.

10 4 Specifically, time information of time ton at which the opposing arm element of the power semiconductor elementis turned on is utilized to determine time tb.

10 40 31 30 3 For example, the time information of time ton may be acquired by providing an overvoltage detection circuit or a voltage change rate dVds/dt detection circuit between the drain electrode and the source electrode of the power semiconductor element. Alternatively, a gate current detection circuit may be connected in series with and adjacent to the gate resistance control circuit. By synchronizing the detection information of these detection circuits with the signal of the second control circuitincluded in the off-bias voltage control circuit, it is possible to adjust time tbto an appropriate time.

31 30 4 10 Alternatively, the second control circuitincluded in the off-bias voltage control circuitmay be provided with a state timer with preset times. For example, time tbmay be set by measuring a time taken to turn on the opposing arm element of the power semiconductor elementin an experiment performed in advance.

42 40 10 In the fifth embodiment, a time at which the bypass switching elementincluded in the gate resistance control circuitis turned on is added to the configuration according to the second embodiment. As a result, the period of applying the deep off-bias voltage Vneg to the gate of the power semiconductor elementcan be shortened more suitably.

102 In a sixth embodiment, the configuration of an integrated drive circuitwill be described.

10 FIG. 102 is a block diagram illustrating the integrated drive circuitaccording to the sixth embodiment.

10 FIG. 102 100 100 100 With reference to, the integrated drive circuitaccording to the sixth embodiment is different from the gate drive circuitin that it is an integrated circuit incorporated with two drive circuits of a gate drive circuitP and a gate drive circuitN.

10 FIG. The integrated drive circuit means that, for example, the upper arm and the lower arm are integrated and the power semiconductor elements are connected in series, and can be applied to a half-bridge circuit which is frequently seen in a power module in which the power semiconductor elements are packaged in 2-in-1 as illustrated in.

10 10 102 The power semiconductor elementP and the power semiconductor elementN connected in series to each other, i.e., the power semiconductor elements in the upper and lower arms, are driven by a single drive circuit, i.e., the integrated drive circuit.

1 2 The input signals are the external drive signal INand the external drive signal IN.

As described in the first embodiment, the external drive signal may be a logic pulse signal as long as the external drive signal IN is set to “1” during a period when a corresponding power semiconductor element should be turned on, and the external drive signal IN is set to “0” during a period when a corresponding power semiconductor element should be turned off.

1 10 20 2 10 20 In the present embodiment, the external drive signal INcontrols the gate of the power semiconductor elementP of the upper arm, and is input to the gate voltage control circuitP. The external drive signal INcontrols the gate of the power semiconductor elementN of the lower arm, and is input to the gate voltage control circuitN.

2 10 30 1 10 30 As described in the first embodiment, the external drive signal INfor notifying the timing of turning on the power semiconductor elementN of the lower arm, which is one of the opposing arm elements, is input to the off-bias voltage control circuitP. The external drive signal INfor notifying the timing of turning on the power semiconductor elementP of the upper arm, which is the other one of the opposing arm elements, is input to the off-bias voltage control circuitN.

100 With such a configuration, the integrated drive circuit performs the same operation as the gate drive circuitdescribed in the first embodiment.

100 100 102 10 10 30 30 30 30 The gate drive circuitP and the gate drive circuitN included in the integrated drive circuitbasically have the same circuit configuration, but if there are variations in the element characteristics between the power semiconductor elementsP andN of the upper and lower arms, the off-bias voltage control circuitsP andN may perform fine adjustment internally. For example, by adjusting the timing of the deep off-bias voltage Vneg and the shallow off-bias voltage Vs with respect to the off-bias voltage control circuitP and the off-bias voltage control circuitN, a more suitable operation of the power semiconductor elements can be achieved.

1 2 20 20 30 30 20 30 In the sixth embodiment, the external drive signal INand the external drive signal INare isolated by an isolating element having a sufficient dielectric strength, for example, an insulating element such as a photocoupler or an insulating transformer inside the gate voltage control circuitP and the gate voltage control circuitN, and inside the off-bias voltage control circuitP and the off-bias voltage control circuitN. The isolating element may be an isolator IC having a plurality of inputs and a plurality of outputs, and in such a configuration, the insulation process of the gate voltage control circuitP and the off-bias voltage control circuitP can be shared.

100 100 A positive voltage source Vdd_P to be supplied to the gate drive circuitP must be an insulated power source, and the potential of the positive voltage source Vdd_P is a floating potential with respect to the ground potential. Each of the deep off-bias voltage Vneg_P and the shallow off-bias voltage Vs_P included in the gate drive circuitP is also a floating potential with respect to the ground potential. Since the positive voltage source Vdd_P is a floating power supply, for example, a three-terminal regulator may generate an arbitrary potential, an appropriate deep off-bias voltage Vneg_P and an appropriate shallow off-bias voltage Vs_P.

10 100 102 With such a configuration, the power semiconductor elementP which corresponds to the upper arm element in the half bridge circuit can be electrically and safely operated by the gate drive circuitP included in the integrated drive circuit.

In the present embodiment, the configuration of a half bridge circuit has been described, but the method according to the fifth embodiment can also be applied to, for example, a power module for a three-phase inverter in which the power semiconductor elements are packaged in a 6-in-1 configuration.

102 10 10 The configuration according to the sixth embodiment includes an integrated drive circuitin which the drive circuit of the upper arm and the drive circuit of the lower arm are integrated to drive the upper and lower arm elements in the half-bridge circuit of the power conversion apparatus. As a result, the power semiconductor elementP of the upper arm and the power semiconductor elementN of the lower arm can be driven with a simple circuit configuration without requiring extra addition or complicated processing of external drive signals.

In a seventh embodiment, the power conversion apparatus according to the above-described embodiment is applied to a power conversion system. Although the present disclosure is not limited to a specific power conversion system, in the seventh embodiment, the present disclosure relates to a power conversion system to which a three-phase inverter is applied.

11 FIG. is a block diagram illustrating a configuration of a power conversion system according to the seventh embodiment.

11 FIG. 1000 1001 1004 1000 1001 1000 1000 With reference to, the power conversion system according to the seventh embodiment includes a power supply, a power conversion apparatus, and a load. The power supplyis a DC power supply that supplies DC power to the power conversion apparatus. The power supplycan be constituted by various types of power supplies, and may be constituted by, for example, a DC system, a solar cell, a storage battery, a rectifier circuit or an AC/DC converter connected to an AC system. In addition, the power supplymay be constituted by a DC/DC converter that converts DC power output from a DC system to a specific power.

1001 1000 1004 1000 1004 1001 1002 1003 1002 1002 The power conversion apparatusis a three-phase inverter connected between the power supplyand the load, and is configured to convert DC power supplied from the power supplyinto AC power and supply the AC power to the load. The power conversion apparatusincludes a main conversion circuitthat converts DC power into AC power and outputs the AC power, and a control circuitthat outputs a control signal for controlling the main conversion circuitto the main conversion circuit.

1004 1001 1004 The loadis a three-phase electric motor driven by the AC power supplied from the power conversion apparatus. The loadis not limited to a specific application, and may be any electric motor mounted on various electric devices, and may be used as, for example, an electric motor for a hybrid vehicle, an electric vehicle, a railroad vehicle, an elevator, or an air-conditioner.

1001 1002 1000 1004 Hereinafter, the power conversion apparatuswill be described in detail. The main conversion circuitincludes a power semiconductor element and a freewheeling diode (not shown), converts DC power supplied from the power supplyinto AC power by switching the power semiconductor element, and supplies the AC power to the load.

1002 1002 1002 1004 Although the main conversion circuitmay have various specific circuit configurations, the main conversion circuitaccording to the embodiment is a two-level three-phase full-bridge circuit, and can be constituted by six power semiconductor elements and six freewheeling diodes connected in reverse parallel to each other. Every two of the six power semiconductor elements are connected in series to form upper and lower arms, and each upper arm or each lower arm forms a phase (U phase, V phase, W phase) of the full bridge circuit. The output terminals of the upper and lower arms, in other words, the three output terminals of the main conversion circuitare connected to the load.

1002 The gate drive circuit described in the first to sixth embodiments and configured to drive each power semiconductor element may be applied to the main conversion circuit.

1002 1002 1003 The gate drive circuit generates a gate control signal that drives the power semiconductor element of the main conversion circuit, and supplies the gate control signal to the control electrode of the power semiconductor element of the main conversion circuit. Specifically, the control circuitoutputs an external drive signal for turning on the power semiconductor element and an external drive signal for turning off the power semiconductor element to the control electrode of each power semiconductor element. When the switching element is maintained at the ON state, the external drive signal is a voltage signal (ON signal) equal to or higher than the threshold voltage of the power semiconductor element, and when the switching element is maintained at the OFF state, the external drive signal is a voltage signal (OFF signal) equal to or lower than the threshold voltage of the power semiconductor element.

1003 1002 1004 The control circuitcontrols the power semiconductor element of the main conversion circuitso that the desired power is supplied to the load.

1002 1004 1002 1002 Specifically, the control circuit calculates a time (ON time) during which each power semiconductor element of the main conversion circuitshould be turned on based on the power to be supplied to the load. For example, the main conversion circuitmay be controlled by a PWM control that modulates the ON time of the power semiconductor element according to the voltage to be output. Then, a control command (external drive signal) is output to a gate drive circuit included in the main conversion circuitso that an ON signal is output to the power semiconductor element that should be turned on or an OFF signal is output to the power semiconductor element that should be turned off at each time point.

1002 In the power conversion apparatus according to the present embodiment, since the gate drive circuit described above that constitutes the main conversion circuitis applied, it is possible to improve reliability.

In the present embodiment, the present disclosure is applied to a two-level three-phase inverter, but the present disclosure is not limited thereto, and it can be applied to various types of power conversion apparatuses. In the present embodiment, a two-level power conversion apparatus is used, but a three-level or multi-level power conversion apparatus may be used, and the present disclosure may be applied to a single-phase inverter which supplies electric power to a single-phase load. The present disclosure can also be applied to a DC/DC converter or an AC/DC converter which supplies electric power to a DC load or the like.

In addition, the power conversion apparatus to which the present disclosure is applied is not limited to the case where the load is an electric motor, and may be used as a power supply device of an electric discharge machine, a laser cutting machine, an induction heating cooker, or a non-contact power supply system, or may be also used as a power conditioner of a photovoltaic power generation system, a power storage system, or the like.

It should be understood that the embodiments disclosed herein are illustrative and non-restrictive in all respects. Furthermore, it goes without saying that there is no problem to suitably combine a plurality of embodiments, and it is desirable to efficiently and economically utilize the power conversion apparatus by further enhancing the effects of each embodiment.

The scope of the present invention is defined by the terms of the claims rather than the description of the embodiments above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

10 10 10 20 20 20 21 22 30 30 30 31 32 40 41 42 100 100 100 101 102 1000 1001 1002 1003 1004 ,N,P: power semiconductor element;,N,P: gate voltage control circuit;: first control circuit;: first switching circuit;,N,P: off-bias voltage control circuit;: second control circuit;: second switching circuit;: gate resistance control circuit;: gate resistor;: bypass switching element;,N,P,: gate drive circuit;: integrated drive circuit;: power supply;: power conversion apparatus;: main conversion circuit;: control circuit;: load.