System for and Method of Inspecting Semiconductor Devices, and Method of Manufacturing the Devices Including the Method

This application is based on and claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2025-0030734, filed on Mar. 10, 2025, in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety.

The disclosure relates to a system and method of inspecting semiconductor devices, and a method of manufacturing the semiconductor devices by using the method. More specifically, the disclosure relates to a method of inspecting a high aspect ratio contact (HARC) structure in semiconductor devices by using a physically vibrating transducer.

As the integration density of semiconductor devices increases, vertical or three-dimensional (3D) semiconductor devices are being investigated as an alternative to conventional planar semiconductor devices. A semiconductor device having a vertical structure may include a structure extending vertically on a substrate. However, as the integration density of semiconductor devices increases, the number of layers stacked in a vertical direction may also increase, and accordingly, a precise method of inspecting semiconductor devices is required.

The disclosure may provide a system for inspecting semiconductor devices with improved reliability.

The disclosure provides a method of inspecting semiconductor devices with improved reliability.

The disclosure provides a method of manufacturing semiconductor devices with improved reliability.

However, the disclosure is not limited to the problems mentioned above, and other problems may be clearly understood by those skilled in the art based on the description below.

One or more embodiments of the disclosure, may provide a method of inspecting semiconductor devices, the method including: selecting a type of a target structure and a type of a target defect based on a semiconductor device including at least one layer, selecting a filter based on the target structure and the target defect, performing an ultrasonic signal simulation based on the target structure, selecting, based on the ultrasonic signal simulation, a type of probe configured to generate an ultrasonic signal by applying a vibration to the semiconductor device, setting a frequency of the vibration based on the ultrasonic signal simulation, generating the ultrasonic signal by applying, using the tip, the vibration to the semiconductor device, measuring the ultrasonic signal, processing the measured ultrasonic signal using the selected filter, performing a fitting for each of a signal generated by the ultrasonic signal simulation and the measured ultrasonic signal processed by the selected filter, and determining an accuracy of the fitting.

One or more embodiments of the disclosure, may provide a method of inspecting semiconductor devices, the method including: selecting, based on a semiconductor device, a type of a target structure and a type of a target defect to be inspected, selecting a filter based on the target structure and the target defect, performing an ultrasonic signal simulation based on the target structure, selecting, based on the ultrasonic signal simulation, a type of a probe configured to generate an ultrasonic signal by applying a vibration to the semiconductor device, setting a frequency of the vibration based on the ultrasonic signal simulation, generating the ultrasonic signal by applying, using the tip, the vibration to the semiconductor device, measuring the ultrasonic signal, processing the measured ultrasonic signal using the selected filter, performing a fitting for each of a signal generated by the ultrasonic signal simulation and the processed measured ultrasonic signal, determining an accuracy of the fitting, wherein, when the determined accuracy does not satisfy a reference value, the method may further include: repeating, based on a reference tool including a different filter and a different ultrasonic signal simulation, the performing the fitting and the determining the accuracy of the fitting, wherein, when the determined accuracy satisfies the reference value, the method may further include: quantifying one or more measurement values for the target structure and/or the target defect, wherein the measuring the ultrasonic signal may further include: measuring a signal based on a vertical stack of the semiconductor device measuring a reference signal, and measuring a target structure of the semiconductor device.

One or more embodiments of the disclosure, may provide a method of manufacturing a semiconductor device, the method including: preparing a wafer, performing a semiconductor process on the wafer, performing a shape profile inspection on the wafer subjected to the semiconductor process, and performing a subsequent semiconductor process, wherein the performing the shape profile inspection includes: selecting respective types of a target structure and a target defect to be inspected, selecting a filter based on the target structure and the target defect, performing an ultrasonic signal simulation based on the target structure, selecting, based on the ultrasonic signal simulation, a type of a probe configured to generate an ultrasonic signal by applying a vibration to the semiconductor device, setting a frequency of the vibration based on the ultrasonic signal simulation, generating the ultrasonic signal by applying, using the tip, the vibration to the semiconductor device, measuring the ultrasonic signal, processing the measured ultrasonic signal using the selected filter, performing a fitting for each of a signal generated by the ultrasonic signal simulation and the processed measured ultrasonic signal, determining an accuracy of the fitting, wherein, when the determined accuracy does not satisfy a reference value, the performing the shape profile inspection may further include: repeating, based on a reference tool including a different filter and a different ultrasonic signal simulation, the performing the fitting and the determining the accuracy of the fitting, wherein, when the determined accuracy satisfies the reference value, the performing the shape profile inspection may further include: quantifying one or more measurement values for the target structure and/or the target defect, wherein the measuring the ultrasonic signal may further include: measuring a signal based on a vertical stack of a semiconductor device, measuring a reference signal, measuring the target structure of the semiconductor device, generating an arbitrary waveform, transmitting the generated arbitrary waveform to a signal transmission and reception apparatus included in a system configured to inspect semiconductor devices, and switching a type of a signal of the signal transmission and reception apparatus to a pulse or an echo, wherein, when the type of the signal is switched to the pulse, the measuring the ultrasonic signal may further include: generating an ultrasonic pulse as the pulse, by a signal transmission portion of the signal transmission and reception apparatus, and transmitting, by the signal transmission portion, the ultrasonic pulse to the semiconductor device, wherein information of the echo, which is based on the semiconductor device and received by a signal receiving portion of the signal transmission and reception apparatus, is transmitted to a switch portion of the signal transmission and reception apparatus, wherein, when the type of the signal is switched to the echo, the measuring the ultrasonic signal may further include: measuring the echo using an oscilloscope, and collecting data measured by the oscilloscope using data acquisition (DAQ). may further include may further include

One or more embodiments of the disclosure, may provide a system for inspecting semiconductor devices may include a signal generation apparatus configured to generate an ultrasonic signal for inspecting a semiconductor device, a signal transmission and reception apparatus including a signal transmission portion configured to transmit a pulse signal, which is an ultrasonic signal delivered from the signal generation apparatus, to the semiconductor device, and a signal receiving portion configured to receive an echo signal, which is the ultrasonic signal reflected from the semiconductor device, and a signal processing apparatus configured to process the signal delivered from the signal transmission and reception apparatus, wherein the signal generation apparatus may include a position controller configured to control a position of a wafer including the semiconductor device, a waveform generator configured to generate the pulse signal, and a waveform amplifier configured to amplify a waveform of the pulse signal.

In one or more embodiments the signal transmission and reception unit may further include a switch portion configured to perform switching of the pulse signal and the echo signal, the signal transmission portion may include a transducer placed above a tip, the signal receiving portion may include a probe, and may be configured to be replaceable, and the tip may physically contact the semiconductor device.

In one or more embodiments the signal processing unit may include a generator-side waveform amplifier configured to amplify a waveform of the echo signal, an oscilloscope configured to receive and obtain information of the echo signal, and a data acquisition system configured to collect the information of the echo signal.

In one or more embodiments the position controller may be configured to control positions of the wafer, the transducer, and the probe based on result values collected in the data acquisition system, and to control the result values.

In one or more embodiments the transducer may be configured to physically vibrate the semiconductor device in a range of about 1 GHz to about 20 GHz and to generate the ultrasonic signal.

In one or more embodiments a diameter of a contact area where the transducer comes into contact with the semiconductor device may be within a range of about 100 nm to about 5000 nm.

In one or more embodiments the signal generation apparatus, the signal transmission and reception apparatus, and the signal processing apparatus may be configured to measure the target structure of the semiconductor device, measurement of the target structure of the semiconductor device may include measuring an error value caused by measurement equipment, adjusting a zero point of the measured value, and measuring a specimen after the zero point adjustment and, in plan view, the measurement may be sequentially performed for at least nine regions using a single transducer.

In one or more embodiments the measurement of the target structure of the semiconductor device may include setting a frequency range, applying vibration to the semiconductor device using the transducer while varying the frequency within the set range, selecting and measuring a first resonant frequency at which resonance first occurs within the frequency range, and selecting and measuring a second resonant frequency at which resonance second occurs within the frequency range, wherein the signal processing unit may be configured to extract a horizontal structure according to a vertical position of the semiconductor device, based on measurement values obtained from each of the first resonance frequency and the second resonance frequency.

In one or more embodiments the measurement of the target structure of the semiconductor device may include setting a frequency range of vibration, applying vibration to the semiconductor device by using the transducer while varying the frequency within the set range, selecting a frequency at which no resonance occurs within the set frequency range, and measuring by using the selected frequency, wherein the signal processing unit may be configured to extract a vertical structure according to a horizontal position of the semiconductor device, based on measurement values obtained from the frequency at which no resonance occurs.

In one or more embodiments the semiconductor device may include at least one layer, and a hole area formed inside the semiconductor device may have a tapered shape in which a horizontal cross-sectional area thereof gradually decreases along the vertical direction.

The one or more embodiments described herein may be subject to various modifications and may take on different forms, and some one or more embodiments are illustrated in the drawings and described in detail below. However, this is not intended to limit the one or more embodiments to any particular disclosed forms. The one or more embodiments described below are merely illustrative, and various modifications may be derived therefrom.

The use of all examples or exemplary terms herein is solely for the purpose of describing the disclosure in detail and is not intended to limit the scope of the disclosure unless otherwise defined by the claims.

Unless otherwise specified, in the disclosure, a vertical direction is defined as a Z direction, and a first horizontal direction and a second horizontal direction may be defined as horizontal directions perpendicular to the Z direction, respectively. The first horizontal direction may be referred to as an X direction, and the second horizontal direction may be referred to as a Y direction. A vertical level may refer to a height level along the vertical direction (Z direction). A horizontal width in the first horizontal direction may refer to a length in the horizontal direction (X and/or Y direction), and a vertical length may refer to a length in the vertical direction (Z direction).

1 FIG. is a diagram illustrating a flowchart of a method of inspecting semiconductor devices, according to an embodiment.

1 FIG. 6 FIG. 6 FIG. 1 10 100 10 100 10 Referring to, a method Sof inspecting semiconductor devices may be a method of inspecting a semiconductor deviceofincluding at least one layer, and may include operation Sof respectively selecting a type of a target structure of the semiconductor deviceand a type of a target defect within the target structure, which are to be inspected. In operation S, layer information in the depth direction of the stack-type semiconductor deviceofto be measured may be identified.

1 150 100 10 200 10 6 FIG. The method Sof inspecting semiconductor devices may include operation S, which is performed following operation S, of selecting a filter corresponding to (i.e., based on, related to, and/or matching) both the target structure and the target defect of the semiconductor deviceof, and operation Sof performing an ultrasonic signal simulation for the target structure of the semiconductor device.

1 300 200 400 300 10 500 400 6 FIG. The method Smay include operation Sof selecting a type of a probe included in a signal transmission portion of a signal transmission and reception unit and setting a frequency to be applied to the tip, which is performed following operation S, operation Sof measuring a response signal while applying an ultrasonic signal of the frequency set in operation Sto the semiconductor deviceof, and operation Sof processing the signal measured in operation S.

500 150 150 500 150 500 150 500 600 23 24 FIGS.and 1 FIG. In the process of processing the signal in operation S, the filter selected in operation Smay be used. That is, the filter selected in operation Smay be applied in the Sstep. In the present invention, “applying a filter” can be understood as a post-processing step for correcting or compensating the data after measurement, using a simulated impulse response of a specific target structure-defect combination. In addition, if the filter is considered an impulse response, it may include the tip transfer function to compensate for the measurement transfer function. The processing of the signal may be performed by a stored filter based on a pulse train composed of ultrasonic pulses previously obtained for various structures before performing the inspection. A description of a process in which the filter selected in operation Sis used in operation Sis provided with reference to. Furthermore, in, the filter selected in operation Sis shown as being applied to S, but it may also be additionally applied in operation S.

1 500 600 600 200 500 400 600 10 10 400 6 FIG. 6 FIG. The method Smay include, following operation S, operation Sof performing fitting between the simulated signal and the measured signal. The simulated signal to be used for performing fitting in operation Sis the simulation result obtained in operation S, and the measured signal to be used for performing fitting refers to the result obtained by completing processing in operation Son the signal measured in operation S. While performing the fitting in operation S, the fitting may be performed for each frequency of the ultrasonic signal. The simulated signal may serve as a reference signal for the measured signal to be used in performing the fitting. That is, information about a vertical stack of the semiconductor deviceofto be measured may be obtained, an inflection point of an inter-layer in the layer structure of the semiconductor deviceofmay be identified, and the simulation may be performed for a shape most similar to the identified one. A “most similar” shape may be determined based on one or more parameters and/or dimensions related to the shape(s) under consideration, but is not limited to any particular parameter, dimension, and/or combination thereof. Furthermore, in one or more embodiments, any parameters and/or dimensions of interest may be assigned a corresponding weighted value score based on user preferences. Operation Smay include obtaining ultrasonic signals by measuring based on three-dimensional (3D) scanning in individual layers per target.

1 700 600 700 100 The method Smay include operation Sof determining accuracy for fitting values obtained in operation S. A reference threshold for the accuracy to be determined in operation Smay be preset in operation S.

700 800 700 800 100 100 150 200 800 800 700 800 100 150 200 800 600 700 700 800 a b b a b b a When the accuracy determined in operation Ssatisfies a preset threshold, operation Sof quantifying a measurement value for the target structure and the target defect within a semiconductor device may finally be performed. More specifically, quantification may be performed for a profile having a 3D structure with respect to each individual unit of a target. When the accuracy determined in operation Sdoes not satisfy the preset threshold, operation Sof measuring by another reference tool may be performed. The other reference tool may refer to a set of settings in which respective types of different target structures and different target defects are selected in operation S, and based on the different values selected in operation S, a different filter is selected in operation S, and different simulation values are selected in operation S. After measuring with the other reference tool selected in operation S, operation Smay be performed for the measured values. In other words, when the determined accuracy does not satisfy a reference value upon performing operation S, the operation of “using a reference tool” in Smay repeat each of operations S, S, and Susing a different target structure, a different target defect, a different filter, and/or different simulation values. Then, operation Smay repeat the “fitting” step of operation Sbased on any different simulation values associated with the “reference tool”, and may also repeat the “determining an accuracy” step of operation S. Finally, if the repeated operation Sdetermines that the fitting is accurate, then operation Smay perform the step of “quantifying structure defect measurement values”.

100 150 200 300 100 1 400 100 200 1 200 222 221 221 210 221 222 1 4 FIG. 4 FIG. 4 FIG. 4 FIG. 4 FIG. Operations S, S, S, and Smay be performed in a signal generation unit(e.g., a signal generation apparatus or device) ofincluded in a systemoffor inspecting semiconductor devices. Operation Smay be performed in the signal generation unitillustrated in, and the signal transmission and reception unitincluded in the semiconductor device inspection systemof. In the present invention, the signal transmission and reception unitmay be understood as “a probe” configuration that supports the transducerand the tipand applies a controlled force to the tip. (e.g., an apparatus or device comprising a switch portion, a tip, and a transducer) included in the systemfor inspecting semiconductor devices of.

221 10 1 2 222 The tipof the present invention may be configured to ensure contact with the sampleand to transfer acoustical signals during transmission SGand reception SG. The transducerof the present invention may be configured to convert electrical energy into acoustical energy during transmission and to convert acoustical energy into electrical energy during reception.

1 222 100 2 200 100 1 2 600 700 800 300 1 800 100 200 300 4 FIG. 4 FIG. 4 FIG. 4 FIG. 4 FIG. 4 FIG. 4 FIG. 4 FIG. 4 FIG. a b More specifically, signal transmission in signal measurement may be performed by generating a transmission signal, which is a pulse SG, at the transducer, which is the signal transmission portion of the signal generation unitof; and signal receiving in the signal measurement may be performed by receiving an echo SG, which is a received signal, at the signal transmission and reception unit (probe), which is a signal receiving portion of the signal generation unitof. Hereinafter, “the pulse SG” of, which is the transmission signal may also be referred to as a “pulse signal” or a “first signal.” Hereinafter, the reception signal, which is the echo SGof, may also be referred to as an “echo signal” or a “second signal.” Operations S, S, and Smay be performed in a signal processing unitofincluded in the systemoffor inspecting semiconductor devices. Operation Smay be performed together in the signal generation unitof, the signal transmission and reception unitof, and the signal processing unitof.

2 FIG. is a detailed flowchart of a signal measurement operation included in a method of inspecting semiconductor devices according to an embodiment.

2 FIG. 1 FIG. 2 FIG. 400 400 400 400 400 400 400 400 400 400 400 400 400 400 400 a b c a b c b a c a b b a a. is to be referred to together with. Referring to, operation Smay include operation Sof measuring a signal for the vertical stack, operation Sof measuring the reference signal to be compared with the measured signal, and operation Sof measuring the target structure of a semiconductor device. The “signal for the vertical stack” may be a signal that is transmitted through and, thus, indicative of a structure of the vertical stack, such that the signal may be considered based on and/or related to the vertical stack. Furthermore, “measuring the target structure” may include identifying, gathering, and/or processing data or information related to any parameters, dimensions, shapes, orientations, or other characteristics of the target structure. Operations S, S, and Smay be performed simultaneously in parallel, but operation Smay be performed after operation S, and finally, operation Smay be sequentially performed in series. The measuring a signal of the vertical stack means prioritizing the measurement of signals for vertical stacks adjacent to a target to be actually measured in the semiconductor device. Signals measured in operation Smay partially overlap with the reference signal measured in operation S. The signals measured in operation Smay correspond not only to signals for the vertical stacks adjacent to a target to be actually measured, but also to measured signals for other semiconductor devices having a structure similar to that of the signal measured in operation S, based on the vertical stack signal measured in operation S

400 b In the present invention, the reference signal may refer to a signal representing the result at a known location where no defects are expected. Therefore, the Sstep can be understood as reading the signal from a pre-stored database. According to one or more embodiments, the invention can obtain the reference signal at a location where the process proceeds normally, the 3D structural profile of the individual unit is well formed, and uniformity with surrounding units may be maintained.

3 FIG. 4 FIG. is another detailed flowchart of a signal measurement operation included in a method of inspecting semiconductor devices according to an embodiment.is a schematic diagram illustrating a configuration of a system for inspecting semiconductor devices according to an embodiment.

3 4 FIGS.and 1 2 FIGS.and 3 FIG. 10 400 400 410 410 221 are referenced together with. Hereinafter, a sample inmay correspond to a specimen or the semiconductor deviceto be inspected. In the disclosure, a “sample” may correspond to a “specimen” in operation S. Operation Sof measuring the ultrasonic signal may include operation Sof generating an arbitrary waveform. Operation Smay include generating a set waveform, which may correspond to a signal for driving the tip. The arbitrary waveform may include a pulse wave, a sine wave, a cosine wave, and a square wave.

400 411 200 410 200 410 1 2 Operation Smay include operation Sof delivering a signal of the generated waveform to the signal transmission and reception unit, which is performed after operation S. The signal transmission and reception unitmay be configured to convert (transmit) an electric signal output in operation Sinto a pulse SG, which is an ultrasonic signal, and to receive the echo SGthat is returned by reflection.

400 420 1 2 410 420 210 200 210 100 200 200 210 2 200 300 200 200 221 221 200 222 210 1 2 1 10 2 10 may Operation Smay include operation Sof switching between the pulse SGand the echo SG, which is performed after operation S. Operation Smay be performed in the switch portionincluded in the signal transmission and reception unit. The switch portionmay deliver an electrical signal generated in the signal generation unitto the signal transmission and reception unit, the signal transmission and reception unitmay convert the electrical signal into an ultrasonic signal, and the switch portionmay deliver the echo SGreceived at the signal transmission and reception unit(probe)to the signal processing unit. According to one embodiment, the signal transmission and reception unit(probe)in the present invention may be a Half-Wavelength Contact Acoustic Microscopy (HaWaCAM) cantilever. In addition, the signal transmission and reception unit (probe)may include a tip, and an electrode for electrical contact. In the present invention, the tipincluded in the signal transmission and reception unit (probe)be understood as the part located beneath the transducerthat makes contact with the sample. That is, the switch portionmay be configured to switch between the pulse SG, which is the transmitted signal, and the echo SG, which is the reflected signal. In other words, the pulse SGmay be the signal that is transmitted as an ultrasonic signal to the semiconductor device, and the echo SGmay correspond to the signal that is reflected and returned from the semiconductor device.

400 421 1 420 422 1 10 2 422 10 420 210 2 300 a a Operation Smay include operation Sof generating an ultrasonic wave when switched to the pulse SGin operation S, and operation Sof transmitting the pulse SGgenerated to the semiconductor device, which is the specimen. The echo SGgenerated by the reflection of the ultrasonic wave transmitted in operation Sat the semiconductor device, which is the specimen, may be delivered to operation S. The switch portionmay deliver the received echo SGto the signal processing unit.

400 2 420 421 2 422 320 300 421 2 421 2 b a b b Operation S, when the signal is switched to the echo SGin operation S, may include operation Sof measuring the echo SG, received in operation S, by using an oscilloscopeincluded in the signal processing unit. Operation Smay be performed to visually record the echo SG, which is the reflected signal, in a time domain. That is, operation Smay correspond to providing amplitude and time information of the echo SG.

400 422 421 422 422 310 310 b b b b Operation Smay include operation Sof performing data acquisition (DAQ) after operation S. Operation Smay digitize oscilloscope data and deliver the digitized data to an analysis software. Operation Smay be performed in a data acquisition system. The data acquisition systemmay correspond to a server or personal computer (PC), each including a memory, and a central processing unit (CPU).

400 431 2 422 431 1 2 431 10 10 a b a a Operation Smay include operation Sof measuring an arrival time of the echo SG, which is the reflected signal, based on the data collected in operation S. Operation Smay measure a time of flight, which is the time taken for the signal to travel round trip through a sample. The time of flight may correspond to the sum of the travel time of the pulse SGand the travel time of the echo SG. Operation Smay measure the arrival time of the reflected signal to analyze a distance and a property inside the sample, and the analysis result may be used to calculate the thickness or internal structural information of the sample. The “property” inside the sample may be related to a structural, electrical, mechanical, and/or material characteristic of the semiconductor device, but is not particularly limited thereto. With regard to the semiconductor device, one or more embodiments may measure film thickness, mechanical strength, material stiffness and/or hardness, prevalence and nature of structural defects, as well as structural and material uniformity of components, films, and other features.

400 432 431 2 1 a a Operation Smay include operation S, which is performed after operation S, of comparing the echo SG, which is the reflected signal, to the pulse SG, which is the original signal, to measure a time delay and a reflection intensity, and analyzing internal structural or shape information of the sample based on a correlation therebetween.

400 431 422 431 b b b Operation Smay include operation Sof performing a fast Fourier transform (FFT) on the data collected in operation S. Operation Smay be configured to convert a time-domain signal into a frequency-domain signal and to calculate amplitude and phase information according to frequencies, or to analyze frequency dependence of the signal.

400 432 431 431 400 433 431 b b b b b. Operation Smay include operation S, which is performed after operation S, of extracting a frequency-dependent signal. Operation Smay analyze how the signal responds at a specific frequency by analyzing the signal, which is generated as a result of the FFT and varies with frequencies, and may thereby analyze physical characteristics of the sample, such as thickness, impedance, or internal defects. Operation Smay include operation Sof obtaining amplitude and phase information of the signal extracted in operation S

400 440 432 433 450 450 2 420 1 422 a b a Operation Smay include operation Sof extracting shape deformation inside the sample based on the data analyzed in operation Sand the amplitude and phase information obtained in operation S, and operation Sof determining an internal structure of the sample. In operation S, information on the echo SGswitched in operation Sas well as information on the pulse SGtransmitted in operation Smay be used together.

4 FIG. 1 100 200 300 1 100 10 200 1 100 10 2 10 210 1 2 300 200 Referring to, the systemfor inspecting semiconductor devices may include the signal generation unit, the signal transmission and reception unit, and the signal processing unit. In the system, the signal generation unitmay be configured to generate the ultrasonic signal for inspecting the semiconductor device, the signal transmission and reception unitmay include the signal transmission portion configured to transmit the pulse SG, which is the ultrasonic signal delivered from the signal generation unit, to the semiconductor device, the signal receiving portion configured to receive the echo SG, which is the ultrasonic signal reflected from the semiconductor device, and the switch portionconfigured to control switching between the pulse SGand the echo SG, and the signal processing unitis configured to process the signal delivered from the signal transmission and reception unit.

100 110 10 221 222 200 120 130 The signal generation unitmay include a position controllerconfigured to control a position of a wafer including the semiconductor deviceand positions of the tipas a signal transmission portion and the transduceras a signal receiving portion of the signal transmission and reception unit, a waveform generatorconfigured to generate the pulse signal, and a generator-side waveform amplifierconfigured to amplify a waveform of the pulse signal.

300 330 2 320 310 The signal processing unitmay include a processing-side waveform amplifierconfigured to amplify a waveform of the echo SG, the oscilloscopeconfigured to receive and obtain information of the echo signal, and the data acquisition systemconfigured to collect the information of the echo signal.

110 222 221 310 The position controllermay be configured to control positions of the wafer, the transducer, and the tipbased on result values collected in the data acquisition system, and to control the result values.

210 420 120 320 The switch portionmay switch between the pulse and the echo according to operation S, receive the pulse generated by the waveform generator, and deliver the echo to the oscilloscope.

130 120 200 330 200 320 130 330 The generator-side waveform amplifiermay be configured to amplify the signal delivered from the waveform generator, and the amplified signal may be delivered to the signal transmission and reception unit. In contrast, the processing-side waveform amplifiermay be configured to amplify the signal delivered from the signal transmission and reception unitand the amplified signal may be delivered to the oscilloscope. That is, the generator-side waveform amplifiermay amplify the signal to be applied as vibration to the specimen, and the processing-side waveform amplifiermay amplify the signal reflected from the specimen.

221 10 10 100 221 10 10 5 7 FIGS.to The tipmay be physically in contact with an upper surface of the semiconductor deviceand may apply vibration to the semiconductor deviceby using the signal delivered from the signal generation unit. The tipmay be configured to generate the ultrasonic signal by applying vibration to the semiconductor devicewithin a range of about 1 GHz to about 50 GHz. The semiconductor devicemay include one or more layers, and details thereof are described with reference to.

5 FIG. is an equivalent circuit diagram of a memory cell array of a semiconductor device according to an embodiment.

5 FIG. 2 FIG. 1 2 1 1 2 1 1 2 1 Referring to, a memory cell array MCA may include a plurality of memory cell strings MS. The memory cell array MCA may include a plurality of bit lines BL: BL, BL, . . . , BLm-, BLm, a plurality of word lines WL: WL, WL, . . . , WLn-, WLn, at least one string select line SSL, at least one ground select line GSL, and a common source line CSL. The plurality of memory cell strings MS may be formed between the plurality of bit lines BL: BL, BL, . . . , BLm-, BLm and the common source line CSL.illustrates a case where each of the plurality of memory cell strings MS includes two string select lines SSL, but the technical ideas of the disclosure is not limited thereto. For example, each of the plurality of memory cell strings MS may include one string select line SSL.

1 2 1 1 2 1 Each of the plurality of memory cell strings MS may respectively include a string select transistor SST, a ground select transistor GST, and a plurality of memory cell transistors MC, MC, . . . , MCn-, MCn. Drain areas of the string select transistors SST may be connected to the bit lines BL: BL, BL, . . . , BLm-, BLm, and source areas of the ground select transistors GST may be connected to the common source line CSL. The common source line CSL may be a region where source regions of a plurality of ground select transistors GST are commonly connected.

1 2 1 1 2 1 The string select transistor SST may be connected to the string select line SSL, and the ground select transistor GST may be connected to the ground select line GSL. Each of the plurality of memory cell transistors MC, MC, . . . , MCn-, MCn may be connected to the plurality of word lines WL: WL, WL, . . . , WLn-, WLn, respectively.

6 FIG. is a cross-sectional view of a semiconductor device according to an embodiment.

6 FIG. 10 Referring to, the semiconductor devicemay include a wafer W having a memory cell region MEC, a connection region CON, and a peripheral circuit region PERI. According to one or more embodiments, an active region AC may be defined in a memory cell region MEC of the wafer W, and a peripheral active region PAC may be defined in the peripheral circuit region PERI.

10 3 FIG. According to one or more embodiments, the peripheral active region PAC may be defined by a device separation layer DSF. For example, the memory cell array MCA may be formed on the active region AC of the memory cell region MEC according to a manufacturing process of the semiconductor devicedescribed below. For example, the connection region CON may be positioned adjacent to an edge side of the memory cell region MEC. The memory cell region MEC may be separated from the peripheral circuit region PERI by the connection region CON. Although only the connection region CON arranged on one side of the memory cell region MEC is illustrated in, the connection region CON may be arranged on each side of the first horizontal direction X of the memory cell region MEC.

According to one or more embodiments, the device separation layer DSF defining the peripheral active region PAC may be formed in a peripheral circuit region PERI of the wafer W. A peripheral transistor may be formed on the peripheral active region PAC. The peripheral transistor may constitute a part of a plurality of circuits formed on the peripheral circuit region PERI. The peripheral transistor may be configured to be electrically connected to the memory cell region MEC through a wiring structure arranged in the connection region CON. The peripheral transistor may include a peripheral gate PG and a peripheral source/drain area PSD formed within the peripheral active region PAC on either side of the peripheral gate PG. In one or more embodiments, unit elements such as resistors and capacitors may be further arranged on the peripheral circuit region PERI. According to one or more embodiments, the wafer W may include Si, Ge, or SiGe.

According to one or more embodiments, a plurality of insulating films IF and a plurality of sacrificial layers (not shown) may be alternately stacked one layer at a time on the memory cell region MEC and the connection region CON of the wafer W. After the plurality of sacrificial layers (not shown) are removed during a process, the ground select line GSL and a conductive pad region CPR may be formed at the location where the sacrificial layers were removed. According to one or more embodiments, the plurality of insulating films IF may include silicon oxide, silicon nitride, or silicon oxynitride. According to one or more embodiments, the plurality of sacrificial layers (not shown) may include silicon nitride, silicon carbide, or polysilicon. For example, the plurality of insulating films IF may include silicon oxide, and the plurality of sacrificial layers (not shown) may include silicon nitride.

After forming an etch-stop layer (not shown) covering the uppermost insulating film IF among the plurality of insulating films IF, a portion of each of the plurality of insulating films IF and the plurality of sacrificial layers (not shown) is removed by a photolithography process in the connection region CON so that one end of each of the plurality of insulating films IF and the plurality of sacrificial layers (not shown) may form a step-like structure STC having a width that gradually decreases in the horizontal direction away from the wafer W. After that, an insulating block IB covering the step-like structure STC and a peripheral transistor TR may be formed on a substrate WC.

1 1 1 FIG. 1 FIG. Thereafter, a plurality of channel holes extending in the vertical direction Z are formed through the plurality of insulating films IF and the plurality of sacrificial layers (not shown) in the memory cell region MEC, and a gate dielectric layer GDF, a channel region CA, and a buried insulating film BUIF are formed inside each of the plurality of channel holes, thereby forming a plurality of channel hole-burying structures. Before forming the gate dielectric layer GDF, the channel region CA, and the buried insulating film BUIF inside each of the plurality of channel holes, the method Sdescribed with reference tomay be performed. That is, the plurality of channel holes may correspond to one of hole areas inspected by the method Sin. The plurality of channel holes may be defined as region A.

According to one or more embodiments, the gate dielectric layer GDF may include silicon oxide, hafnium oxide, aluminum oxide, zirconium oxide, tantalum oxide, silicon nitride, boron nitride, silicon boron nitride, impurity-doped polysilicon, a metal oxide, or combinations thereof. The metal oxide may include hafnium oxide, aluminum oxide, zirconium oxide, tantalum oxide, or combinations thereof. According to one or more embodiments, the channel region CA may have a cylindrical shape. The channel region CA may include doped polysilicon or undoped polysilicon. According to one or more embodiments, the buried insulating film BUIF may fill the interior space of the channel region CA. The buried insulating film BUIF may include an insulating material. For example, the buried insulating film BUIF may include silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof. In some one or more embodiments, the buried insulating film BUIF may be omitted, in which case the channel region CA may have a pillar structure without internal space.

Thereafter, a middle insulating film MDIF covering the plurality of channel hole-burying structures, the step-like structure STC, and the insulating block IB may be formed over the memory cell region MEC, the connection region CON, and the peripheral circuit region PERI, a plurality of contact holes may be formed in the middle insulating film MDIF to expose upper surfaces of the plurality of channel hole-burying structures, and a plurality of drain areas DA may be formed in the plurality of contact holes to form a channel structure CS. The middle insulating film MDIF may be formed to have a planarized top surface spanning the memory cell region MEC, the connection region CON, and the peripheral circuit region PERI. According to one or more embodiments, the middle insulating film MDIF may include silicon oxide, silicon nitride, or silicon oxynitride. According to one or more embodiments, the drain area DA may include a doped polysilicon layer. The plurality of sacrificial layers may be replaced by a plurality of gate lines GL and a plurality of conductive pad regions CP.

6 FIG. Although not illustrated in, a plurality of word line cut trenches (not illustrated) may be formed that penetrate the plurality of insulating films IF and the plurality of sacrificial layers to expose the wafer W. The plurality of word line cut trenches (not shown) may be formed to extend lengthwise in the first horizontal direction X and cross the memory cell region MEC and the connection region CON.

According to one or more embodiments, the plurality of sacrificial layers exposed through the plurality of word line cut trenches (not shown) are selectively removed to create a space between each of the plurality of insulating films IF, and then a conductive material is filled in the space to form a plurality of gate stacks GS. According to one or more embodiments, the plurality of gate stacks GS may include a metal, a metal silicide, a doped semiconductor, or combinations thereof. For example, each of the plurality of gate stacks GS may include a metal such as tungsten, nickel, cobalt, tantalum, or the like, a metal silicide such as tungsten silicide, nickel silicide, cobalt silicide, tantalum silicide, or the like, doped polysilicon, or combinations thereof.

1 2 1 3 FIG. According to one or more embodiments, the plurality of gate stacks GS may include the plurality of gate lines GL and the plurality of conductive pad regions CPR integrally connected to the plurality of gate lines GL. According to one or more embodiments, the plurality of conductive pad regions CPR on the connection region CON may form the step-like structure STC. According to one or more embodiments, a portion of the gate stack GS disposed on the memory cell region MEC may form a memory stack MST. For example, the memory stack MST may include, but is not limited to, 48 to 128 gate lines stacked in the vertical direction Z. The plurality of gate lines GL included in the gate stack GS are arranged on the memory cell region MEC and extend in the horizontal direction parallel to the upper surface of the wafer W and may overlap each other in the vertical direction Z. According to one or more embodiments, the plurality of gate lines GL may include the plurality of word lines WL: WL, WL, . . . , WLn-, WLn, the at least one ground select line GSL, and the at least one string select line SSL.illustrates an example in which the plurality of gate lines GL include two ground select lines GSL and two string select lines SSL, but the technical idea of the disclosure is not limited thereto.

After forming an upper insulating film UPIF, a plurality of bit line contact pads BLCP that penetrate the upper insulating film UPIF in the memory cell region MEC and are connected to a plurality of channel structures CS may be formed. The insulating block IB, the middle insulating film MDIF, and the upper insulating film UPIF may form an insulating structure INS. According to one or more embodiments, the plurality of bit line contact pads BLCP may be mutually insulated by the upper insulating film UPIF. The plurality of bit line contact pads BLCP may include metal, metal nitride, or a combination thereof. According to one or more embodiments, each of the upper insulating film UPIF may include an oxide film, a nitride film, or a combination thereof.

1 1 1 FIG. 1 FIG. A metal silicide film MSF may be formed on a surface of the conductive pad region CPR exposed through each of a plurality of first contact holes on the connection region CON, and a contact structure CTS may be formed on the metal silicide film MSF inside each of the plurality of first contact holes. The method Sdescribed with reference tomay be performed before or after forming the contact structure CTS inside each of the plurality of first contact holes. That is, the plurality of first contact holes may correspond to one of the hole areas inspected by the method Sin. The plurality of first contact holes may be defined as region B.

1 1 1 FIG. 1 FIG. For example, the contact structure CTS may include a contact plug CTP extending in the vertical direction Z and in contact with the metal silicide film MSF, and an insulating plug IP surrounding the contact plug CTP. In addition, a peripheral insulating plug PIP and a peripheral contact plug PCP may be sequentially formed within a plurality of second contact holes on the peripheral circuit region PERI to form a peripheral contact structure PTS. The method Sdescribed with reference tomay be performed before or after forming the peripheral contact structure PTS inside each of the plurality of second contact holes. That is, the plurality of second contact holes may correspond to one of the hole areas inspected by the method Sin. The plurality of second contact holes may be defined as region C.

According to one or more embodiments, the insulating plug IP and a peripheral insulating plug CIP may each include a silicon nitride film, a silicon oxide film, or a combination thereof. According to one or more embodiments, the contact plug CTP and the peripheral contact plug PCP may each include tungsten, titanium, tantalum, copper, aluminum, titanium nitride, tantalum nitride, tungsten nitride, or combinations thereof. According to one or more embodiments, the metal silicide film MSF may include WSi, WSiN, WSiO, or combinations thereof. The terms “WSi”, “WSiN”, and “WSiO” used in this specification mean materials composed of the elements included in each term, and are not chemical formulas representing stoichiometric relationships.

In an embodiment, after forming an interlayer insulating film ILIF covering the resultant on the memory cell region MEC, the connection region CON, and the peripheral circuit region PERI, the plurality of bit lines BL, a plurality of wiring layers ML and a plurality of peripheral wiring layers PML penetrating through some portions of the interlayer insulating film ILIF may be formed.

According to one or more embodiments, the drain area DA of each of the plurality of channel structures CS may be connected to a corresponding one of the plurality of bit lines BL through a bit line contact pad BLCP. According to one or more embodiments, the plurality of bit lines BL may be mutually insulated by the interlayer insulating film ILIF. According to one or more embodiments, the plurality of bit lines BL may include metal, metal nitride, or a combination thereof. For example, the plurality of bit lines BL may include tungsten, titanium, tantalum, copper, aluminum, titanium nitride, tantalum nitride, tungsten nitride, or combinations thereof. According to one or more embodiments, the interlayer insulating film ILIF may include an oxide film, a nitride film, or a combination thereof.

According to one or more embodiments, the plurality of wiring layers ML may be formed at the same level as the plurality of bit lines BL arranged on the memory cell region MEC. According to one or more embodiments, each of the plurality of wiring layers ML may be connected to the contact plug CTP of the contact structure CTS. According to one or more embodiments, each of the plurality of wiring layers ML may be configured to be electrically connectable to one conductive pad region CPR selected from among the plurality of conductive pad regions CP via one contact plug CTP selected from among a plurality of contact plugs CTP. According to one or more embodiments, the plurality of wiring layers ML may not include a portion that vertically overlaps the memory stack MST. According to one or more embodiments, the plurality of wiring layers ML on the connection region CON may be insulated from each other by the interlayer insulating film ILIF. According to one or more embodiments, the plurality of wiring layers ML may include tungsten, titanium, tantalum, copper, aluminum, titanium nitride, tantalum nitride, tungsten nitride, or combinations thereof.

According to one or more embodiments, the plurality of peripheral wiring layers PML may extend horizontally at the same level as a level of the plurality of wiring layers ML formed in the connection region CON. According to one or more embodiments, each of the plurality of peripheral wiring layers PML may be connected, via one of a plurality of peripheral contact plugs PCP, to either the peripheral gate PG or the peripheral source/drain area PSD. At least some of the plurality of peripheral wiring layers PML may be configured to be connected to other circuitry or wiring disposed on the peripheral circuit region PERI. The plurality of peripheral wiring layers PML may be mutually insulated by the interlayer insulating film ILIF. According to one or more embodiments, each of the plurality of peripheral wiring layers PML may include tungsten, titanium, tantalum, copper, aluminum, titanium nitride, tantalum nitride, tungsten nitride, or combinations thereof.

1 1 FIG. Hereinafter, a process of performing inspection and measurement on the region A will be described in detail. However, as mentioned above, the method Sofmay be performed not only for the region A, but also for the regions B and C, and may be extended to cases where the semiconductor device is dynamic random-access memory (DRAM).

7 FIG. 6 FIG. 8 FIG. is a enlarged perspective view showing the region A of.is a plan view illustrating a semiconductor device from the perspective of a vertical axis according to an embodiment.

7 8 FIGS.and 1 4 FIGS.to 6 FIG. 7 FIG. are referenced together with. A molding layer MLDL may be formed on the wafer W. The molding layer MLDL may be, but is not limited to, one of a gate stack GS, the step-like structure STC, and the insulating block IB of, and may be configured to surround first contacts, second contacts, or the channel structure CS. That is, in the case of, only the region A among the regions A, B, and C is enlarged, so the molding layer MLDL may correspond to the plurality of gate stacks GS.

The hole area HA may be formed inside the molding layer MLDL. In a vertical view, the cross-section of the hole area HA is depicted as circular, but the shape of the cross-section of the hole area HA is not limited to this and may be elliptical or rectangular. The vertical length of the molding layer MLDL may vary depending on the number of gate stacks deposited. As an embodiment, when a thickness of the ground select line GSL is about 15 nm, a thickness of the insulating film IF is about 25 nm, and the ground select line GSL and the insulating film IF are stacked in 75 layers, a vertical length of the molding layer MLDL may be 3 μm. In an embodiment, a length of each side in the horizontal direction of the molding layer MLDL may be from about 0.5 μm to about 1.5 μm.

221 4 FIG. In an embodiment, the diameter of the hole area HA may be from about 100 nm to about 500 nm. In an embodiment, the diameter of the hole area HA may be within a range of about 100 nm to about 5000 nm, which is the diameter of the area where the tipofcomes into contact with the semiconductor device.

The molding layer MLDL may be a region that forms a periphery of a high aspect ratio contact (HARC) structure having a vertical length that is greater in comparison to a horizontal cross-sectional area. That is, the hole area HA may correspond to a contact area included in the HARC structure.

8 FIG. When viewed along a vertical axis, a plurality of molding layers MLDL may be arranged. The plurality of molding layers MLDL may be in contact with each other. Although each molding layer MLDL is shown as having a hole area HA formed therein, the molding layer MLDL may not have the hole area HA formed therein. The area illustrated inmay correspond to a boundary between semiconductor devices.

9 FIG. is a plan view illustrating a semiconductor device from the perspective of a vertical axis according to an embodiment.

9 FIG. 6 8 FIGS.to 9 FIG. 9 FIG. 1 10 2 10 10 10 1 10 10 10 is referenced together with. A reference measurement region Rof the semiconductor devicelocated on the left side ofmay correspond to a reference region for comparison with a measurement value of the target structure. An actual measurement region Rof the semiconductor devicelocated on the right side ofmay be a measurement region corresponding to the target structure. The semiconductor deviceon the left and the semiconductor deviceon the right may be the same or different from each other. That is, the reference measurement region Rfor measuring the reference signal may perform measurement not only in the semiconductor devicethat includes the actual target structure, but also in another semiconductor devicethat does not include the target structure. In the semiconductor device, a plurality of hole areas HA may be regularly arranged in a planar manner, and the outer surface of each hole area HA may be surrounded by the molding layer MLDL.

1 2 1 2 The reference measurement region Rand the actual measurement region Rmay have the same width in a planar direction. Each of the reference measurement region Rand the actual measurement region Rmay be measured while being physically contacted by a plurality of tips.

10 FIG. is a conceptual diagram illustrating various types of inspection of a semiconductor device according to an embodiment.

10 FIG. 10 FIG. 10 FIG. 10 FIG. Referring to, the wafer W is provided, a semiconductor device may be disposed on an upper surface of the wafer W, and various film materials may be formed on the upper surface of the semiconductor device. In an embodiment, in the left diagram of, the upper surface of the semiconductor device may include a non-metallic material and may have a relatively low absorption coefficient k compared to the upper surface in the right diagram. In an embodiment, in the right diagram of, the upper surface of the semiconductor device may include a metallic material and may have a relatively high absorption coefficient k compared to the upper surface in the left diagram. The absorption k ofmay correspond to a refractive index.

In inspecting a semiconductor stack structure, the measurement may be performed by irradiating light or by irradiating picosecond ultrasonic waves. Additionally, as in the disclosure, the ultrasonic waves for inspection may be generated by the transducer physically contacting the upper surface of the semiconductor device and applying vibration (tip-contact acoustic) to the semiconductor device.

Measurement equipment such as reflectometry and ellipsometry, which utilize light, may obtain information on 3D structural changes inside a stack structure of the semiconductor device because light may sufficiently penetrate the stack structure of the semiconductor device when the upper surface thereof is made of a medium with low absorption coefficient, as shown in the diagram on the left. However, in the case of picosecond ultrasonic, which generates ultrasonic waves by modulating a degree of absorption by applying optical pulse signals, generation of an ultrasonic signal with sufficient intensity may not be successful with a medium with low absorption coefficient.

On the other hand, in the case of the semiconductor device having an upper surface formed of a metallic material with high absorption coefficient, as shown on the right, light may not penetrate downward. Accordingly, it may not be possible to obtain 3D structural information below the upper surface formed of the metallic material. However, in the case of picosecond ultrasonic, since the wavelength is significantly absorbed in a material with a high absorption coefficient, a strong ultrasonic signal may be generated, and inspection of the semiconductor device may be performed using this signal.

In the case of the disclosure, it may be possible to measure 3D structural changes in a lower portion regardless of the material type of the upper layer of the semiconductor device. More specifically, the system for inspecting semiconductor devices according to the disclosure may deliver ultrasonic waves throughout the entire stack regardless of the absorption coefficient of the semiconductor device, by having the transducer substantially contact the upper surface of the semiconductor device.

11 FIG. is a conceptual diagram illustrating the inspection of a semiconductor device using a system for inspecting semiconductor devices according to an embodiment.

11 FIG. 221 221 Referring to, the tip, which is the signal transmission portion, may physically contact the upper surface of the semiconductor device, and the tipand the hole area HA of the semiconductor device may contact each other at a contact point CP. Although the diameter of the contact point CP is illustrated as corresponding to the diameter of the uppermost surface of the hole area HA, the diameter of the contact point CP may be less than that of the hole area HA. The contact point CP may be formed not only on an upper surface of the hole area HA but also on a partial area of an upper surface of the molding layer MLDL.

221 10 10 1 The tipmay physically contact the upper surface of the semiconductor deviceat the hole area HA, and may apply vibration to the semiconductor deviceto generate the pulse SG, which is the first signal. The pulse SGmay descend in the depth direction through the stack structure and reach the upper surface of the wafer W.

1 2 2 2 222 The upper surface of the wafer W may reflect the pulse SGas the first signal and form the echo SGas the second signal. The echo SGmay ascend in the depth direction through the stack structure and reach an upper surface of the hole area HA. The echo SGthat reaches the upper surface of the hole area HA may arrive at the transducer.

12 FIG. 13 FIG. is a plan view showing a bottom surface of a system for inspecting semiconductor devices according to an embodiment.is a conceptual diagram illustrating inspection of a semiconductor device according to an embodiment.

12 13 FIGS.and 12 FIG. 221 221 are referenced together. Referring to, the bottom surface of the system for inspecting semiconductor devices is illustrated, which corresponds to an area in contact with the upper surface of the semiconductor device. The bottom surface of the system for inspecting semiconductor devices may have a plurality of contact points CP regularly arranged in the horizontal direction. The diameter D_CP of the contact point CP may be formed within a range of about 100 nm to about 5000 nm as described above. In conventional light-based metrology used to measure 3D structural profiles of 3D semiconductor devices, there is a limitation in that only averaged 3D structural data of a plurality of units located within several tens of micrometers may be measured due to a limited beam size. Accordingly, the disclosure is configured to measure the 3D structural profiles on a unit-by-unit basis using the tiphaving a smaller contact point CP. The the tipis replaceable depending on the diameter of the hole area HA of the semiconductor device.

13 FIG. 1 2 2 Referring to, the hole area includes a first hole area HAhaving no defects D and a second hole area HAhaving defects D therein. While the pulses and the echo scan the inside of the hole area, information about the defect D may be included in the echo when a defect is present. In the case of the second hole area HA, four defects D may be formed inside the hole area. The number, position, and shape of the formed defect D are not limited to what is shown in the drawing.

1 2 Accordingly, the pulse and echo used to scan the first hole area HAand the second hole area HAmay yield different results.

14 FIG. is a conceptual diagram illustrating another inspection of a semiconductor device according to an embodiment.

14 FIG. 14 FIG. 2 Referring to, in inspecting the defects D of the second hole area HA, the stack-type semiconductor device may be formed by stacking a plurality of layers, that is, a plurality of molding layers MLDL, as shown in, and may then form the 3D structure through etching or other methods. In this case, an abnormality in equipment performing the process on the semiconductor device may independently occur. Therefore, high-resolution ultrasonic waves are required to confirm that the semiconductor devices in the form of the stack are formed with a defect-free profile layer by layer. As the frequency of the vibration signal applied by the tip configured in the transducer increases, a resolution of the generated ultrasonic signal in the depth direction of the semiconductor device may be improved.

In an embodiment, when the frequency is 1 GHz, a peak may be formed over a relatively broad range in the vertical height direction where a defect exists. However, when the frequency exceeds 1 GHz, the peak may be formed in a relatively narrower range limited to the vertical height where the defect actually occurs, as compared to the left-side case. Accordingly, vertical structural defects of the semiconductor device stack may be detected and distinguished by using the transducer capable of vibrating the sample at a frequency of 1 GHz or higher. In an embodiment, the transducer forming the tip of the disclosure may apply physical vibration to the semiconductor device in a frequency range of about 1 GHz to about 50 GHz.

15 FIG. 2 FIG. 16 FIG. 15 FIG. is a detailed flowchart illustrating operations of measuring a target structure inaccording to an embodiment.is a conceptual diagram illustrating an inspection of a semiconductor device according to an embodiment in accordance with the flowchart of.

15 FIG. 400 400 11 400 12 400 11 400 13 400 12 c c c c c c Referring to, operation Sof measuring the target structure of the semiconductor device may include operation_of measuring an error value caused by equipment, operation S_of adjusting a zero point of the measured value in operation S_, and operation S_of re-measuring the specimen after the zero point is adjusted operation S_.

16 FIG. 15 FIG. 400 11 c Referring totogether with, the upper surface of the hole area HA surrounded by the molding layer MLDL is illustrated. In plan view, the measurement may be performed by at least nine or more of the transducers, and accordingly, the number of hole areas HA to be measured may also be nine or more. A drawing shown in box (a) is for explaining steps corresponding to operation S_, which is for measuring error values caused by the equipment. Box (a) illustrates measured results at each vertical level of the semiconductor device stack. In an embodiment, in the top portion within box (a), corresponding measured result values may match the actual areas. In an embodiment, in the middle portion of the stack within box (a), some actual areas and measured result values may not match. More specifically, in the middle portion, dotted lines represent cross-sections of the actual hole areas for the vertical level, and hatched areas surrounded by solid lines represent measured values. Therefore, in the middle portion of the stack within box (a), it may be confirmed that error values caused by the measurement equipment occur in six out of nine hole areas HA. Such error values caused by the measurement equipment may correspond to errors caused by the equipment, not to a defect in the actual semiconductor device.

In an embodiment, in the bottom portion of the stack within box (a), as in the middle portion, measured result values may not match actual areas. More specifically, in the bottom portion, dotted lines may represent cross-sections of the actual hole areas for the vertical level, and hatched areas enclosed by solid lines may represent the measured values. Therefore, in the bottom portion of the stack within box (a), it may be confirmed that error values caused by the measurement equipment occur in six out of nine hole areas HA. Such error values may correspond to equipment-induced errors, not to defects in the actual semiconductor device. The error values occurring in the bottom portion may have a greater absolute value than the error values occurring in the middle portion.

400 11 400 12 c c In operation S_, as described above, magnitudes and directions of error values caused by the equipment, which may result in measurements indicating defects even when no actual defect is present, may be measured. In operation S_, the zero point may be adjusted based on the magnitude and direction of error values caused by the equipment.

400 13 c The diagram shown in box (b) is provided to illustrate operation S_, which involves measuring the specimen after the zero point is adjusted. Box (b) shows measured values for each vertical level of the semiconductor device stack. Therefore, unlike the measurement results for each vertical level of the semiconductor device stack in box (a), error values observed in box (b) may correspond to actual defects in the semiconductor device.

In an embodiment, in the top portion of box (b), measured result values may match actual areas. In an embodiment, in the middle portion of the stack in box (b), dotted lines may indicate cross-sections corresponding to good hole areas or zero-adjusted values for the vertical level, and hatched areas enclosed by solid lines may represent measured values. Therefore, in the middle portion of the stack within box (b), it may be confirmed that actual defects occur in two out of nine hole areas HA of the semiconductor device stack. That is, compared to the area corresponding to a good hole, the cross-section may be shifted toward the upper left and may have a smaller diameter.

In an embodiment, in the bottom portion of the stack within box (b), as in the middle portion, dotted lines may indicate cross-sections corresponding to good hole areas or zero-adjusted values for the vertical level, and hatched areas enclosed by solid lines may represent the measured values. Therefore, in the bottom portion of the stack within box (b), it may be confirmed that actual defects occur in two out of nine hole areas HA of the semiconductor device stack. That is, compared to the area corresponding to a good hole, the cross-section may be shifted toward the upper left and may have a smaller diameter. Therefore, by integrating the measured values for each vertical level in box (b), inspection results for the internal structure or defects of the target semiconductor device may be derived.

In summary, when semiconductor fabrication processes are performed on the stack of a semiconductor device, an etching technique that forms hole areas by drilling them at once may be essential. In this case, the processes may need to proceed such that the processed stack units have identical profiles in order to be considered good quality. To verify whether the process was properly performed, 3D structure profiles of adjacent individual units may need to be compared. Therefore, the profiles for at least nine unit structures may be scanned using ultrasonic signals, and the results may be visualized. By obtaining multiple scanned ultrasonic signals, equipment-induced influences may be removed, enabling more accurate measurement of relative positional non-uniformities at specific heights of the individual units after zero-point adjustment.

17 FIG. 2 FIG. 18 FIG. 17 FIG. is another detailed flowchart illustrating operations of measuring the target structure inaccording to an embodiment.is a conceptual diagram illustrating the inspection of a semiconductor device according to an embodiment in accordance with the flowchart of.

17 FIG. 400 400 21 400 22 400 21 400 23 400 24 c c c c c c Referring to, operation Sfor measuring the target structure of the semiconductor device may include operation S_of setting a range of vibration frequencies of the transducer, operation S_of applying vibration to the semiconductor device by using the transducer while varying the frequency within the range set in operation S_, operation S_of searching for a first resonance frequency at which resonance first occurs within the frequency range as the transducer applies the vibration to the semiconductor device, selecting the first resonance frequency, and performing the measurement, and operation S_of searching for a second resonance frequency at which a resonance next occurs within the frequency range, selecting the second resonance frequency, and performing the measurement.

18 FIG. 18 FIG. 0 1 2 2 1 1 1 1 0 2 0 Referring to, on the left side, the stack-type semiconductor device includes the plurality of molding layers MLDL is shown on the upper surface of the wafer W. That is, the semiconductor device may include at least one layer, and the hole area HA formed inside the semiconductor device may have a tapered shape in which the cross-sectional area in the horizontal direction gradually decreases along the vertical direction, and the tapered shape may be discontinuous at a certain vertical level. In an embodiment, the semiconductor device shown inmay include a ground layer LV_F, a first layer LV_F, and a second layer LV_F as a topmost layer. From LV_F to LV_F, an inner surface of the hole area HA may have a continuously tapered shape. However, starting from LV_F, a horizontal area of the hole area HA may be formed discontinuously. More specifically, the horizontal area of the hole area HA may increase discontinuously from LV_F. In addition, from LV_F to LV_F, the side surfaces of the hole area HA may again have a continuously tapered shape. In summary, the inner surface of the hole area HA from LV_F to LV_F may not be conformal.

18 FIG. In, the graph shown to the right of the semiconductor device represents the horizontal direction on the X-axis and the depth direction of the semiconductor device on the Y-axis, where each circle in the graph represents a cross-section of the hole area at each vertical level. That is, a total of 25 data are shown for each of the five horizontal hole areas, which are cross sections of the five vertical hole areas.

2 2 1 2 1 1 1 0 1 0 0 0 2 1 1 0 0 Five cross-sections HA_S_F of hole areas corresponding to the uppermost vertical level LV_F, the second layer, are shown. Five cross-sections HA_S_F_a of hole areas corresponding to the vertical level between LV_F and LV_F are shown. Five cross-sections HA_S_F_b of hole areas corresponding to the vertical level of LV_F are shown. Five cross-sections HA_S_F_a of hole areas corresponding to the vertical level between LV_F and LV_F are shown. Finally, five cross-sections HA_S_F of hole areas corresponding to the bottom ground layer LV_F are shown. Diameters of the hole area cross-sections corresponding to each layer may differ from one another. In an embodiment, the diameter of HA_S_F may be greater than that of HA_S_F_a. In an embodiment, the diameter of HA_S_F may be greater than the diameters of HA_S_F_a and HA_S_F.

1 1 In the case of HA_S_F, it may correspond to a vertical level where periodicity of the repeated structure is broken, and it may be located at a horizontal position different from that of other hole area cross-sections. Alternatively, HA_S_F may be located at the same horizontal position as other hole area cross-sections, but the variation in cross-sectional diameter with respect to the vertical level may differ.

400 23 400 24 1 2 1 1 1 0 2 1 2 300 c c 4 FIG. In the case of the stack of the semiconductor device in which a plurality of layers are vertically stacked, the units having identical 3D profiles may be arranged repeatedly in the planar direction. Even when the transducer with a small contact area is used, signals may be modulated due to interactions between the ultrasonic waves generated by the transducer and the individual units located around the target to be measured. In such a case, when the frequency of the mechanically vibrating tip of the transducer is similar to the periodicity of the repeated units, a resonance phenomenon may occur. That is, the resonance frequencies described in operations S_and S_may occur. Therefore, when the ultrasonic waves are generated at the frequency at which a resonance phenomenon occurs with the repeated structure at a specific height, while varying the frequency within the set frequency range, the ultrasonic signal may significantly change near the area of an individual unit where the periodicity of the structure is broken. In the disclosure, the area where the periodicity is broken may correspond to an area near LV_F. In an embodiment, a resonance phenomenon may occur between LV_F and LV_F by a first resonance frequency f_. In an embodiment, a resonance phenomenon may occur between LV_F and LV_F by a second resonance frequency f_. The first resonance frequency f_and the second resonance frequency f_may have different magnitudes. That is, when the periodicity of the individual units or the diameter of hole area cross-sections differs between the upper and lower parts, the resonance frequency may be configured differently for the individual units in each layer where such a periodicity mismatch occurs in the depth direction. Accordingly, based on the difference between the resonance frequencies, the aperiodicity of the individual units may be extracted. In other words, the signal processing unitofmay extract the horizontal structure according to the vertical position of the semiconductor device, based on measurement values obtained from each of the first resonance frequency and the second resonance frequency. The intensity of ultrasonic waves may be progressively reduced in the downward vertical direction. In the disclosure, the intensity of ultrasonic waves may correspond to the magnitude of the amplitude of the ultrasonic waves.

19 FIG. 20 FIG. 2 FIG. 21 FIG. 20 FIG. is a graph showing decibel values over time during an inspection of a semiconductor device according to an embodiment.is another detailed flowchart illustrating operations of measuring the target structure inaccording to an embodiment.is a conceptual diagram illustrating an inspection of a semiconductor device according to the flowchart ofaccording to an embodiment.

19 21 FIGS.to 21 FIG. 400 400 31 400 32 400 31 400 33 400 34 400 33 3 c c c c c c c are referenced together. Operation Sfor measuring the target structure of the semiconductor device may include operation S_of setting a range of vibration frequencies of the transducer, operation S_of applying vibration to the semiconductor device by using the transducer while varying the frequency within the range set in operation S_, operation S_of searching for a frequency at which no resonance occurs within the frequency range as the transducer applies the vibration to the semiconductor device, selecting a non-resonant frequency, and operation S_of performing the measurement with the non-resonant frequency. The frequency selected in the S_operation may be f_of.

19 FIG. 2 1 1 0 Referring to, data without resonance and data with resonance are shown. When viewing the data after 0 nanoseconds from the start of measurement, it may be seen that signals with greater amplitude are detected in the space between the second layer and the first layer, that is, from LV_F to LV_F, in the case without resonance compared to the case with resonance. It may also be seen that in the space between the first layer and the ground layer, that is, from LV_F to LV_F, a signal with a greater amplitude is detected in the case without resonance compared to the case with resonance.

18 FIG. 19 21 FIGS.to 4 FIG. 300 In a semiconductor device including a plurality of layers with a high stack structure, it may be necessary to precisely measure the depth of a hole area, such as the value of total recess, the total thickness of the stack, and the extent to which the hole is formed in the layers of the stack. However, due to the planar shape of a unit at a given depth and the influence of signals from surrounding units, the generated ultrasonic signal may be distorted in terms of depth information. That is, as observed in, as it goes deeper in the vertical direction, which is the depth direction, the amplitude of the ultrasonic signal may become weaker, and as a result, distortion in the depth information of the hole area may further occur. Therefore, as described in, a frequency insensitive to structural changes of each layer in the depth direction may be selected. In the disclosure, the insensitive frequency may correspond to a frequency at which no resonance occurs. Based on structural information of layers in the depth direction, the frequency at which resonance does not occur due to a planar repetitive structure of the stack of the semiconductor device may be selected. Based on measurement values obtained at the non-resonant frequency by the signal processing unitof, a vertical structure according to a horizontal position may be extracted.

18 FIG. 21 FIG. 2 1 Compared with, the intensity of ultrasonic wave inmay be reduced at each different vertical level. In other words, the intensity of ultrasonic waves may be primarily attenuated at LV_F and may be secondarily attenuated at LV_F.

22 FIG. is a graph showing decibel values over time during an inspection of a semiconductor device according to an embodiment.

22 FIG. 221 1 2 3 Referring to, data measured by different tips are shown. The tipmay be configured to be replaceable. A plurality of tips may differ in size, arrangement, spacing, and constituent materials. The plurality of tips may be sequentially applied to a single semiconductor device to select a tip suitable for measurement. Sensitivity to the ultrasonic signal may vary depending on a shape of the tip contacting the individual unit. Accordingly, in the disclosure, grouping of the tips may be first performed based on 3D shape information of the structure of a semiconductor device to be measured, as described above. Subsequently, by selecting a tip corresponding to a target layer from the grouped tips, changes in a 3D profile of the target structure may be measured with high sensitivity. In an embodiment, measurement information obtained by a first tip Tip, a second tip Tip, and a third tip Tipis examined.

2 1 1 0 3 In a region between the second layer and the first layer, that is, in a space from LV_F to LV_F, and in a region between the first layer and the ground layer, that is, in a space from LV_F to LV_F, it may be observed that the signal of the third tip Tiphas a greater amplitude than signals from the other tips. Therefore, in an embodiment, the third tip may be selected and measurement may be repeatedly performed.

23 FIG. 2 FIG. 24 FIG. 23 FIG. is another detailed flowchart illustrating the measuring of the target structure inaccording to an embodiment.is a conceptual diagram illustrating an inspection of a semiconductor device according to an embodiment in accordance with the flowchart of.

23 24 FIGS.and 24 FIG. 24 FIG. 400 400 41 400 42 400 43 400 44 400 43 1 2 400 41 400 42 c c c c c c c c Referring to, the operation Sof measuring the target structure of a semiconductor device may include operation S_of securing a database of pulse trains including multiple pulses, operation S_of measuring the pulse train for a specimen, operation S_of selecting at least one filter corresponding to the specimen from the database, and operation S_of applying the filter selected in operation S_and removing noise. In the disclosure, the ultrasonic signal may include multiple pulses, such as a first pulse Pand a second pulse P, as shown in. The multiple pulses may form the pulse train PT. After obtaining a database of the pulse trains in operation S_, a measurement with the pulse train may be performed to the structure through operation S_as shown in.

400 43 1 2 c 24 FIG. At least one filter selected in operation S_may correspond to a first filter FTRand a second filter FTRof. The number of filters may correspond to the number of pulses included in the pulse train.

400 44 1 1 2 2 1 1 1 2 2 2 c Through operation S_, noise may be removed by applying the first filter FTRto the first pulse Pand by applying the second filter FTRto the second pulse P. By applying the first filter FTRto the first pulse P, a first result value Resultfrom which noise has been removed may be obtained. In addition, by applying the second filter FTRto the second pulse P, a second result value Resultfrom which noise has been removed may be obtained.

25 FIG. is a diagram schematically illustrating an electronic system including a semiconductor device according to an embodiment.

25 FIG. 1000 1100 1200 1100 1000 1100 Referring to, an electronic systemmay include one or more memory devicesand a memory controllerelectrically connected to the one or more memory devices. The electronic systemmay be, for example, a solid state drive (SSD) device, a universal serial bus (USB), a computing system, a medical device, or a communication device including at the one or more memory devices.

1100 1100 10 1100 1100 1100 1100 1100 1110 1120 1130 6 FIG. The memory devicemay be an integrated circuit device including a nonvolatile memory device. For example, the memory devicemay include the semiconductor devicedescribed with reference to. The memory devicemay include a first structureF and a second structureS on the first structureF. The first structureF may be a peripheral circuit structure. The peripheral circuit may include a row decoder, a page buffer, and a logic circuit.

1100 1100 1 2 1 2 The second structureS may be a cell array structure. The second structureS may include the plurality of bit lines BL, a common source line CSL, the plurality of word lines WL, a plurality of first and second string select lines ULand UL, first and second ground select lines LLand LL, and a plurality of memory cell strings CSTR between the plurality of bit lines BL and the common source line CSL. Gate electrodes and channel structures may form the plurality of memory cell strings CSTR.

1100 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 In the second structureS, each of the plurality of memory cell strings CSTR may include ground select transistors LTand LTadjacent to the common source line CSL, string select transistors UTand UTadjacent to the bit line BL, and a plurality of memory cell transistors MCT disposed between the ground select transistors LTand LTand the string select transistors UTand UT. The numbers of ground select transistors LTand LTand the string select transistors UTand UTmay vary depending on one or more embodiments. One of the plurality of channel structures and one of the plurality of gate electrodes may form one of the plurality of transistors LT, LT, UT, UT, and MCT.

1 2 1 2 1 2 1 2 In one or more embodiments, a plurality of ground select lines LLand LLmay each be connected to gate electrodes of ground select transistors LTand LT. A word line WL may be connected to a gate electrode of a memory cell transistor MCT. Each of the plurality of string select lines ULand ULmay be connected to gate electrodes of string select transistors UTand UT.

1 2 1 2 1110 1120 A common source line CSL, the plurality of ground select lines LLand LL, the plurality of word lines WL, and the plurality of string select lines ULand ULmay be connected to the row decoder. The plurality of bit lines BL may be electrically connected to the page buffer.

1100 1200 1101 1130 1101 1130 The memory devicemay communicate with a memory controllerthrough an external connection padelectrically connected to a logic circuit. The external connection padmay be electrically connected to the logic circuit.

1200 1210 1220 1230 1000 1100 1200 1100 The memory controllermay include a processor, a Not AND (NAND) controller, and a host interface. In some one or more embodiments, the electronic systemmay include a plurality of memory devices, and in this case, the memory controllermay control the plurality of memory devices.

1210 1000 1200 1210 1100 1220 1220 1221 1100 1221 1100 1100 1100 1230 1000 1230 1210 1100 The processormay control overall operations of the electronic systemincluding the memory controller. The processormay operate according to predetermined firmware and may access the memory deviceby controlling the NAND controller. The NAND controllermay include a NAND interfacefor processing communication with the memory device. Through the NAND interface, control commands for controlling the memory device, data to be written to the plurality of memory cell transistors MCT of the memory device, and data to be read from the plurality of memory cell transistors MCT of the memory devicemay be transmitted. The host interfacemay provide a communication function between the electronic systemand an external host. When a control command is received from the external host through the host interface, the processormay control the memory devicein response to the control command.

26 FIG. is a perspective view illustrating an electronic system including a semiconductor device according to an embodiment.

26 FIG. 2000 2001 2002 2001 2003 2004 2003 2004 2002 2005 2001 Referring to, an electronic systemaccording to an embodiment may include a main board, a memory controllermounted on the main board, one or more semiconductor packages, and a DRAM. The semiconductor packageand the DRAMmay be interconnected with the memory controllervia multiple wiring patternsformed on the main board.

2001 2006 2006 2000 2000 2000 2006 2000 2002 2003 The main boardmay include a connectorhaving a plurality of pins coupled to the external host. The number and arrangement of the multiple pins in the connectormay vary depending on a communication interface between the electronic systemand the external host. In one or more embodiments, the electronic systemmay communicate with an external host according to any one of the interfaces such as USB, peripheral component interconnect (PCI) Express, serial advanced technology attachment (SATA), or M-Phy for universal flash storage (UFS). In one or more embodiments, the electronic systemmay operate by power supplied from the external host through the connector. The electronic systemmay further include a power management integrated circuit (PMIC) for distributing power supplied from the external host to the memory controllerand the semiconductor package.

2002 2003 2003 2000 The memory controllermay write data to the semiconductor packageor read data from the semiconductor package, and may improve an operating speed of the electronic system.

2004 2003 2004 2000 2003 2000 2004 2002 2004 2003 The DRAMmay be a buffer memory for alleviating a speed difference between the data storage space of the semiconductor packageand the external host. The DRAMincluded in the electronic systemmay operate as a kind of cache memory and may provide a space for temporarily storing data during control operations for the semiconductor package. When the electronic systemincludes the DRAM, the memory controllermay further include a DRAM controller for controlling the DRAMin addition to the NAND controller for controlling the semiconductor package.

2003 2003 2003 2003 2003 2200 2003 2003 2100 2200 2100 2300 2200 2400 2200 2100 2500 2200 2400 2100 a b a b a b The semiconductor packagemay include a first semiconductor packageand a second semiconductor packagespaced apart from each other. Each of the first and second semiconductor packagesandmay be the semiconductor package including a plurality of semiconductor chips. Each of the first and second semiconductor packagesandmay include a package substrate, the plurality of semiconductor chipson the package substrate, an adhesive layerdisposed on a lower surface of each of the plurality of semiconductor chips, connection structureselectrically connecting the plurality of semiconductor chipsto the package substrate, and a molding layercovering the plurality of semiconductor chipsand the connection structureson the package substrate.

2100 2130 2200 2210 2200 10 6 FIG. The package substratemay be a printed circuit board including a plurality of package upper pads. Each of the plurality of semiconductor chipsmay include an input/output pad. Each of the plurality of semiconductor chipsmay include the semiconductor devicedescribed with reference to.

2400 2210 2130 2003 2003 2200 2130 2100 2003 2003 2200 2400 a b a b In one or more embodiments, the connection structuremay be bonding wire electrically connecting the input/output padand the package upper pad. Thus, in the first and second semiconductor packagesand, the plurality of semiconductor chipsmay be electrically connected to each other in a wire-bonding manner and may be electrically connected to the package upper padsof the package substrate. In one or more embodiments, in the first and second semiconductor packagesand, the plurality of semiconductor chipsmay be electrically connected to each other by a connection structure including a plurality of through silicon vias (TSVs) instead of the bonding wire connection structure.

2002 2200 2002 2200 2001 In one or more embodiments, the memory controllerand the plurality of semiconductor chipsmay be included in a single package. In an embodiment, the memory controllerand the plurality of semiconductor chipsmay be mounted on an interposer substrate separate from the main board, and may be connected to each other through wiring formed on the interposer substrate.

27 FIG. is a cross-sectional view illustrating a semiconductor package including a semiconductor device according to an embodiment.

27 FIG. 26 FIG. 26 FIG. 26 FIG. 26 FIG. 6 FIG. 2003 2100 2100 2120 2130 2120 2125 2120 2135 2130 2125 2120 2130 2400 2125 2005 2001 2000 2800 2200 10 Referring to, in the semiconductor package, the package substratemay be the printed circuit board. The package substratemay include a package substrate body, the plurality of package upper pads(see) disposed on an upper surface of the package substrate body, a plurality of lower padsdisposed on or exposed through a lower surface of the package substrate body, and a plurality of internal wiringselectrically connecting the plurality of package upper pads(see) and the plurality of lower padsinside the package substrate body. As shown in, the plurality of package upper padsmay be electrically connected to a plurality of connection structures. The plurality of lower padsmay be connected to a plurality of multiple wiring patternson a main boardof the electronic systemshown inthrough a plurality of conductive bumps. Each of the plurality of semiconductor chipsmay include the semiconductor devicedescribed with reference to.

28 FIG. is a schematic block diagram of a shape profile measuring system according to an embodiment.

28 FIG. 28 FIG. 4 FIG. 40 41 42 43 44 45 40 1 40 40 40 45 Referring to, a shape profile measuring systemmay include a measuring unit, a communication unit, an operation processing unit, a memory, and a bus. The shape profile measuring systemofmay correspond to the systemfor inspection the semiconductor device of. However, the components included in the shape profile measuring systemare not necessarily limited to those listed above, and the shape profile measuring systemmay variously include components for measuring a shape profile. Each component of the shape profile measuring systemmay communicate with one another through the bus.

41 41 41 41 The measuring unitmay measure the semiconductor device as a measurement target including structural patterns. For example, the measuring unitmay include a device that measures the semiconductor device as a measurement target MT based on an interference signal generated by reflection from the measurement target MT. For example, the measuring unitmay include a signal generator that generates and emits an ultrasonic signal in a wavelength band having high transmittance for the semiconductor device as the measurement target. For example, the measuring unitmay generate an ultrasonic signal having a vibration frequency of about 1 GHz to about 5 GHz.

42 40 40 The communication unitmay provide network communication to the shape profile measuring system. The network may be a wired and/or wireless network such as radio, cellular, satellite, or broadcasting. In an embodiment, the shape profile measuring systemmay be an electronic device installed with an image processing program such as a computer, a smartphone, a personal computer, or a server.

43 41 43 The operation processing unitmay perform operations on data obtained by the measuring unit. The operation processing unitmay measure optical path lengths based on the interference signals.

43 41 43 In some one or more embodiments, the operation processing unitmay perform operations on two-dimensional (2D) images obtained by the measuring unit. The operation processing unitmay measure a planar position of a hole H.

43 For example, the operation processing unitmay include a CPU, a graphics processing unit (GPU), a vector processor, a quantum processing unit, or an embedded processing unit.

44 43 44 41 44 The memorymay store data processed by the operation processing unit. The memorymay store data obtained by the measuring unit. For example, the memorymay include a flash memory, a hard disk drive (HDD), a SSD, a DRAM, or a static random-access memory (SRAM).

29 FIG. is a flowchart illustrating a method of manufacturing a semiconductor device including a method of measuring a shape profile according to an embodiment.

29 FIG. 10 Referring to, the wafer W may first be prepared (operation S). The wafer W may include, for example, a wafer on which one or more semiconductor processes have been performed or a bare wafer on which no semiconductor process has been performed.

20 Thereafter, a semiconductor process may be performed on the wafer W (operation S). An oxidation process, a photolithography process, a deposition process, an etching process, an ion implantation process, and/or a cleaning process may be performed on the wafer W. The patterns may be formed on the wafer by semiconductor processes performed thereon. In some one or more embodiments, at least a portion of the wafer W may be removed in the vertical direction (Z direction) to form a pattern extending in the vertical direction (Z direction). In another embodiment, after forming the plurality of layers on the wafer W, at least a portion of the plurality of layers may be removed in the vertical direction (Z direction) to form a pattern extending in the vertical direction (Z direction).

30 30 1 1 FIG. Thereafter, a shape profile inspection may be performed (operation S). The operation of inspecting the shape profile (operation S) may correspond to operation Sof.

40 Thereafter, a subsequent semiconductor process may be performed on the wafer W (operation S). The subsequent semiconductor process on the wafer W may include various processes. For example, the subsequent semiconductor process may include an oxidation process, a photolithography process, a deposition process, an etching process, an ion implantation process, and/or a cleaning process. In addition, the subsequent semiconductor process may include a singulation process for separating the wafer W into individual semiconductor chips, a testing process for testing the semiconductor chips, and a packaging process for packaging the semiconductor chips. A semiconductor device may be completed through the subsequent semiconductor process on the wafer W.

While the disclosure has been particularly shown and described with reference to one or more embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the following claims.