Driving High-Capacity Storage Device Performance Using Capacitors

A storage device may be communicatively coupled to a host and to non-volatile memory including, for example, a NAND flash memory device on which the storage device may store data received from the host. The memory device may include multiple dies which may be divided into physical blocks and the storage device may store data in pages on blocks on the memory device. Data may be stored in the blocks in various formats, with the formats being defined by the number of bits that may be stored per memory cell. For example, a single-level cell (SLC) format may write one bit per memory cell, a multi-level cell (MLC) format may write two bits per memory cell, a triple-level cell (TLC) format may write three bits per memory cell, a quadruple-level cell (QLC) format may write four bits per memory cell, and so on. A format used to store fewer bits per memory cell may be accessed faster than a format used to store more bits per memory cell.

As the capacity of the storage device increases, the number of dies on the storage device may also increase such that the power to the storage device provided by the host may be insufficient to write to all the dies at the same time. When the storage device includes more dies than can be powered under a maximum power limit of host supplied power, a multi meta-die approach may be used wherein a limited number of dies may be operated on in parallel, thereby reducing the peak power consumed at any instant in time. For example, if a system includes sixty-four dies that may be operated in parallel, but because of the host power constraint the system may only support sixteen active dies, sixteen dies may be included in a meta-die. Each meta-die may be an independent unit. In this example, the system may include four meta-dies, one of which may be active at a time.

A controller on the storage device may extend the life of the device by distributing writes evenly across the meta-dies. A meta block on a meta-die may be formed in an interleaved manner, wherein the meta block may include a block from each die in the meta-die. When the controller programs data to a meta block on a first meta-die, at the end of the meta block on the first meta-die, the controller may begin an erase operation on a meta-block on a second meta-die in order to write data on the meta block in the second meta-die. The erase operation may occur in the foreground and the block erase-overheads may cause performance on the storage device to drop. Although the impact of a block erase operation may be present in sustained write operations, the impact of the block erase operation may be significant during burst write operations when the storage device is accessing, for example, a SLC meta-block at a fast rate. To place the erase-overheads in the background such that the erase-overheads may not affect host operations, a pre-erase feature may be used, wherein a certain number of blocks that may be required for benchmarks may be kept in an erase state on a newly installed storage device. The pre-erase feature only allows for high burst writes on a newly installed storage device, and as such, it is a onetime use feature that may have limited practical use. As the capacity of the storage device increases and the burst range increases, having an increased number of SLC/hybrid blocks in pre-erase state might not be possible

When the storage device performs host write operations, the storage device may also perform control write operations wherein the storage device may write control data such as logical-to-physical data to a global address table (GAT). When buffers used to store GAT deltas are full, eviction from the buffers may be triggered. The storage device may wait for GAT delta page write operation to complete before resuming host write operations, possibly stalling host operations and causing performance on the storage device to drop. In some cases, to prevent program and read failures, the storage device may perform exclusive OR (XOR) writes after host write operations. If the dies are busy with, for example, TLC writes and XOR writes are to be performed on, for example, a SLC block, the XOR write must wait for TLC write to complete. Hence, the XOR buffers may not be ready to accommodate more parity and may pause the host write operations until the XOR write is complete, possibly stalling the host operations and causing performance drop on the storage device. A multi-meta-die storage device may have idle dies to perform control write and/or XOR write operations while host write operations are being performed in other dies. However, because of power constraints, the idle dies may not be used.

In some implementations, a storage device may use power from a capacitor to increase performance on the storage device. The storage device includes a memory device including multiple meta-dies. Each of the meta-dies may include a set of dies. One meta-die may be used for host operations at a time and is supplied host power and the other meta-dies are not supplied host power. The storage device also includes a capacitor to provide backup power to complete an ongoing operation during loss of host power on the storage device. A controller may use host power to perform a host burst write operation on a first subset of dies in a first meta-die. The controller may use power reserved by the capacitor for a subset of dies in the second meta-die. The controller may use the capacitor power to execute an erase operation on dies in the second meta-die without requesting more power from host, wherein the controller executes the erase operation in parallel with the host burst write operation on the first meta-die,

In some implementations, a storage device may use power from a capacitor to increase performance on the storage device. The storage device includes a memory device including multiple meta-dies. Each of the meta-dies may include a set of dies. One meta-die may be used for host operations at a time and is supplied host power and the other meta-dies are not supplied host power. The storage device also includes a capacitor to provide backup power to complete an ongoing operation during loss of host power on the storage device. A controller may use host power to perform a host burst write operation on a first subset of dies in a first meta-die. The controller may use power reserved by the capacitor for a subset of dies in the second meta-die. The controller may use the capacitor power to execute a control write operation on the die in the second meta-die in parallel with the host burst write operation on a die in the first meta-die.

In some implementations, a method is provided on the storage device for increasing performance on the storage device by using power from a capacitor on the storage device. The method includes providing backup power to a capacitor to complete an ongoing operation during loss of host power on the storage device. The method also includes performing a host burst write operation, using host power, on a first subset of dies in first meta-die and using power reserved by the capacitor for a second subset of dies in the second meta-die. The method further includes executing an erase operation, using capacitor power, on dies in the second meta-die in parallel with the host burst write operation on the first meta-die.

Skilled artisans will appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help to improve understanding of implementations of the present disclosure.

The apparatus and method components have been represented where appropriate by conventional symbols in the drawings, showing those specific details that are pertinent to understanding the implementations of the present disclosure so as not to obscure the disclosure with details that will be readily apparent to those of ordinary skill in the art.

The following detailed description of example implementations refers to the accompanying drawings. The same reference numbers in different drawings may identify the same or similar elements.

1 FIG. 100 102 104 102 104 104 104 104 102 102 is a schematic block diagram of an example system in accordance with some implementations. Systemmay include a hostand a storage devicethat may be in the same physical location as components on a single computing device or on different computing devices that are communicatively coupled. Hostmay provide operational power for storage deviceand notify storage deviceabout the maximum/peak host power to be used by storage device. Storage devicemay communicate with hostvia a Non-Volatile Memory Express (NVMe) protocol over a peripheral component interconnect express (PCIe) bus, and the like. Hostmay include additional components (not shown in this figure for the sake of simplicity).

104 108 110 110 110 108 106 106 106 102 106 112 114 116 116 110 a n a b a b a n Storage devicemay be, for example, a solid-state drive (SSD) that may include a controllerand one or more storage components such as non-volatile memory devices-(referred to herein as the memory device(s)). Controllerthat may include a front-end moduleand a backend module. Front-end modulemay include a host interface module and other components that may be used to interface with host. Backend modulemay include a flash translation layer (FTL), a high-level data path (HLDP), and lower-level data paths (LLDP)-that may be used to interface with memory device.

108 102 102 108 110 102 108 110 108 110 110 Controllersmay interface with hostand process foreground operations including instructions transmitted from host. For example, controllersmay read data from and/or write to memory devicesbased on instructions received from host. Controllersmay also execute background operations to manage resources on memory device. For example, controllersmay monitor memory devicesand may execute garbage collection and other relocation functions per internal relocation algorithms to refresh, recycle, and/or relocate the data on memory devices.

110 110 110 110 0 0 100 100 100 Memory devicesmay be flash based. For example, memory devicesmay be a NAND or NOR flash memory that may be used for storing host and control data over the operational life of memory devices. Memory devicesmay include one or more meta-dies (for example, meta-die-meta-die N) connected to a memory bus including data lines and chip enable lines. A meta-die may include a number of dies (for example, dies-N) that may be operated on in parallel. For example, if systemincludes sixty-four dies that may be used in parallel, but because of host power constraint, systemmay only support sixteen active dies, sixteen dies may be included in a meta-die. As such, systemmay include four meta-dies.

104 108 108 110 104 104 A meta block may be formed in an interleaved manner, wherein the meta block may include a block from each die in the meta-die. Data may be stored in the meta-blocks in various formats, with the formats being defined by the number of bits that may be stored per memory cell. For example, a single-level cell (SLC) format may write one bit per memory cell, a multi-level cell (MLC) format may write two bits per memory cell, a triple-level cell (TLC) format may write three bits per memory cell, a quadruple-level cell (QLC) format may write four bits per memory cell, and so on. A format used to store fewer bits per memory cell may be accessed faster than a format used to store more bits per memory cell. As such, during peak performance when storage deviceis performing a burst write operation, controllermay write data to SLC blocks. During normal/sustained write operations on storage device, controllermay write data to blocks that may store more bits per cell than SLC blocks including, for example, TLC blocks. Memory devicemay be included in storage deviceor may be otherwise communicatively coupled to storage device.

102 104 104 104 104 104 104 0 Hostmay restrict the amount of host power consumed by storage deviceat a given time. For example, in some protocols, the maximum amount of host power that may be consumed by storage deviceat a given time may be 7.5 watts (W). With such power restriction when the capacity of storage deviceincrease such that storage devicesupports multiple meta-dies, only one meta-die may be active at a given time. As such, using the example where storage deviceincludes four meta-dies, when storage deviceis programming, for example, meta-die, the other meta-dies may be placed on an inactive state and may not be supplied host power.

104 104 0 0 104 102 104 118 104 118 106 0 104 b While storage deviceis writing to a meta-die, an ungraceful shutdown event may occur. For example, storage devicemay lose host power while it is writing data to meta-die. To ensure that the data being written to meta-dieis not lost during an ungraceful shutdown when storage deviceis no longer receiving power from host, storage devicemay also include a capacitor bankwith one or more capacitors that may provide backup power for storage deviceto complete an ongoing operation and avoid a write-abort scenario, wherein write operations may be aborted because of power loss. As such, capacitor bankmay provide backup power to hardware components in a write path including hardware components in backend moduleand meta-die(i.e., the meta-die on which data is being written) when there is an ungraceful shutdown on storage device. The other meta-dies that were not being supplied host power when the ungraceful shutdown occurred may continue to remain in an inactive state (i.e., in a state without power).

104 118 104 102 104 118 102 118 104 108 108 Storage devicemay also use capacitor bankas a power booster while storage deviceis receiving power from host. For example, storage devicemay charge capacitor bankwith power supplied by host. In an example where a meta-die includes sixteen dies, capacitor bankmay be charged with 16-die worth of backup power to carry out a sustained write on all active dies in the meta-die during an ungraceful shutdown (i.e., to write to TLC blocks on the meta-die blocks to complete an ongoing write operation when storage deviceloses host power). Due to the higher die throughput during a burst write, controllermay perform burst writes on a first subset of dies in an active meta-die. During the burst operation, the host power that may be supplied to a second subset of dies (i.e., dies that are not in the first subset of dies in the active meta-die) may not be used for the burst write. With a sixteen die meta-die configuration where a target a burst write may be two gigabytes (GB) per second and a die has a SLC program time of 100 microseconds (μs), controllermay perform burst writes with only four dies operating at a time, due to the higher die throughput of approximately 640 megabits (MBps). As such, during a burst operation, the host power that may be supplied to the other twelve dies in the active meta-die may not be used for the burst write.

118 108 118 102 102 0 104 0 104 0 118 108 118 1 102 When the capacitors in capacitor bankare charged, controllermay use capacitor bankto power up inactive/dormant dies without drawing more power from host. For example, if the power being supplied by hostis sufficient to write to meta-diebut is insufficient to supply power to other meta-dies, while controlleris performing a burst write on the first subset of dies in meta-die, storage devicemay draw power reserved for the second subset of dies in meta-diefrom capacitor bank. Controllermay use the power drawn from capacitor bankto power up inactive/dormant dies (i.e., inactive dies on one or more of the meta-dies-N,), without drawing extra power from host.

104 108 108 102 108 108 0 1 3 0 104 0 1 108 0 To extend the life of the dies on storage device, controllermay implement wear-leveling, wherein controllermay distribute writes evenly across the dies/meta-dies. For example, if hostissues a write command with 4 GB of data and controllermay write 1 GB to a meta block, controllermay write the first GB to a meta block in meta-die, the second GB to a meta block in meta-die, the third GB to a meta block in meta-die 2, and the fourth GB to a meta block in meta-die. While controller is writing the first GB to the meta-block in meta-die, storage devicemay supply host power to meta-dieand may not supply host power to the other meta-dies. As such, meta-dies-N may be in an inactive/dormant state without host power, when controlleris programming meta-die.

108 108 0 3 104 108 0 3 108 1 1 0 2 2 1 3 3 2 Prior to programming data on a meta-die, controllermay perform an erase operation on the meta-die. For example, when controlleris writing the four GB host data to meta-dies-, based on the host operations pending in storage device, controllermay determine that the host data is to be written to the meta blocks on meta-dies-. As such, controllermay determine that the dies in meta-diemay have to be erased such that the dies in meta-diemay be ready to be programmed after the dies in meta-diehave been programmed, that the dies in meta-diemay have to be erased such that the dies in meta-diemay be ready to be programmed after the dies in meta-diehave been programmed, and that the dies in meta-diemay have to be erased such that the dies in meta-diemay be ready to be programmed after the dies in meta-diehave been programmed.

108 0 108 1 1 108 0 104 118 102 While controlleris programing the first GB on the meta-block in meta-die, controllermay perform an erase operation on meta-dieprior to programming the second GB to the meta block on meta-die. When controlleris performing a burst operation, as noted, a first subset of the dies in the meta-die may be active during the SLC write. For example, four of the dies in meta-diemay be active during a burst write. As such, storage devicemay ensure that capacitor bankreserves 4-die worth of charge from power provided by hostto handle an ungraceful abort operation on the burst data being written to the first subset of dies on the active meta-die.

0 1 108 118 1 1 118 0 102 To hide erase overheads when switching from meta-dieto meta-die, controllermay use the remaining 12-die worth of charge that would otherwise be reserved on capacitor bank, but that may be unused for burst operations, to begin the erase operation on the meta block in meta die. The erase operation on the meta block in meta dieusing the power provided by capacitor bankmay occur in parallel with the burst write on meta-dieusing the power provided by host. In an example where the program time is approximately 100 μs and the erase time is approximately 3 ms, programming of a block would take approximately 8 ms.

108 108 108 1 108 1 1 108 1 108 0 108 1 108 1 1 Controllermay execute multiple burst sessions to fully program an active meta-die. For example, in a sixteen die meta-die configuration where four dies may be programmed during a burst session, controllermay execute four burst sessions to fully program the active meta die. When controlleris performing a burst write on, for example, the first four dies in meta-die(referred to herein as a first burst session on the active meta-die), controllermay use the remaining 12-die worth of capacitor charge to erase the meta-block on a subset of dies in meta-die(the subset of dies on meta-dieare referred to herein as a third subset of dies). For example, controllermay use the remaining 12-die worth of capacitor charge to erase in the first twelve dies in meta-die. When controlleris performing a burst write on the next first four dies in meta-die(referred to herein as a second burst session on the active meta-die), controllermay use the 4-die worth of capacitor charge associated with the second burst session to erase the remaining section of the meta-block in meta-diethat was not erased with the reserved capacitor power associated with the first burst session. For example, controllermay use the 4-die worth of capacitor charge to erase the remaining section of the meta-block in the last four dies in meta-die. In this example, the erase operations on meta-diemay be completed in approximate 3 ms*2 steps, i.e., approximately 6 ms.

118 108 118 108 1 108 108 1 If additional capacitors are added to capacitor bank, controllermay complete the erase process faster. For example, if four capacitors are added to capacitor bank, controllermay use the reserved 16-die worth of capacitor charge associated with the first burst session to erase the meta-block on the sixteen dies on meta-die. As such, controllermay complete the erase process in one step taking approximately 3 ms, i.e., controllermay complete the erase operation on all the dies in meta-diewhen executing the first burst session on the active meta-die.

104 118 108 104 108 104 Storage devicemay have opportunities to charge the capacitors in capacitor bankwith ongoing burst programming as the host power being consumed may be for only a subset of the dies (for example, 4-dies) in the active meta-die. As such, controllermay perform the parallel erase and burst write operation throughout the life cycle of storage device. Controllermay thus avoid stalling host operations due to erase operations and may achieve higher burst performance throughout the life cycle of storage device, as opposed to performing pre-erase operation only on a newly installed drive as is currently the case in a traditional burst write scheme.

108 108 0 0 108 0 1 118 0 1 108 0 1 0 108 Controllermay further avoid stalling host operations due to control write operations including, for example, XOR parity write operations and/or GAT delta write operations. For example, when controlleris performing a burst operation on dieon meta-die, controllermay power up, for example, dieon meta-diewith power from capacitors on capacitor bankand perform the control write operation on dieon meta-die. Controllermay perform the control write operation on dieon meta-diein parallel with a host write operation on the dies on meta-die. By performing the control write operation in a different meta-die from the meta-die on which the host write is being perform, controllermay avoid stalls in the host write path.

104 118 An exemplary set of calculations are provided to show that an erase operation may be carried on a subset of dies an inactive meta-die while burst writes are ongoing in an active meta-die. In an example, the time for programming a meta-die with sixteen dies may be 1 millisecond (ms). To protect against an ungraceful write abort situation on a TLC block, storage devicemay need backup power for 1 ms to complete processing a write operation after a write abort situation occurs, i.e., capacitor bankshould provide sufficient power to keep 16-dies in an active state for 1 ms.

104 118 104 If, for ease of calculation, the power required to power up 16 dies is considered to be equal to 100 megawatt (mW), the energy needed may be equal to 100 mW×1 ms, i.e., 100 mW×1000 μs, which is equal to 100000 mW-μs. If storage deviceis in burst mode at any instant, four dies in a meta-die may be engaged in the burst write and the other twelve dies in the meta-die on which the burst write is taking place may be inactive. The power calculation to protect against a write abort situation on the four dies where the SLC programming time is 60 μs may be (100 mW/16)*4, which may be 25 mW. The energy required may be equal to 25 mW×60 μs, i.e., 1500 mW-μs. The energy left in capacitor bankwhich storage devicemay use to perform pre-erase and/or control write operations may be (100000−1500) mW-μs, i.e., 98500 mW-μs.

102 102 104 118 The energy not consumed from hostin a burst mode may be the power required for the other twelve dies in the meta-die on which the burst write is occurring, which may be equal to (100 mW/16)*12=48 mW, and the energy not consumed from hostas the other twelve dies are inactive during bursting may be equal to 48 mW×60 μs, i.e., 2880 mW-μs. As such, storage devicemay use 2880 mW-μs to power up capacitors in capacitor bank.

104 118 118 118 The total energy which storage devicemay consume for internal operations may be (98500 (i.e., the energy left in capacitor bank)+2880 mW-μs=101380 mW-μs. The erase time may be 3 ms and the power required to erase one physical block in a die may be (100 mW/16), i.e., 6 mW. The energy required to erase one physical block in a die may therefore be 6 mW×3 ms, i.e., 6 mW×3000 μs which is equal to 18000 mW-μs. The number of dies that may be powered up may be 101380 mW-μs/6000 mW-μs. i.e., five dies. Therefore, from this exemplary calculation an existing capacitor bankmay be used to perform erase operation on more than one die in an inactive meta-die while burst writes are ongoing in an active meta-die. There may also be sufficient window and energy to charge capacitor bankwhen writes are ongoing in a burst mode as not all sixteen dies in a meta-die may be engaged in the burst write at any instant.

104 108 110 110 110 108 100 1 FIG. 1 FIG. Storage devicemay perform these processes based on a processor, for example, controllerexecuting software instructions stored by a non-transitory computer-readable medium, such as storage component/memory device. As used herein, the term “computer-readable medium” refers to a non-transitory memory device. Software instructions may be read into storage componentfrom another computer-readable medium or from another device. When executed, software instructions stored in storage componentmay cause controllerto perform one or more processes described herein. Additionally, or alternatively, hardware circuitry may be used in place of or in combination with software instructions to perform one or more processes described herein. Thus, implementations described herein are not limited to any specific combination of hardware circuitry and software. Systemmay include additional components (not shown in this figure for the sake of simplicity).is provided as an example. Other examples may differ from what is described in.

2 FIG. 2 FIG. 2 FIG. 2 FIG. 104 102 104 104 104 0 100 104 0 1 is another schematic block diagram of an example system showing how host power is supplied to meta-dies in accordance with some implementations. When storage deviceis writing data to a meta-die, hostmay supply power to storage device. In a case where the peak power consumed by storage device is sufficient to only power one meta-die, storage devicemay supply power to the meta-die on which it is performing host operation. As shown in, storage devicemay supply power to meta-die, i.e., the meta-die on which it is performing host operation. The components of systemthat are being supplied host power when storage deviceis writing to meta-dieare shaded. Meta-dies-N are inactive and are thus not supplied host power.is provided as an example. Other examples may differ from what is described in.

3 FIG. 104 104 0 108 0 0 104 118 102 is another schematic block diagram of an example system showing how host power and capacitor power are supplied to meta-dies in accordance with some implementations. Host power is being supplied to a meta-die on which storage deviceis performing host operations. The components of the system that are being supplied host power when storage deviceis writing to meta-dieare shaded. If controlleris performing a burst operation, as noted, a sub-section of the dies in meta-diemay be active during the SLC write. For example, four of the dies in meta-diemay be active during a burst write. As such, storage devicemay ensure that capacitor bankreserves 4-die worth of charge from power provided by hostto handle an ungraceful abort operation on the burst data.

108 118 1 104 0 1 1 0 104 118 0 108 104 3 FIG. 3 FIG. Controllermay use the remaining 12-die worth of charge that would otherwise be reserved on capacitor bank, but that may be unused for burst operations, to begin an erase or control write operation on the meta block in meta die. The components of the system that are being supplied capacitor power when storage deviceis writing to meta-dieare shown with slanted lines. As such, the dies in meta-dieare shown with slanted lines. The erase operation on the meta blocks in meta diemay occur in parallel with the burst write on meta-die. Storage devicemay have opportunities to charge the capacitors in capacitor bankwith ongoing burst programming as the host power being consumed may be for only a sub-set of the dies (for example, 4-dies) in meta-die. As such, controllermay perform the parallel erase and burst write operation throughout the life cycle of storage device. As indicated aboveis provided as an example. Other examples may differ from what is described in.

4 FIG. 4 FIG. 4 FIG. 410 104 118 102 118 420 108 430 104 118 102 104 440 108 104 450 104 118 is an example flow diagram for using power from a capacitor to boost the performance of a storage device in accordance with some implementations. At, storage devicemay charge a capacitor bankwith power from hostsuch that capacitor bankmay include sufficient backup power to carry out a sustained write on all active dies in a first meta-die. At, controllermay perform burst writes with a first subset of dies in the first meta-die such that host power supplied to a second subset of dies in the first meta-die may not be used during the burst write. At, storage devicemay use the capacitors in capacitor bankto power up inactive/dormant dies in a second meta-die without drawing more power from host, while controllerperforms a burst operation on the first meta-die. At, when controlleris performing a burst operation on the first subset of dies in the first meta-die, storage devicemay use the capacitor power for the second subset of dies in the first meta-die to perform an erase operation on a set of dies in the second meta-die. At, storage devicemay charge the capacitors in capacitor bankwith ongoing burst programming. As indicated aboveis provided as an example. Other examples may differ from what is described in.

5 FIG. 5 FIG. 5 FIG. 510 104 118 102 118 520 108 530 104 118 102 104 540 108 104 is another example flow diagram for using power from a capacitor to boost the performance of a storage device in accordance with some implementations. At, storage devicemay charge a capacitor bankwith power from hostsuch that capacitor bankmay include sufficient backup power to carry out a sustained write on all active dies in a first meta-die. At, controllermay perform burst writes with a first subset of dies in the first meta-die such that host power supplied to a second subset of dies in the first meta-die may not be used during the burst write. At, storage devicemay use the capacitors in capacitor bankto power up inactive/dormant dies in a second meta-die without drawing more power from host, while controllerperforms a burst operation on the first meta-die. At, when controlleris performing a burst operation on the first subset of dies in the first meta-die, storage devicemay use the capacitor power for the second subset of dies in the first meta-die to perform control write operations on a die in the second meta-die. As indicated aboveis provided as an example. Other examples may differ from what is described in.

6 FIG. 6 FIG. 600 102 102 102 104 104 104 108 104 102 104 n a n is a diagram of an example environment in which systems and/or methods described herein are implemented. As shown in, Environmentmay include hosts-(referred to herein as host(s)), and one or more storage devices-(referred to herein as storage device(s)). Controllermay use power from a capacitor to boost the performance of storage device. Hostsand storage devicesmay communicate via Non-Volatile Memory Express (NVMe) over peripheral component interconnect express (PCI Express or PCIe), SD, or the like.

600 6 FIG. Devices of Environmentmay interconnect via wired connections, wireless connections, or a combination of wired and wireless connections. For example, the network inmay include NVMe over Fabric(NVMe-oF) Internet Small Computer Systems Interface (iSCSI), Fibre Channel (FC), Fibre Channel Over Ethernet (FCoE) connectivity and any another type of next-generation network and storage protocols, a local area network (LAN), a wide area network (WAN), a metropolitan area network (MAN), a private network, an ad hoc network, an intranet, the Internet, a fiber optic-based network, a cloud computing network, or the like, and/or a combination of these or other types of networks.

6 FIG. 6 FIG. 6 FIG. 6 FIG. 600 600 The number and arrangement of devices and networks shown inare provided as an example. In practice, there may be additional devices and/or networks, fewer devices and/or networks, different devices and/or networks, or differently arranged devices and/or networks than those shown in. Furthermore, two or more devices shown inmay be implemented within a single device, or a single device shown inmay be implemented as multiple, distributed devices. Additionally, or alternatively, a set of devices (e.g., one or more devices) of Environmentmay perform one or more functions described as being performed by another set of devices of Environment.

7 FIG. 1 FIG. 102 700 700 700 705 710 715 720 725 730 730 700 700 700 730 is a diagram of example components of one or more devices of. In some implementations, hostmay include one or more devicesand/or one or more components of device. Devicemay include, for example, a communications component, an input component, an output component, a processor, a storage component, and a bus. Busmay include components that enable communication among multiple components of device, wherein components of devicemay be coupled to be in communication with other components of devicevia bus.

710 700 700 715 700 710 715 720 Input componentmay include components that permit deviceto receive information via user input (e.g., keypad, a keyboard, a mouse, a pointing device, and a network/data connection port, or the like), and/or components that permit deviceto determine the location or other sensor information (e.g., an accelerometer, a gyroscope, an actuator, another type of positional or environmental sensor). Output componentmay include components that provide output information from device(e.g., a speaker, display screen, and network/data connection port, or the like). Input componentand output componentmay also be coupled to be in communication with processor.

720 720 720 Processormay be a central processing unit (CPU), a graphics processing unit (GPU), an accelerated processing unit (APU), a microprocessor, a microcontroller, a digital signal processor (DSP), a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), or another type of processing component. In some implementations, processormay include one or more processors capable of being programmed to perform a function. Processormay be implemented in hardware, firmware, and/or a combination of hardware and software.

725 720 725 700 725 Storage componentmay include one or more memory devices, such as random-access memory, read-only memory (ROM), and/or another type of dynamic or static storage device (e.g., a flash memory, a magnetic memory, and/or optical memory) that stores information and/or instructions for use by processor. A memory device may include memory space within a single physical storage device or memory space spread across multiple physical storage devices. Storage componentmay also store information and/or software related to the operation and use of device. For example, storage componentmay include a hard disk (e.g., a magnetic disk, an optical disk, and/or a magneto-optic disk), a solid-state drive (SSD), a compact disc (CD), a digital versatile disc (DVD), a floppy disk, a cartridge, a magnetic tape, CXL device and/or another type of non-transitory computer-readable medium, along with a corresponding drive.

705 700 705 700 705 705 705 Communications componentmay include a transceiver-like component that enables deviceto communicate with other devices, such as via a wired connection, a wireless connection, or a combination of wired and wireless connections. The communications componentmay permit deviceto receive information from another device and/or provide information to another device. For example, communications componentmay include an Ethernet interface, an optical interface, a coaxial interface, an infrared interface, a radio frequency (RF) interface, a universal serial bus (USB) interface, a Wi-Fi interface, and/or a cellular network interface that may be configurable to communicate with network components, and other user equipment within its communication range. Communications componentmay also include one or more broadband and/or narrowband transceivers and/or other similar types of wireless transceiver configurable to communicate via a wireless network for infrastructure communications. Communications componentmay also include one or more local area network or personal area network transceivers, such as a Wi-Fi transceiver or a Bluetooth transceiver.

700 700 720 725 725 705 725 720 Devicemay perform one or more processes described herein. For example, devicemay perform these processes based on processorexecuting software instructions stored by a non-transitory computer-readable medium, such as storage component. As used herein, the term “computer-readable medium” refers to a non-transitory memory device. Software instructions may be read into storage componentfrom another computer-readable medium or from another device via communications component. When executed, software instructions stored in storage componentmay cause processorto perform one or more processes described herein. Additionally, or alternatively, hardware circuitry may be used in place of or in combination with software instructions to perform one or more processes described herein. Thus, implementations described herein are not limited to any specific combination of hardware circuitry and software.

7 FIG. 7 FIG. 700 700 700 The number and arrangement of components shown inare provided as an example. In practice, devicemay include additional components, fewer components, different components, or differently arranged components than those shown in. Additionally, or alternatively, a set of components (e.g., one or more components) of devicemay perform one or more functions described as being performed by another set of components of device.

The foregoing disclosure provides illustrative and descriptive implementations but is not intended to be exhaustive or to limit the implementations to the precise form disclosed herein. One of ordinary skill in the art will appreciate that various modifications and changes can be made without departing from the scope of the present disclosure as set forth in the claims below. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of present teachings.

As used herein, the term “component” is intended to be broadly construed as hardware, firmware, and/or a combination of hardware and software. It will be apparent that systems and/or methods described herein may be implemented in different forms of hardware, firmware, and/or a combination of hardware and software.

Even though particular combinations of features are recited in the claims and/or disclosed in the specification, these combinations are not intended to limit the disclosure of various implementations. In fact, many of these features may be combined in ways not specifically recited in the claims and/or disclosed in the specification. Although each dependent claim listed below may directly depend on only one claim, the disclosure of various implementations includes each dependent claim in combination with every other claim in the claim set.

No element, act, or instruction used herein should be construed as critical or essential unless explicitly described as such. Also, as used herein, the articles “a” and “an” are intended to include one or more items and may be used interchangeably with “one or more.” Furthermore, as used herein, the term “set” is intended to include one or more items (e.g., related items, unrelated items, a combination of related items, unrelated items, and/or the like), and may be used interchangeably with “one or more.” The term “only one” or similar language is used where only one item is intended. Further, the phrase “based on” is intended to mean “based, at least in part, on” unless explicitly stated otherwise.

Moreover, in this document, relational terms such as first and second, top and bottom, and the like, may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. The terms “comprises,” “comprising,” “has”, “having,” “includes”, “including,” “contains”, “containing” or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises, has, includes, contains a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by “comprises . . . a”, “has . . . a”, “includes . . . a”, or “contains . . . a” does not, without more constraints, preclude the existence of additional identical elements in the process, method, article, or apparatus that comprises, has, includes, contains the element. The terms “substantially”, “essentially”, “approximately”, “about” or any other version thereof, are defined as being close to as understood by one of ordinary skill in the art, and in one non-limiting implementation, the term is defined to be within 10%, in another implementation within 5%, in another implementation within 1% and in another implementation within 0.5%. The term “coupled” as used herein is defined as connected, although not necessarily directly and not necessarily mechanically. A device or structure that is “configured” in a certain way is configured in at least that way but may also be configured in ways that are not listed.