Pixel Circuit and Driving Method Thereof, Display Apparatus

The present application claims the priority of the Patent Application No. PCT/CN2023/113514 filed on Aug. 17, 2023, the entire contents disclosed by the above patent application are hereby incorporated by reference.

At least one embodiment of the present disclosure relates to a pixel circuit and a driving method thereof, and a display apparatus.

With continuous development of display technology, Organic Light-Emitting Diodes (OLED) and Quantum-dot Light-Emitting Diodes (QLED) are active light-emitting display devices with advantages of self-luminescence, wide viewing angle, high contrast, low power consumption, extremely high response speed, light weight, bendability and low cost.

At least one embodiment of the disclosure provides a pixel circuit and a driving method thereof, and a display apparatus.

At least one embodiment of the disclosure provides a pixel circuit, which includes a driving circuit, a first compensation circuit, a light-emitting element, a second light-emitting control circuit and a reset control circuit, the driving circuit includes a control terminal, a first terminal and a second terminal, and is configured to control a magnitude of a driving current flowing through the first terminal and the second terminal; the first compensation circuit is configured to apply a reference signal to the control terminal of the driving circuit in response to a first compensation control signal, the first compensation circuit includes a first storage capacitor, a first electrode of the first storage capacitor is electrically connected to the control terminal of the driving circuit, and a second electrode of the first storage capacitor is electrically connected to the first terminal of the driving circuit; the light-emitting element is configured to emit light driven by the driving current, a second electrode of the light-emitting element is electrically connected to a second voltage terminal to receive a second power supply voltage; a control terminal of the second light-emitting control circuit is configured to receive a second light-emitting control signal, a first terminal of the second light-emitting control circuit is electrically connected to the first terminal of the driving circuit, a second terminal of the second light-emitting control circuit is electrically connected to a first electrode of the light-emitting element, and the second light-emitting control circuit is configured to apply the driving current to the light-emitting element in response to the second light-emitting control signal and allow a reset signal to be applied to the first terminal of the driving circuit; a control terminal of the reset control circuit is configured to receive a reset control signal, a first terminal of the reset control circuit is electrically connected to the first terminal of the driving circuit, a second terminal of the reset control circuit is electrically connected to a reset signal terminal to receive the reset signal, a third terminal of the reset control circuit is electrically connected to the first electrode of the light-emitting element, and the reset control circuit is configured to apply the reset signal to the first electrode of the light-emitting element and/or the first terminal of the driving circuit in response to the reset control signal.

For example, in the pixel circuit according to at least one embodiment of the disclosure, the reset control circuit includes a second compensation circuit and a reset circuit, the second compensation circuit includes a second storage capacitor, the second storage capacitor is electrically connected between the first terminal of the driving circuit and the reset signal terminal; and a control terminal of the reset circuit serves as the control terminal of the reset control circuit and is configured to receive the reset control signal, a first terminal of the reset circuit serves as the third terminal of the reset control circuit and is electrically connected to the first electrode of the light-emitting element, and a second terminal of the reset circuit serves as the second terminal of the reset control circuit and is electrically connected to the reset signal terminal to receive the reset signal.

For example, in the pixel circuit according to at least one embodiment of the disclosure, a value of the reset signal is adjustable.

For example, in the pixel circuit according to at least one embodiment of the disclosure, the reset signal includes at least a first reset signal and a second reset signal, the first reset signal corresponds to a first display temperature, the second reset signal corresponds to a second display temperature, the first display temperature is lower than the second display temperature, and a value of the first reset signal is lower than a value of the second reset signal.

For example, in the pixel circuit according to at least one embodiment of the disclosure, the first reset signal is adjusted to the second reset signal during a reset signal adjustment period, and the pixel circuit corresponds to a plurality of display frame cycles, the reset signal adjustment period is located between two adjacent display frame cycles of the plurality of display frame cycles; or the reset signal adjustment period is located within one display frame cycle of the plurality of display frame cycles; the one display frame cycle includes at least a reset phase, a compensation phase, a data writing phase and a light-emitting phase; and the reset signal adjustment period overlaps at least partially or does not overlap with any one selected from a group consisting of the reset phase, the compensation phase, the data writing phase and the light-emitting phase.

For example, in the pixel circuit according to at least one embodiment of the disclosure, a value of the reference signal is adjustable.

For example, in the pixel circuit according to at least one embodiment of the disclosure, a first electrode of the second storage capacitor serves as the first terminal of the reset control circuit and is electrically connected to the first terminal of the driving circuit, and a second electrode of the second storage capacitor is electrically connected to the first terminal of the reset circuit.

For example, the pixel circuit according to at least one embodiment of the disclosure further includes a first light-emitting control circuit, a control terminal of the first light-emitting control circuit is configured to receive a first light-emitting control signal, a first terminal of the first light-emitting control circuit is electrically connected to the second terminal of the driving circuit, a second terminal of the first light-emitting control circuit is electrically connected to a first voltage terminal to receive a first power supply voltage, and the first light-emitting control circuit is configured to apply the first power supply voltage to the second terminal of the driving circuit in response to the first light-emitting control signal.

For example, in the pixel circuit according to at least one embodiment of the disclosure, the first light-emitting control circuit includes a first light-emitting control transistor, a gate electrode of the first light-emitting control transistor is electrically connected to a first light-emitting control terminal to receive the first light-emitting control signal, a first electrode of the first light-emitting control transistor is electrically connected to the second terminal of the driving circuit, and a second electrode of the first light-emitting control transistor is electrically connected to the first voltage terminal to receive the first power supply voltage.

For example, in the pixel circuit according to at least one embodiment of the disclosure, the second terminal of the driving circuit is directly electrically connected to a first voltage terminal to receive a first power supply voltage.

For example, in the pixel circuit according to at least one embodiment of the disclosure, the reset circuit includes a reset transistor, a gate electrode of the reset transistor is electrically connected to a reset control terminal to receive the reset control signal, a first electrode of the reset transistor is electrically connected to the second electrode of the second storage capacitor and the first terminal of the driving circuit, and a second electrode of the reset transistor is electrically connected to the reset signal terminal to receive the reset signal.

For example, in the pixel circuit according to at least one embodiment of the disclosure, the second light-emitting control circuit includes a second light-emitting control transistor, a gate electrode of the second light-emitting control transistor is electrically connected to a second light-emitting control terminal to receive the second light-emitting control signal, a first electrode of the second light-emitting control transistor is electrically connected to the first terminal of the driving circuit, and a second electrode of the second light-emitting control transistor is electrically connected to the first electrode of the light-emitting element.

For example, the pixel circuit according to at least one embodiment of the disclosure further includes an auxiliary compensation circuit, a control terminal of the auxiliary compensation circuit is configured to receive an auxiliary compensation signal, a first terminal of the auxiliary compensation circuit is electrically connected to the second electrode of the second storage capacitor, and a second terminal of the auxiliary compensation circuit is electrically connected to the first electrode of the light-emitting element.

For example, in the pixel circuit according to at least one embodiment of the disclosure, the first terminal of the auxiliary compensation circuit is also electrically connected to the second terminal of the second light-emitting control circuit and the first terminal of the reset circuit.

For example, in the pixel circuit according to at least one embodiment of the disclosure, the auxiliary compensation circuit includes an auxiliary compensation transistor, a gate electrode of the auxiliary compensation transistor serves as the control terminal of the auxiliary compensation circuit to receive the auxiliary compensation control signal, a first electrode of the auxiliary compensation transistor is electrically connected to the second electrode of the second compensation capacitor and the second electrode of the second light-emitting control transistor, and a second electrode of the auxiliary compensation transistor is electrically connected to the first electrode of the light-emitting element.

For example, in the pixel circuit according to at least one embodiment of the disclosure, the first terminal of the auxiliary compensation circuit is also electrically connected to the first terminal of the reset circuit, and the second terminal of the auxiliary compensation circuit is also electrically connected to the second terminal of the second light-emitting control circuit.

For example, in the pixel circuit according to at least one embodiment of the disclosure, the auxiliary compensation circuit includes an auxiliary compensation transistor, a gate electrode of the auxiliary compensation transistor is electrically connected to an auxiliary compensation control terminal to receive the auxiliary compensation control signal, a first electrode of the auxiliary compensation transistor is electrically connected to the second electrode of the second compensation capacitor and the first electrode of the reset transistor, and a second electrode of the auxiliary compensation transistor is electrically connected to the first electrode of the light-emitting element.

For example, in the pixel circuit according to at least one embodiment of the disclosure, the gate electrode of the auxiliary compensation transistor is electrically connected to the gate electrode of the second light-emitting control transistor, the auxiliary compensation transistor and the second light-emitting control transistor share a gate electrode, the second light-emitting control signal serves as the auxiliary compensation control signal, and a type of the auxiliary compensation transistor is same as a type of the second light-emitting control transistor; or the gate electrode of the auxiliary compensation transistor and the gate electrode of the second light-emitting control transistor are independent of each other and not electrically connected.

For example, in the pixel circuit according to at least one embodiment of the disclosure, the gate electrode of the auxiliary compensation transistor is electrically connected to the gate electrode of the reset transistor, the auxiliary compensation transistor and the reset transistor share a gate electrode, the reset control signal serves as the auxiliary compensation control signal, and a type of the auxiliary compensation transistor is same as a type of the reset transistor; or the gate electrode of the auxiliary compensation transistor and the gate electrode of the reset transistor are independent of each other and not electrically connected.

For example, in the pixel circuit according to at least one embodiment of the disclosure, the driving circuit includes a driving transistor, a gate electrode of the driving transistor serves as the control terminal of the driving circuit and is electrically connected to a first node, a first electrode of the driving transistor serves as the first terminal of the driving circuit and is electrically connected to a first electrode of the second storage capacitor at a second node, and a second electrode of the driving transistor serves as the second terminal of the driving circuit and is electrically connected to a first voltage terminal to receive a first power supply voltage; the pixel circuit further includes: a data writing circuit, a control terminal of the data writing circuit is configured to receive a data scanning signal, a first terminal of the data writing circuit is electrically connected to a data signal terminal to receive a data signal, a second terminal of the data writing circuit is electrically connected to the first node, and the data writing circuit is configured to write the data signal to the control terminal of the driving circuit in response to the data scanning signal.

For example, in the pixel circuit according to at least one embodiment of the disclosure, a control terminal of the first compensation circuit is configured to receive the first compensation control signal, a first terminal of the first compensation circuit is electrically connected to a reference signal terminal to receive the reference signal, and a second terminal of the first compensation circuit is electrically connected to the second node, the first compensation circuit further includes a first compensation transistor, a gate electrode of the first compensation transistor serves as the control terminal of the first compensation circuit and is electrically connected to a first compensation control signal terminal to receive the first compensation control signal, a first electrode of the first compensation transistor serves as the first terminal of the first compensation circuit and is electrically connected to the reference signal terminal to receive the reference signal, and a second electrode of the first compensation transistor is electrically connected to the first node, the data writing circuit includes a data writing transistor, a gate electrode of the data writing transistor is electrically connected to a data scanning signal terminal to receive the data scanning signal, a first electrode of the data writing transistor is electrically connected to the data signal terminal to receive the data signal, and a second electrode of the data writing transistor is electrically connected to the first node.

For example, in the pixel circuit according to at least one embodiment of the disclosure, the data writing transistor and the first compensation transistor are transistors controlled independently of each other, the data scanning signal terminal and the first compensation control signal terminal are different signal terminals independent of each other, and the data signal terminal and the reference signal terminal are different signal terminals independent of each other; or the data writing transistor also serves the first compensation transistor, the data scanning signal also serves the first compensation control signal, the first electrode of the data writing transistor is also electrically connected to the reference signal terminal to receive the reference signal, and the data signal terminal also serves the reference signal terminal and is configured to provide the data signal or the reference signal in different time periods.

At least one embodiment of the disclosure further provides a display apparatus, which includes the pixel circuit according to any embodiments as mentioned above.

At least one embodiment of the disclosure further provides a driving method, which is applicable to the pixel circuit according to any embodiments as mentioned above, the driving method includes: setting the reset control signal as an On signal so that the reset signal is applied to the first electrode of the light-emitting element and/or the first terminal of the driving circuit through the reset control circuit.

For example, in the driving method according to at least one embodiment of the disclosure, the reset control circuit includes a second compensation circuit and a reset circuit, and the second compensation circuit includes a second storage capacitor, a first electrode of the second storage capacitor serves as the first terminal of the reset control circuit and is electrically connected to the first terminal of the driving circuit, and a second electrode of the second storage capacitor is electrically connected to a first terminal of the reset circuit; a control terminal of the reset circuit serves as the control terminal of the reset control circuit and is configured to receive the reset control signal, a first terminal of the reset circuit serves as the third terminal of the reset control circuit and is electrically connected to the first electrode of the light-emitting element, a second terminal of the reset circuit serves as the second terminal of the reset control circuit and is electrically connected to the reset signal terminal to receive the reset signal, the driving method includes a reset phase, a compensation phase, a data writing phase and a light-emitting phase, in the reset phase, the reset control signal is set to be an ON signal in at least part of a time period so that the first terminal and the second terminal of the reset circuit are turned on, and the reset signal is applied to the second electrode of the second storage capacitor, the first terminal of the driving circuit and the first electrode of the light-emitting element through the second terminal and the first terminal of the reset circuit in sequence; in the compensation phase and the data writing phase, the reset control signal is set to be an ON signal, and the reset signal is applied to the second electrode of the second storage capacitor and the first electrode of the light-emitting element through the second terminal and the first terminal of the reset circuit in sequence; and in the light-emitting phase, the reset control signal is set to be an OFF signal in at least part of a time period of the light-emitting phase, so that the second electrode of the second storage capacitor is electrically disconnected from the reset signal terminal.

101 104 101 102 104 For example, in the driving method according to at least one embodiment of the disclosure, the pixel circuit further includes a data writing circuit and a first light-emitting control circuit; a control terminal of the data writing circuit is configured to receive a data scanning signal, a first terminal of the data writing circuit is electrically connected to a data signal terminal to receive a data signal, and a second terminal of the data writing circuit is electrically connected to the control terminal of the driving circuit; a control terminal of the first light-emitting control circuit is configured to receive a first light-emitting control signal, a first terminal of the first light-emitting control circuit is electrically connected to the second terminal of the driving circuit, and a second terminal of the first light-emitting control circuit is electrically connected to a first voltage terminal so that the second terminal of the driving circuit receives a first power supply voltage; in the light-emitting phase, the driving method includes sequentially performing steps Sto S; step S: setting the data scanning signal as an OFF signal to turn off the data writing circuit; step S: setting the second light-emitting control signal to an ON signal to turn on the second light-emitting control circuit, and keeping the first light-emitting control signal as an OFF signal to turn off the first light-emitting control circuit; and step S: setting the first light-emitting control signal to an ON signal to turn on the first light-emitting control circuit, so that the second terminal of the driving circuit receives the first power supply voltage from the first voltage terminal through the first light-emitting control circuit.

1010 1030 1010 1020 1030 For example, in the driving method according to at least one embodiment of the disclosure, the pixel circuit further includes a data writing circuit and a first light-emitting control circuit; a control terminal of the data writing circuit is configured to receive a data scanning signal, a first terminal of the data writing circuit is electrically connected to a data signal terminal to receive a data signal, and a second terminal of the data writing circuit is electrically connected to the control terminal of the driving circuit; a control terminal of the first light-emitting control circuit is configured to receive a first light-emitting control signal, a first terminal of the first light-emitting control circuit is electrically connected to the second terminal of the driving circuit, and a second terminal of the first light-emitting control circuit is electrically connected to a first voltage terminal so that the second terminal of the driving circuit receives a first power supply voltage; in the reset phase, the driving method includes sequentially performing steps Sto S; step S: electrically disconnecting the second terminal of the driving circuit from the first voltage terminal; step S: setting the reset control signal as an ON signal to turn on the reset circuit; and step S: setting the first compensation control signal as an ON signal to turn on the first compensation circuit, and, in the reset phase, the data scanning signal remains as an OFF signal to turn off the data writing circuit, and the second light-emitting control signal remains as an ON signal to turn on the second light-emitting control circuit.

2010 2020 2010 2020 For example, in the driving method according to at least one embodiment of the disclosure, in the compensation phase, the driving method includes sequentially performing steps Sto S; step S: setting the second light-emitting control signal as an OFF signal to turn off the second light-emitting control circuit, and keeping the first light-emitting control signal as an OFF signal to turn off the first light-emitting control circuit; step S: setting the first light-emitting control signal as an ON signal to turn on the first light-emitting control circuit, and keeping the second light-emitting control signal as an OFF signal; and, in the compensation phase, the data scanning signal remains as an OFF signal to keep the data writing circuit turned off, and the first compensation control signal remains as an ON signal to keep the first compensation circuit turned on.

3010 3030 3010 3030 For example, in the driving method according to at least one embodiment of the disclosure, the pixel circuit further includes a data writing circuit, a control terminal of the data writing circuit is configured to receive a data scanning signal, a first terminal of the data writing circuit is electrically connected to a data signal terminal to receive a data signal, and a second terminal of the data writing circuit is electrically connected to the control terminal of the driving circuit, in the data writing phase, the driving method includes sequentially performing steps Sto S; step S: setting the first compensation control signal as an OFF signal to turn off the first compensation circuit, and keeping the second terminal of the driving circuit receiving a first power supply voltage; step S: setting the data scanning signal as an ON signal to turn on the data writing circuit; and, in the data writing phase, the second light-emitting control signal remains as an OFF signal to keep the second light-emitting control circuit turned off.

3030 For example, in the driving method according to at least one embodiment of the disclosure, the pixel circuit further includes a first light-emitting control circuit, a control terminal of the first light-emitting control circuit is configured to receive a first light-emitting control signal, a first terminal of the first light-emitting control circuit is electrically connected to the second terminal of the driving circuit, and a second terminal of the first light-emitting control circuit is electrically connected to a first voltage terminal so that the second terminal of the driving circuit receives a first power supply voltage; and the step Sfurther includes: setting the first light-emitting control signal as an ON signal to turn on the first light-emitting control circuit, so that the second terminal of the driving circuit receives the first power supply voltage.

In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be described clearly and completely in the following in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are a part of the embodiments of the present disclosure, and not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by a person of ordinary skill in the art without the need for creative labor fall within the scope of protection of the present disclosure.

Unless otherwise defined, technical or scientific terms used in the present disclosure shall have the ordinary meaning understood by a person of ordinary skill in the art to which the present disclosure belongs. The terms “first”, “second”, and the like as used in the present disclosure do not indicate any order, number, or significance, but are only used to distinguish different components. Words such as “including” or “comprising” and the like are intended to mean that the component or object preceded by the word encompasses the component or object enumerated after the word and its equivalents, and does not exclude other components or objects.

Features such as “perpendicular”, “parallel”, and “the same” as used in embodiments of the present disclosure include “perpendicular”, “parallel”, and “identical” in the strict sense, as well as “substantially perpendicular”, “substantially parallel”, “approximately the same”, etc. that include a certain amount of error, taking into account the measurement and the error associated with the measurement of the particular quantity (i.e., the limitations of the measurement system), which indicates being within a range of acceptable deviations for the particular value as determined by a person of ordinary skill in the art. “Center” in embodiments of the present disclosure may include a location strictly at the geometric center as well as a location approximately at the center within a small area around the geometric center.

In some cases, display apparatus may experience short-term residual images when displaying, meaning that after displaying the same image for a period of time, when the image currently displayed is switched to a next image, the original image partially remains and emerges in the next image, and then after a period of time, the short-term residual image will disappear. The short-term residual image may be caused by a lag effect in the driving transistor of the pixel circuit. The lag effect is mainly due to the shifting of a threshold voltage (Vth) caused by movable ions remaining in holes. When the display apparatus switches images, the Vgs (a voltage difference between the gate electrode and the source electrode of the driving transistor) of the driving transistor in the initialization stage may be different, causing the threshold voltage of the driving transistor to shift.

For example, after the display apparatus has displayed an initial image for a period of time, when the display apparatus switches to a new image, the initial image is partially retained for several hours, thereby affecting the display. Therefore, there is an urgent need to solve a problem of the threshold voltage (Vth) shifting of the driving transistor.

A pixel circuit using oxide has been increasingly applied in display apparatuses. The pixel circuit features a high refresh rate and a manufacturing process with high uniformity. In some pixel circuits, a first electrode of the driving transistor is directly connected to a reset signal terminal, causing fluctuation of a reset signal to affect voltage stability of the first electrode of the driving circuit. In other pixel circuits, the first electrode of the driving transistor is electrically connected to a first light-emitting control transistor, a second electrode of the driving transistor is electrically connected to a light-emitting element through a second light-emitting control transistor, a first electrode of a storage capacitor is electrically connected to the first electrode of the driving transistor, and a second electrode of the storage capacitor is electrically connected to a constant signal terminal to receive a constant signal, for example, the constant signal may be a reset signal. When the above constant signal is unstable, it is easy to cause a voltage of the second electrode of the storage capacitor to fluctuate, thereby causing external noise to be introduced into the pixel circuit. For example, when the pixel circuit enters a light-emitting phase from a data writing phase, the reset signal needs to be switched from an ON signal to an OFF signal, which easily increases a risk of introducing noise into the pixel circuit, thereby causing the driving current to be unstable and affecting a display effect.

At least one embodiment of the present disclosure provides a pixel circuit and a driving method thereof, and a display apparatus.

At least one embodiment of the present disclosure provides a pixel circuit including a driving circuit, a first compensation circuit, a light-emitting element, a second light-emitting control circuit and a reset control circuit, in which the driving circuit includes a control terminal, a first terminal and a second terminal, and is configured to control a magnitude of a driving current flowing through the first terminal and the second terminal; the first compensation circuit is configured to apply a reference signal to the control terminal of the driving circuit in response to a first compensation control signal, the first compensation circuit includes a first storage capacitor, a first electrode of the first storage capacitor is electrically connected to the control terminal of the driving circuit, and a second electrode of the first storage capacitor is electrically connected to the first terminal of the driving circuit; the light-emitting element is configured to emit light driven by the driving current, and a second electrode of the light-emitting element is electrically connected to a second voltage terminal to receive a second power supply voltage; a control terminal of the second light-emitting control circuit is configured to receive a second light-emitting control signal, a first terminal of the second light-emitting control circuit is electrically connected to the first terminal of the driving circuit, a second terminal of the second light-emitting control circuit is electrically connected to a first electrode of the light-emitting element, and the second light-emitting control circuit is configured to apply the driving current to the light-emitting element in response to the second light-emitting control signal and allow a reset signal to be applied to the first terminal of the driving circuit; a control terminal of the reset control circuit is configured to receive a reset control signal, a first terminal of the reset control circuit is electrically connected to the first terminal of the driving circuit, a second terminal of the reset control circuit is electrically connected to a reset signal terminal to receive a reset signal, a third terminal of the reset control circuit is electrically connected to the first electrode of the light-emitting element, and the reset control circuit is configured to apply the reset signal to the first electrode of the light-emitting element and/or the first terminal of the driving circuit in response to the reset control signal.

The pixel circuit provided by at least one embodiment of the present disclosure is provided with the reset control circuit, and the first terminal of the reset control circuit is electrically connected to the first terminal of the driving circuit, and the second terminal of the reset control circuit is electrically connected to the reset signal terminal, so that the reset signal needs to pass through the reset control circuit before it may be applied to the first electrode of the light-emitting element and/or to the first terminal of the driving circuit, thereby reducing impact of the fluctuation of the reset signal on the voltage of the first electrode of the light-emitting element and the first terminal of the driving circuit, and reducing the risk of introducing noise into the pixel circuit, so as to cause the driving current to be more stable to improve the display effect.

The pixel circuit and the driving method thereof, and the display apparatus provided by the embodiments of the present disclosure are described below in conjunction with the accompanying drawings.

1 FIG. is a schematic block diagram of a pixel circuit provided by at least one embodiment of the present disclosure.

1 FIG. 10 100 300 500 600 780 As shown in, a pixel circuitincludes a driving circuit, a first compensation circuit, a second light-emitting control circuit, a light-emitting elementand a reset control circuit.

1 FIG. 100 100 100 100 100 100 1 100 100 2 100 100 3 100 100 100 600 100 600 600 m a b m a b a b As shown in, the driving circuitincludes a control terminal, a first terminal, and a second terminal. The control terminalof the driving circuitis electrically connected to a first node N, the first terminalof the driving circuitis electrically connected to a second node N, and the second terminalof the driving circuitis electrically connected to a third node N. The driving circuitis configured to control a magnitude of a driving current flowing through the first terminaland the second terminal. For example, the driving current may be used to drive the light-emitting elementto emit light. For example, in a light-emitting phase, the driving circuitmay provide the light-emitting elementwith the driving current to drive the light-emitting elementto emit light.

1 FIG. 2 FIG. 300 300 300 300 300 300 300 2 300 300 300 300 2 300 300 1 300 100 100 2 300 1 1 100 100 1 100 100 m a b c m a b c m m a As shown in, the first compensation circuitincludes a control terminal, a first terminal, a second terminal, and a third terminal. The control terminalof the first compensation circuitis configured to receive a first compensation control signal G, the first terminalof the first compensation circuitis electrically connected to a reference signal terminal REF to receive a reference signal REF, the second terminalof the first compensation circuitis electrically connected to the second node N, and the third terminalof the first compensation circuitis electrically connected to the first node N. The first compensation circuitis configured to apply the reference signal REF to the control terminalof the driving circuitin response to the first compensation control signal G. For example, the first compensation circuitmay include a first storage capacitor C(see), a first electrode of the first storage capacitor Cis electrically connected to the control terminalof the driving circuit, and a second electrode of the first storage capacitor Cis electrically connected to the first terminalof the driving circuit. However, the embodiments of the present disclosure are not limited thereto.

1 FIG. 500 500 500 500 500 500 2 500 500 100 100 500 500 600 600 500 600 2 100 100 500 2 100 600 500 m a b m a a b a a For example, as shown in, the second light-emitting control circuitincludes a control terminal, a first terminal, and a second terminal. The control terminalof the second light-emitting control circuitis configured to receive a second light-emitting control signal EM, the first terminalof the second light-emitting control circuitis electrically connected to the first terminalof the driving circuit, the second terminalof the second light-emitting control circuitis electrically connected to a first electrodeof the light-emitting element, and the second light-emitting control circuitis configured to apply a driving current to the light-emitting elementin response to the second light-emitting control signal EMand allow a reset signal VINI to be applied to the first terminalof the driving circuit. For example, in a light-emitting phase, the second light-emitting control circuitis turned on in response to the second light-emitting control signal EM, so that the driving circuitmay apply the driving current to the light-emitting elementthrough the second light-emitting control circuitto enable it to emit light.

1 FIG. 600 600 600 600 600 100 100 600 600 600 600 600 600 a b a a b For example, as shown in, the light-emitting elementincludes a first electrodeand a second electrode, the first electrodeof the light-emitting elementis electrically connected to the first terminalof the driving circuit, the second electrodeof the light-emitting elementis electrically connected to a second voltage terminal VSS to receive a second power supply voltage VSS, and the light-emitting elementis configured to emit light driven by the driving current. For example, the second voltage terminal VSS may be grounded, that is, the second power supply voltage VSS may be OV. For example, the second power supply voltage VSS may be a negative voltage. For example, the light-emitting elementmay use an Organic Light-Emitting Diode (OLED). In the embodiments described below, the light-emitting elementis taken as an OLED as an example. For example, the light-emitting elementmay also be an electroluminescent device of any other type, such as an inorganic light-emitting diodes, a quantum-dot light-emitting element, etc. The embodiments of the present disclosure do not limit the type of the light-emitting element.

1 FIG. 780 780 780 780 780 780 780 3 780 780 100 100 780 780 780 780 600 600 780 600 600 100 100 3 500 2 700 100 100 100 600 500 2 600 600 m a b c m a a b c a a a a As shown in, the reset control circuitincludes a control terminal, a first terminal, a second terminal, and a third terminal. The control terminalof the reset control circuitis configured to receive a reset control signal G, the first terminalof the reset control circuitis electrically connected to the first terminalof the driving circuit, the second terminalof the reset control circuitis electrically connected to the reset signal terminal VINI to receive the reset signal VINI, the third terminalof the reset control circuitis electrically connected to the first electrodeof the light-emitting element, and the reset control circuitis configured to apply the reset signal VINI to the first electrodeof the light-emitting elementand/or the first terminalof the driving circuitin response to the reset control signal G. For example, in a reset phase, the second light-emitting control circuitmay be turned on in response to the second light-emitting control signal EM, so that it may be combined with other circuit elements (for example, a reset circuitdescribed in the following embodiment) to allow the reset signal VINI to be applied to the first terminalof the driving circuit, thereby implementing a reset operation and other operations of the driving circuitand the light-emitting element. For example, in a compensation phase and a data writing phase, the second light-emitting control circuitis turned off in response to the second light-emitting control signal EM, and the reset signal VINI is applied to the first electrode of the light-emitting element, and the light-emitting elementmay be prevented from emitting light in this phase to meet a display requirement of the display apparatus. For example, the reset signal VINI may be the reset voltage VINI.

1 FIG. 780 780 100 100 780 780 780 600 600 100 600 600 100 100 10 a a b a a a As shown in, the first terminalof the reset control circuitis electrically connected to the first terminalof the driving circuit, and the second terminalof the reset control circuitis electrically connected to the reset signal terminal VINI. Thus, the reset signal from the reset signal terminal VINI needs to pass through the reset control circuitbefore it may be applied to the first electrodeof the light-emitting elementand/or the first terminal of the driving circuit, thereby reducing the impact of the fluctuation of the reset signal on the voltage of the first electrodeof the light-emitting elementand the first terminalof the driving circuit, and reducing the risk of introducing noise into the pixel circuit, thereby causing the driving current to be more stable to improve the display effect.

1 FIG. 780 700 800 600 600 100 100 700 800 780 780 a a For example, as shown in, the reset control circuitincludes a reset circuitand a second compensation circuit, and the reset signal VINI is applied to the first electrodeof the light-emitting elementand/or the first terminalof the driving circuitthrough the reset circuitand the second compensation circuit. For example, in some embodiments of the present disclosure, the reset control circuitmay also include other sub-circuits, and the embodiments of the present disclosure do not limit a specific structure of the reset control circuit.

1 FIG. 1 FIG. 2 FIG. 800 800 800 800 2 2 100 100 700 700 100 700 700 700 780 780 3 100 700 780 780 600 600 700 700 780 780 2 780 780 100 100 2 700 700 2 700 a b a m a b m m a c a b b a a a For example, as shown in, the second compensation circuitincludes a first terminaland a second terminal, the second compensation circuitincludes a second storage capacitor C, and the second storage capacitor Cis electrically connected between the first terminalof the driving circuitand the reset signal terminal VINI. For example, the reset circuitincludes a control terminal, a first terminal, and a second terminal. The control terminalof the reset circuitserves as the control terminalof the reset control circuitand is configured to receive the reset control signal G, the first terminalof the reset circuitserves as the third terminalof the reset control circuitand is electrically connected to the first electrodeof the light-emitting element, and the second terminalof the reset circuitserves as the second terminalof the reset control circuitand is electrically connected to the reset signal terminal VINI to receive the reset signal VINI. For example, in conjunction withand, a first electrode of the second storage capacitor Cserves as the first terminalof the reset control circuitand is electrically connected to the first terminalof the driving circuit, and a second electrode of the second storage capacitor Cis electrically connected to the first terminalof the reset circuit, so that in this solution, the second electrode of the second storage capacitor Cis indirectly electrically connected to the reset signal terminal VINI through the reset circuit.

2 700 700 700 700 700 700 700 2 600 600 101 a b b a a Because the second electrode of the second storage capacitor Cis connected to the first terminalof the reset circuitinstead of the second terminalof the reset circuit, the reset signal VINI needs to pass through the second terminaland the first terminalof the reset circuitin sequence before it may be applied to the second electrode of the second storage capacitor Cand the first electrodeof the light-emitting element, thereby reducing the risk of introducing noise into a pixel circuitbecause of the fluctuation of the reset signal VINI.

2 Of course, in some other embodiments of the present disclosure, the second electrode of the second storage capacitor Cmay also be directly electrically connected to the reset signal terminal VINI, so that a structural design form of the pixel circuit is more flexible, and the embodiments of the present disclosure are not limited thereto.

1 FIG. 10 200 400 For example, as shown in, the pixel circuitfurther includes a data writing circuitand a first light-emitting control circuit.

1 FIG. 200 200 200 200 200 200 1 200 200 200 200 1 200 100 100 1 200 1 100 100 200 m a b m a b m m For example, as shown in, the data writing circuitincludes a control terminal, a first terminaland a second terminal. The control terminalof the data writing circuitis configured to receive a data scanning signal G, the first terminalof the data writing circuitis electrically connected to a data signal terminal DATA to receive a data signal DATA, the second terminalof the data writing circuitis electrically connected to the first node N, and the data writing circuitis configured to write the data signal DATA to the control terminalof the driving circuitin response to the data scanning signal G. For example, in the data writing phase, the data writing circuitis turned on in response to the data scanning signal G, so that the data signal DATA may be written into the control terminalof the driving circuitthrough the data writing circuit.

1 FIG. 400 400 400 400 400 400 1 400 400 100 100 400 400 400 100 100 1 400 1 100 100 400 600 600 m a b m a b b b b b As shown in, the first light-emitting control circuitincludes a control terminal, a first terminal, and a second terminal. The control terminalof the first light-emitting control circuitis configured to receive a first light-emitting control signal EM, the first terminalof the first light-emitting control circuitis electrically connected to the second terminalof the driving circuit, the second terminalof the first light-emitting control circuitis electrically connected to a first voltage terminal ELVDD to receive a first power supply voltage ELVDD, and the first light-emitting control circuitis configured to apply the first power supply voltage ELVDD to the second terminalof the driving circuitin response to the first light-emitting control signal EM. For example, in the compensation phase, the first light-emitting control circuitmay be turned on in response to the first light-emitting control signal EM, so that the first power supply voltage ELVDD may be applied to the second terminalof the driving circuitthrough the first light-emitting control circuit. The second electrodeof the light-emitting elementreceives the second power supply voltage VSS, for example, the first power supply voltage ELVDD may be a high voltage, and the second power supply voltage VSS may be a low voltage, but the embodiments of the present disclosure are not limited thereto.

2 FIG. 1 FIG. 3 FIG. is a circuit diagram of an implementation example of the pixel circuit shown in; andis a signal timing diagram of a driving method provided by at least one embodiment of the present disclosure.

1 FIG. 2 FIG. 2 FIG. 101 1 2 3 4 5 1 2 1 2 3 4 5 For example, the pixel circuit shown inmay be implemented as a pixel circuit structure shown in. As shown in, the pixel circuitincludes: a driving transistor DT, a data writing transistor T, a first light-emitting control transistor T, a first compensation transistor T, a second light-emitting control transistor T, a reset transistor T, a first storage capacitor C, a second storage capacitor C, and a light-emitting element OLED. For example, the data writing transistor T, the first light-emitting control transistor T, the first compensation transistor T, the second light-emitting control transistor T, and the reset transistor Tare used as switching transistors. For example, the light-emitting element is an OLED, which may be of various types, such as a top emission type, a bottom emission type, etc., and may emit red light, green light, blue light or white light, etc. The embodiments of the present disclosure are not limited thereto.

1 FIG. 2 FIG. 100 100 100 1 100 100 2 2 100 100 m a b As shown inand, the driving circuitincludes a driving transistor DT, and a gate electrode of the driving transistor DT serves as the control terminalof the driving circuitand is electrically connected to the first node N. A first electrode of the driving transistor DT serves as the first terminalof the driving circuit, and is electrically connected to the first electrode of the second storage capacitor Cat the second node N. A second electrode of the driving transistor DT serves as the second terminalof the driving circuitand is electrically connected to the first voltage terminal ELVDD to receive the first power supply voltage ELVDD.

1 FIG. 2 FIG. 300 3 1 3 300 300 2 2 3 300 300 3 1 1 1 m a As shown inand, the first compensation circuitincludes a first compensation transistor Tand a first storage capacitor C. A gate electrode of the first compensation transistor Tserves as the control terminalof the first compensation circuitand is electrically connected to the first compensation control signal terminal Gto receive the first compensation control signal G. A first electrode of the first compensation transistor Tserves as the first terminalof the first compensation circuitand is electrically connected to the reference signal terminal REF to receive the reference signal REF; and a second electrode of the first compensation transistor Tis electrically connected to the first node N. A first electrode of the first compensation capacitor Cis electrically connected to the gate electrode of the driving transistor DT, and a second electrode of the first storage capacitor Cis electrically connected to the first electrode of the driving transistor DT.

1 FIG. 2 FIG. 500 4 4 2 2 4 100 100 4 600 600 a a For example, as shown inand, the second light-emitting control circuitincludes a second light-emitting control transistor T, and a gate electrode of the second light-emitting control transistor Tis electrically connected to the second light-emitting control terminal EMto receive the second light-emitting control signal EM. A first electrode of the second light-emitting control transistor Tis electrically connected to the first terminalof the driving circuit. A second electrode of the second light-emitting control transistor Tis electrically connected to the first electrodeof the light-emitting element.

1 FIG. 2 FIG. 700 5 5 3 3 5 2 100 100 5 a As shown inand, the reset circuitincludes a reset transistor T, and a gate electrode of the reset transistor Tis electrically connected to the reset control terminal Gto receive the reset control signal G. A first electrode of the reset transistor Tis electrically connected to the second electrode of the second storage capacitor Cand the first terminalof the driving circuit, and a second electrode of the reset transistor Tis electrically connected to the reset signal terminal VINI to receive the reset signal VINI.

1 FIG. 2 FIG. 5 100 100 5 100 100 4 a a As shown inand, in the pixel circuit provided by at least one embodiment of the present disclosure, the first electrode of the reset transistor Tis indirectly electrically connected to the first terminalof the driving circuit, that is, the first electrode of the reset transistor Tis electrically connected to the first terminalof the driving circuitthrough the second light-emitting control transistor T.

1 FIG. 2 FIG. 5 100 100 100 10 a As shown inand, the reset signal from the reset signal terminal VINI needs to pass through the first electrode and the second electrode of the reset transistor Tbefore it may be applied to the first electrode of the light-emitting element OLED and/or the first terminal of the driving circuit, thereby reducing the impact of the fluctuation of the reset signal on the voltage of the first electrode of the light-emitting element OLED and the first terminalof the driving circuit, and reducing the risk of introducing noise into the pixel circuit, so as to cause the driving current to be more stable to improve the display effect.

1 FIG. 2 FIG. 800 2 2 800 800 100 100 2 800 800 700 700 5 a a b a For example, as shown inand, the second compensation circuitincludes a second storage capacitor C, and a first electrode of the second storage capacitor Cserves as the first terminalof the second compensation circuitand is electrically connected to the first terminalof the driving circuit(i.e., the first electrode of the driving transistor DT). A second electrode of the second storage capacitor Cserves as the second terminalof the second compensation circuitand is electrically connected to the first terminalof the reset circuit(i.e., the first electrode of the reset transistor T).

2 5 5 2 600 600 5 101 a In a technical solution of this embodiment, because the second electrode of the second storage capacitor Cis electrically connected to the first electrode of the reset transistor Tinstead of the second electrode of the reset transistor T, the reset signal VINI is applied to the second electrode of the second storage capacitor Cand the first electrodeof the light-emitting elementthrough the second electrode and the first electrode of the reset transistor Tin sequence, thereby reducing the risk of introducing noise to the pixel circuitbecause of the fluctuation of the reset signal VINI.

1 FIG. 2 FIG. 200 1 1 1 1 1 1 1 For example, as shown inand, the data writing circuitincludes a data writing transistor T, a gate electrode of the data writing transistor Tis electrically connected to the data scanning signal terminal Gto receive the data scanning signal G, a first electrode of the data writing transistor Tis electrically connected to the data signal terminal DATA to receive the data signal DATA, and a second electrode of the data writing transistor Tis electrically connected to the first node N.

1 FIG. 2 FIG. 400 2 2 1 1 2 100 100 2 b For example, as shown inand, the first light-emitting control circuitincludes a first light-emitting control transistor T, a gate electrode of the first light-emitting control transistor Tis electrically connected to the first light-emitting control terminal EMto receive the first light-emitting control signal EM. A first electrode of the first light-emitting control transistor Tis electrically connected to the second terminalof the driving circuit. A second electrode of the first light-emitting control transistor Tis electrically connected to the first voltage terminal ELVDD to receive the first power supply voltage ELVDD.

1 2 3 1 2 1 2 3 It should be noted that in description of the embodiments of the present disclosure, the first node N, the second node Nand the third node Ndo not necessarily represent actual components but rather denote junctions of circuit connection in the circuit diagram. In the description of the embodiments of the present disclosure, the reference sign DATA may represent both the data signal terminal and the data signal; similarly, the reference sign Gmay represent both the data scanning signal terminal and the data scanning signal; the reference sign REF may represent both the reference signal terminal and the reference signal; the reference sign Gmay represent both the first compensation control signal terminal and the first compensation control signal; the reference sign EMmay represent both the first light-emitting control terminal and the first light-emitting control signal; the reference sign ELVDD may represent both the first voltage terminal and the first power supply voltage; the reference sign EMmay represent both the second light-emitting control terminal and the second light-emitting control signal; the reference sign Gmay represent both the reset control terminal and the reset control signal; the reference sign VINI may represent both the reset signal terminal and the reset signal, and may also represent the reset voltage; the reference sign VSS may represent both the second voltage terminal and the second power supply voltage. The same applies to subsequent embodiments and will not be repeated.

It should be noted that transistors used in the embodiments of the present disclosure may be thin-film transistors, field-effect transistors or other switching devices with same characteristics. The embodiments of the present disclosure are all described by taking thin-film transistors as examples. The source electrode and the drain electrode of the transistor used here may be symmetrical in structure, so the source electrode and the drain electrode may be structurally indistinguishable. In the embodiments of the present disclosure, in order to distinguish the two electrodes of the transistor other than the gate electrode, one of the electrodes is directly described as the first electrode and the other electrode is the second electrode.

In addition, the transistors may be divided into an N-type transistor and a P-type transistor according to characteristics of the transistors. When the transistor is a P-type transistor, a turn-on voltage is a low-level voltage (for example, 0V, −5V, −10V or other suitable voltages), and a turn-off voltage is a high-level voltage (for example, 5V, 10V or other suitable voltages). When the transistor is an N-type transistor, the turn-on voltage is a high-level voltage (for example, 5V, 10V or other suitable voltages), and the turn-off voltage is a low-level voltage (for example, 0V, −5V, −10V or other suitable voltages). However, the embodiments of the present disclosure do not limit the type of transistor. When the type of transistor changes, a connection relationship in the circuit may be adjusted accordingly.

101 1 2 3 4 2 FIG. 3 FIG. 3 FIG. An operating principle of the pixel circuitshown inis described below in conjunction with the signal timing diagram shown in. As shown in, a display process of each frame of an image includes four phases, namely, a reset phase, a compensation phase, a data writing phaseand a light-emitting phase.

101 1 2 3 4 5 2 FIG. For example, in the pixel circuitshown in, the driving transistor DT, the data writing transistor T, the first light-emitting control transistor T, the first compensation transistor T, the second light-emitting control transistor T, and the reset transistor Tare all N-type transistors. That is, a gate electrode of each transistor is turned on when a high-level signal is connected, and is turned off when a low-level signal is connected. Of course, in other embodiments, the above transistors may also be P-type transistors. The embodiments of the present disclosure do not limit the type of each transistor, which may be selected as needed. Here, the N-type transistors are taken as an example.

1 FIG. 3 FIG. 3 600 600 100 100 780 a a As shown into, an embodiment of the present disclosure provides a driving method, including: setting the reset control signal Gas an ON signal, so that the reset signal VINI is applied to the first electrodeof the light-emitting elementand/or the first terminalof the driving circuitthrough the reset control circuitin sequence.

1 FIG. 3 FIG. 100 100 780 3 100 100 a a For example, as shown into, the first terminalof the driving circuitis not directly connected to the reset signal terminal VINI, that is, the two are electrically connected through the reset control circuit. For example, when the reset control signal Gis an OFF signal, the first terminalof the driving circuitis disconnected from the reset signal terminal VINI.

In this way, the reset signal from the reset signal terminal needs to pass through the reset control circuit before it may be applied to the first electrode of the light-emitting element and/or the first terminal of the driving circuit, thereby reducing the impact of the fluctuation of the reset signal on the voltage of the first electrode of the light-emitting element and the first terminal of the driving circuit, reducing the risk of introducing noise into the pixel circuit, so as to cause the driving current to be more stable to improve the display effect.

1 FIG. 3 FIG. 1 3 700 700 700 2 100 100 600 600 700 700 700 1 1 a b a a b a For example, as shown into, in the reset phase, the driving method of the pixel circuit includes: setting the reset control signal Gas an ON signal in at least part of the time period so that the first terminaland the second terminalof the reset circuitare turned on, and the reset signal VINI is applied to the second electrode of the second storage capacitor C, the first terminalof the driving circuit, and the first electrodeof the light-emitting elementthrough the second terminaland the first terminalof the reset circuitin sequence, thereby implementing a reset operation. For example, the above at least part of the time period may be an entire time period of the reset phase, or may be a part of the time period in the reset phase, and the embodiments of the present disclosure are not limited thereto.

1 FIG. 3 FIG. 1 3 5 2 600 600 2 4 100 100 4 a a Correspondingly, as shown into, in the reset phase, the reset control signal Gis a high-level signal in the at least part of the time period to turn on the reset transistor T, so that the reset signal VINI may be applied to the second electrode of the second storage capacitor Cand the first electrodeof the light-emitting element. In this phase, the second light-emitting control signal EMis a high-level signal to turn on the second light-emitting control transistor T, and then the reset signal VINI is applied to the first terminalof the driving circuitthrough the second light-emitting control transistor T.

1 FIG. 3 FIG. 2 3 3 2 600 600 700 700 700 a b a For example, as shown into, in the compensation phaseand the data writing phase, the driving method of the pixel circuit includes: setting the reset control signal Gas an ON signal, and the reset signal VINI is applied to the second electrode of the second storage capacitor Cand the first electrodeof the light-emitting elementthrough the second terminaland the first terminalof the reset circuitin sequence.

1 FIG. 3 FIG. 2 3 3 5 2 4 2 600 600 a Correspondingly, as shown into, in the compensation phaseand the data writing phase, the reset control signal Gis a high-level signal in at least part of the time period to turn on the reset transistor. For example, the second light-emitting control signal EMis a low-level signal to turn off the second light-emitting control transistor T. Therefore, a voltage of the second electrode of the second storage capacitor Cand a voltage of the first electrodeof the light-emitting elementmay remain as a reset voltage VINI.

1 FIG. 3 FIG. 4 3 2 4 4 For example, as shown into, in the light-emitting phase, the driving method of the pixel circuit includes: setting the reset control signal Gas an OFF signal in at least part of the time period, so that the second electrode of the second storage capacitor Cis disconnected from the reset signal terminal VINI. For example, the above at least part of the time period may be an entire time period of the light-emitting phase, or may be a part of the time period in the light-emitting phase, and the embodiments of the present disclosure are not limited thereto.

1 FIG. 3 FIG. 4 3 5 2 Correspondingly, as shown into, in the light-emitting phase, the reset control signal Gis a low-level signal in at least part of the time period to turn off the reset transistor T, so that the second electrode of the second storage capacitor Cand the first electrode of the light-emitting element OLED are disconnected from the reset signal terminal VINI, so as to facilitate a voltage of the first electrode of the light-emitting element OLED to remain as a voltage when the light-emitting element OLED is in a light-emitting state.

1 FIG. 3 FIG. 3 101 780 600 600 2 3 600 600 2 100 100 100 100 101 a a a a In this way, as shown into, when the reset control signal Gis an ON signal, the reset signal VINI enters an interior of the pixel circuitthrough the reset control circuit, for example, it is applied to the first electrodeof the light-emitting elementand the second electrode of the second storage capacitor C. When the reset control signal Gis an OFF signal, the reset signal VINI is disconnected from the first electrodeof the light-emitting element, the second electrode of the second storage capacitor C, and the first terminalof the driving circuit. While an operating requirement of each phase is satisfied, the impact of the fluctuation of the reset signal VINI on the voltage of the first terminalof the driving circuitmay be reduced, and the risk of introducing noise into the pixel circuitmay be reduced, so as to cause the driving current to be more stable to improve the display effect.

3 FIG. 1 1 2 3 2 4 5 3 6 7 8 4 9 10 11 12 For example, as shown in, the reset phaseincludes a first sub-reset phase P, a second sub-reset phase Pand a third sub-reset phase Pwhich are performed in sequence. For example, the compensation phaseincludes a first sub-compensation phase Pand a second sub-compensation phase Pwhich are performed in sequence. For example, the data writing phaseincludes a first sub-data writing phase P, a second sub-data writing phase Pand a third sub-data writing phase Pwhich are performed in sequence. For example, the light-emitting phaseincludes a first sub-light-emitting phase P, a second sub-light-emitting phase P, a third sub-light-emitting phase Pand a fourth sub-light-emitting phase Pwhich are performed in sequence.

4 FIG.A 2 FIG. 4 FIG.B 2 FIG. 4 FIG.C 2 FIG. 4 FIG.D 2 FIG. 4 FIG.A 4 FIG.D is a schematic diagram of the pixel circuit inin a third sub-reset phase;is a schematic diagram of the pixel circuit inin a second sub-compensation phase;is a schematic diagram of the pixel circuit inin a third sub-data writing phase; andis a schematic diagram of the pixel circuit inin a fourth sub-light-emitting phase. In addition, transistors marked with dotted lines intoare all in an OFF state in a corresponding phase.

1 FIG. 3 FIG. 1 1010 100 100 b Step S: disconnecting the second terminalof the driving circuitfrom the first voltage terminal ELVDD; 1020 3 700 Step S: setting the reset control signal Gas an ON signal to turn on the reset circuit; and 1030 2 300 Step S: setting the first compensation control signal Gas an ON signal to turn on the first compensation circuit. Specifically, for example, as shown inand, in the reset phase, the driving method of the pixel circuit includes:

1 200 2 500 In the reset phase, the data scanning signal Gremains as an OFF signal to turn off the data writing circuit, and the second light-emitting control signal EMremains as an ON signal to turn on the second light-emitting control circuit.

1 FIG. 3 FIG. 1 1 200 2 500 2 3 300 700 1010 1 400 100 100 b For example, as shown inand, in the first sub-reset phase P, the data scanning signal Gremains as an OFF signal to turn off the data writing circuit; the second light-emitting control signal EMremains as an ON signal to turn off the second light-emitting control circuit; the first compensation control signal Gand the reset control signal Gboth remain as OFF signals, so that the first compensation circuitand the reset circuitare both in an OFF state; in addition, corresponding to the step S, the first light-emitting control signal EMis switched to an OFF signal to turn off the first light-emitting control circuit, so that the second terminalof the driving circuitis disconnected from the first voltage terminal ELVDD.

1 FIG. 3 FIG. 2 1 200 2 500 1 400 2 300 1020 3 700 2 600 600 100 100 a a For example, as shown inand, in the second sub-reset phase P, the data scanning signal Gremains as an OFF signal to turn off the data writing circuit; the second light-emitting control signal EMremains as an ON signal to turn on the second light-emitting control circuit; the first light-emitting control signal EMremains as an OFF signal to turn off the first light-emitting control circuit; the first compensation control signal Gremains as an OFF signal to cause the first compensation circuitto be in an OFF state; in addition, corresponding to the step S, the reset control signal Gis switched to an ON signal to turn on the reset circuit, so that the reset signal VINI may be applied to the second electrode of the second storage capacitor C, the first electrodeof the light-emitting elementand the first terminalof the driving circuit.

1 FIG. 3 FIG. 3 1 200 2 500 1 400 3 700 1030 2 300 100 100 m For example, as shown inand, in the third sub-reset phase P, the data scanning signal Gremains as an OFF signal to turn off the data writing circuit; the second light-emitting control signal EMremains as an ON signal to turn on the second light-emitting control circuit; the first light-emitting control signal EMremains as an OFF signal to turn off the first light-emitting control circuit; the reset control signal Gremains as an ON signal to turn on the reset circuit; in addition, corresponding to the step S, the first compensation control signal Gis switched to an ON signal to turn on the first compensation circuit, so that the reference signal REF may be applied to the control terminalof the driving circuit.

1 FIG. 3 FIG. 700 400 400 1 700 2 400 700 100 500 For example, as shown inand, by activating the reset circuitwhen the first light-emitting control circuitis turned off, that is, when the first light-emitting control circuitis turned off in the first sub-reset phase P, the reset circuitis turned on in the second sub-reset phase P, thereby preventing the first light-emitting control circuitfrom being turned on with the reset circuitthrough the driving circuitand the second light-emitting control circuit, so that the driving current may be more stable, which is beneficial to safety of the device.

2 FIG. 3 FIG. 1 1 1 2 4 2 3 3 5 1010 1 2 Correspondingly, as shown inand, in the first sub-reset phase P, the data scanning signal Gremains as a low-level signal to turn off the data writing transistor T; the second light-emitting control signal EMremains as a high-level signal to turn on the second light-emitting control transistor T; the first compensation control signal Gand the reset control signal Gboth remain as low-level signals, so that the first compensation transistor Tand the reset transistor Tare both in an ON state; in addition, corresponding to the step S, the first light-emitting control signal EMis switched to a low-level signal to turn off the first light-emitting control transistor T, so that the second electrode of the driving transistor DT is disconnected from the first voltage terminal ELVDD.

2 FIG. 3 FIG. 2 1 1 2 4 1 2 2 3 1020 3 5 2 Correspondingly, as shown inand, in the second sub-reset phase P, the data scanning signal Gremains as a low-level signal to turn off the data writing transistor T; the second light-emitting control signal EMremains as a high-level signal to turn on the second light-emitting control transistor T; the first light-emitting control signal EMremains as a low-level signal to turn off the first light-emitting control transistor T; the first compensation control signal Gremains as a low-level signal to turn off the first compensation transistor T; in addition, corresponding to the step S, the reset control signal Gis switched to a high-level signal to turn on the reset transistor T, so that the reset signal VINI may be applied to the second electrode of the second storage capacitor C, the first electrode of the light-emitting element OLED, and the first electrode of the driving transistor DT.

3 FIG. 4 FIG.A 3 1 1 2 4 1 2 3 5 1030 2 3 Correspondingly, as shown inand, in the third sub-reset phase P, the data scanning signal Gremains as a low-level signal to turn off the data writing transistor T; the second light-emitting control signal EMremains as a high-level signal to turn on the second light-emitting control transistor T; the first light-emitting control signal EMremains as a low-level signal to turn off the first light-emitting control transistor T; the reset control signal Gremains as a high-level signal to turn on the reset transistor T; in addition, corresponding to the step S, the first compensation control signal Gis switched to a high-level signal to turn on the first compensation transistor T, so that the reference signal REF may be applied to the gate electrode of the driving transistor DT.

3 FIG. 4 FIG.A 5 2 2 5 4 Therefore, as shown inand, the reset transistor Tis turned on when the first light-emitting control transistor Tis turned off, thereby preventing the first light-emitting control transistor Tfrom being turned on to the reset transistor Tthrough the driving transistor DT and the second light-emitting control transistor T, so that the driving current may be more stable, which is beneficial to the safety of the device.

3 FIG. 4 FIG.A REF INI REF INI 1 2 3 For example, as shown inand, the reference signal REF is a reference voltage, and a value thereof is V; the reset signal VINI is a reset voltage, and a value thereof is V. A difference between a voltage value of the gate electrode of the driving transistor DT and a voltage value of the first electrode of the driving transistor DT is a gate-source voltage Vgs, and a threshold voltage of the driving transistor DT is Vth. When steps in the first sub-reset phase P, the second sub-reset phase P, and the third sub-reset phase Pare completed, Vgs≥Vth, that is, V−V≥Vth. For example, when Vgs>Vth, the driving transistor DT is in an ON state.

1 2 3 1 2 3 1 2 3 It should be noted that the steps corresponding to the first sub-reset phase P, the second sub-reset phase Pand the third sub-reset phase Pare performed in sequence, so that the driving current in the pixel circuit can be well controlled, but the embodiments of the present disclosure are not limited thereto. For example, in some embodiments, the steps corresponding to at least two of the first sub-reset phase P, the second sub-reset phase Pand the third sub-reset phasemay be performed synchronously. For example, the steps corresponding to the first sub-reset phase P, the second sub-reset phase Pand the third sub-reset phase Pmay be performed synchronously, and the embodiments of the present disclosure are not limited thereto.

1 FIG. 3 FIG. 2 2010 2 500 1 400 Step S: setting the second light-emitting control signal EMas an OFF signal to turn off the second light-emitting control circuit, and setting the first light-emitting control signal EMas an OFF signal to turn off the first light-emitting control circuit; and 2020 1 400 2 Step S: setting the first light-emitting control signal EMas an ON signal to turn on the first light-emitting control circuit, and keeping the second light-emitting control signal EMas an OFF signal. For example, as shown inand, in the compensation phase, the driving method of the pixel circuit includes:

2 1 200 2 300 3 700 For example, in the compensation phase, the data scanning signal Gremains as an OFF signal to keep the data writing circuitturned off, the first compensation control signal Gremains as an ON signal to keep the first compensation circuitturned on, and the reset control signal Gis an ON signal to turn on the reset circuit.

1 FIG. 3 FIG. 4 1 200 2 3 300 700 1 400 2010 2 500 For example, as shown inand, in the first sub-compensation phase P, the data scanning signal Gremains as an OFF signal to turn off the data writing circuit; the first compensation control signal Gand the reset control signal Gboth remain as ON signals, so that the first compensation circuitand the reset circuitare both in an ON state; the first light-emitting control signal EMremains as an OFF signal to turn off the first light-emitting control circuit; in addition, corresponding to the step S, the second light-emitting control signal EMis switched to an OFF signal to turn off the second light-emitting control circuit.

1 FIG. 3 FIG. 5 1 200 2 3 300 700 2 500 2020 1 400 For example, as shown inand, in the second sub-compensation phase P, the data scanning signal Gremains as an OFF signal to turn off the data writing circuit; the first compensation control signal Gand the reset control signal Gboth remain as ON signals, so that the first compensation circuitand the reset circuitare both in the ON state; the second light-emitting control signal EMremains as an OFF signal to turn off the second light-emitting control circuit; in addition, corresponding to the step S, the first light-emitting control signal EMis switched to an ON signal to turn on the first light-emitting control circuit.

1 FIG. 3 FIG. 500 4 5 400 5 700 400 700 100 500 For example, as shown inand, when the second light-emitting control circuitis turned off in the first sub-compensation phase Pand remains turned off in the second sub-compensation phase P, the first light-emitting control circuitis turned on in the second sub-compensation phase P, so that when the reset circuitis in the ON state, the first light-emitting control circuitmay be prevented from being turned on to the reset circuitthrough the driving circuitand the second light-emitting control circuit, so that the driving current may be more stable, which is beneficial to the safety of the device.

2 FIG. 3 FIG. 4 1 1 2 3 3 5 1 2 2010 2 4 Correspondingly, as shown inand, in the first sub-compensation phase P, the data scanning signal Gremains as an OFF signal to turn off the data writing transistor T; the first compensation control signal Gand the reset control signal Gboth remain as ON signals, so that the first compensation transistor Tand the reset transistor Tare both in an ON state; the first light-emitting control signal EMremains as an OFF signal to turn off the first light-emitting control transistor T; in addition, corresponding to the step S, the second light-emitting control signal EMis switched to an OFF signal to turn off the second light-emitting control transistor T.

3 FIG. 4 FIG.B 5 1 1 2 3 3 5 2 4 2020 1 2 Correspondingly, as shown inand, in the second sub-compensation phase P, the data scanning signal Gremains as an OFF signal to turn off the data writing transistor T; the first compensation control signal Gand the reset control signal Gboth remain as ON signals, so that the first compensation transistor Tand the reset transistor Tare both in the ON state; the second light-emitting control signal EMremains as an OFF signal to turn off the second light-emitting control transistor T; in addition, corresponding to the step S, the first light-emitting control signal EMis switched to an ON signal to turn on the first light-emitting control transistor T, so that the first power supply voltage ELVDD is applied to the second electrode of the driving transistor DT.

2 FIG. 3 FIG. 4 FIG.B 4 4 5 2 5 5 2 5 4 For example, as shown in,and, when the second light-emitting control transistor Tis turned off in the first sub-compensation phase Pand remains turned off in the second sub-compensation phase P, the first light-emitting control transistor Tis turned on in the second sub-compensation phase P. Therefore, when the reset transistor Tis in the ON state, the first light-emitting control transistor Tmay be prevented from being turned on to the reset transistor Tthrough the driving transistor DT and the second light-emitting control transistor T, so that the driving current may be more stable, which is beneficial to the safety of the device.

3 FIG. 4 FIG.B 2 4 5 REF For example, as shown inand, at a beginning of the compensation phase, the voltage value of the first electrode of the driving transistor DT is equal to a value of the reset voltage Vini, and Vgs−Vth>0. When the steps in the first sub-compensation phase Pand the second sub-compensation phase Pare completed, the voltage value of the gate electrode of the driving transistor DT is V, and the voltage of the second electrode of the driving transistor DT is the first power supply voltage ELVDD. Because the value of the first power supply voltage ELVDD is greater than the voltage value of the first electrode of the driving transistor DT (that is, Vini), the driving transistor DT may be charged by the first power supply voltage ELVDD until the driving transistor DT is turned off, so that a voltage value Vs of the first electrode of the driving transistor DT is equal to Vref−Vth.

4 5 4 5 It should be noted that the steps corresponding to the first sub-reset phase Pand the second sub-compensation phase Pare performed in sequence so that the driving current in the pixel circuit can be well controlled, but the embodiments of the present disclosure are not limited thereto. For example, in some embodiments, the steps corresponding to the first sub-reset phase Pand the second sub-compensation phase Pmay also be performed synchronously, and the embodiments of the present disclosure are not limited thereto.

1 FIG. 3 FIG. 3 3010 2 300 100 Step S: setting the first compensation control signal Gas an OFF signal to turn off the first compensation circuit, and keeping the second terminal of the driving circuitreceiving the first power supply voltage ELVDD; 3020 1 400 100 Step S: setting the first light-emitting control signal EMas an OFF signal to turn off the first light-emitting control circuit, so that the second terminal of the driving circuitis disconnected from the first voltage terminal ELVDD; and 3030 1 200 Step S: setting the data scanning signal Gas an ON signal to turn on the data writing circuit. For example, as shown inand, in the data writing phase, the driving method of the pixel circuit includes:

3 2 500 3 700 In the data writing phase, the second light-emitting control signal EMremains as an OFF signal to keep the second light-emitting control circuitturned off, and the reset control signal Gremains as an ON signal to keep the reset circuitturned on.

1 FIG. 3 FIG. 6 1 200 1 400 100 2 500 3 700 3010 2 300 100 100 m For example, as shown inand, in the first sub-data writing phase P, the data scanning signal Gremains as an OFF signal to turn off the data writing circuit; the first light-emitting control signal EMremains as an ON signal to turn on the first light-emitting control circuit, so that the second terminal of the driving circuitcontinues to receive the first power supply voltage ELVDD; the second light-emitting control signal EMremains as an OFF signal to turn off the second light-emitting control circuit; the reset control signal Gremains as an ON signal, so that the reset circuitis in the ON state; in addition, corresponding to the step S, the first compensation control signal Gis switched to an OFF signal to turn off the first compensation circuit, so that the reference signal REF stops being applied to the control electrodeof the driving circuit.

1 FIG. 3 FIG. 7 1 200 2 500 3 700 2 300 3020 1 400 100 For example, as shown inand, in the second sub-data writing phase P, the data scanning signal Gremains as an OFF signal to turn off the data writing circuit; the second light-emitting control signal EMremains as an OFF signal to turn off the second light-emitting control circuit; the reset control signal Gremains as an ON signal to keep the reset circuitin the ON state; the first compensation control signal Gis an OFF signal to turn off the first compensation circuit; in addition, corresponding to the step S, the first light-emitting control signal EMis switched to an OFF signal to turn off the first light-emitting control circuit, so that the second terminal of the driving circuitstops receiving the first power supply voltage ELVDD.

1 FIG. 3 FIG. 8 2 500 3 700 2 300 1 400 3030 1 200 100 100 m For example, as shown inand, in the third sub-data writing phase P, the second light-emitting control signal EMremains as an OFF signal to turn off the second light-emitting control circuit; the reset control signal Gremains as an ON signal, so that the reset circuitis in the ON state; the first compensation control signal Gis an OFF signal to turn off the first compensation circuit; the first light-emitting control signal EMremains as an OFF signal to turn off the first light-emitting control circuit; in addition, corresponding to the step S, the data scanning signal Gis switched to an ON signal to turn on the data writing circuit, so that the data signal DATA is applied to the control electrodeof the driving circuit.

1 FIG. 3 FIG. 8 6 300 200 200 100 100 300 100 100 m m For example, as shown inand, a step corresponding to the third sub-data writing phase Pis performed after a step corresponding to the first sub-data writing phase P, that is, after the first compensation circuitis turned off, the data writing circuitis turned on. By adopting this driving method, it is possible to avoid the data writing circuitapplying the data signal DATA to the control terminalof the driving circuitwhile the first compensation circuitapplies the reference signal REF to the control terminalof the driving circuit, so that a controlling manner of the driving circuit is more reliable and the driving current is more stable.

2 FIG. 3 FIG. 6 1 1 1 2 2 4 3 5 3010 2 3 Correspondingly, as shown inand, in the first sub-data writing phase P, the data scanning signal Gremains as an OFF signal to turn off the data writing transistor T; the first light-emitting control signal EMremains as an ON signal to turn on the first light-emitting control transistor T, so that the second electrode of the driving transistor DT continues to receive the first power supply voltage ELVDD; the second light-emitting control signal EMremains as an OFF signal to turn off the second light-emitting control transistor T; the reset control signal Gremains as an ON signal, so that the reset transistor Tis in the ON state; in addition, corresponding to the step S, the first compensation control signal Gis switched to an OFF signal to turn off the first compensation transistor T.

2 FIG. 3 FIG. 7 1 1 2 4 3 5 2 3 3020 1 2 Correspondingly, as shown inand, in the second sub-data writing phase P, the data scanning signal Gremains as an OFF signal to turn off the data writing transistor T; the second light-emitting control signal EMremains as an OFF signal to turn off the second light-emitting control transistor T; the reset control signal Gremains as an ON signal to turn on the reset transistor T; and the first compensation control signal Gremains as an OFF signal to turn off the first compensation transistor T. In addition, corresponding to the step S, the first light-emitting control signal EMis switched to an OFF signal to turn off the first light-emitting control transistor T, thereby disconnecting the second electrode of the driving transistor DT from the first power supply voltage terminal ELVDD.

3 FIG. 4 FIG.C 8 2 4 3 5 2 3 1 2 3030 1 1 Correspondingly, as shown inand, in the third sub-data writing phase P, the second light-emitting control signal EMremains as an OFF signal to turn off the second light-emitting control transistor T; the reset control signal Gremains as an ON signal to turn on the reset transistor T; the first compensation control signal Gremains as an OFF signal to turn off the first compensation transistor T; the first light-emitting control signal EMremains as an OFF signal to turn off the first light-emitting control transistor T, so that the second electrode of the driving transistor DT is disconnected from the first power supply voltage terminal ELVDD. In addition, corresponding to the step S, the data scanning signal Gis switched to an ON signal to turn on the data writing transistor T, so that the data signal DATA is written into the gate electrode of the driving transistor DT.

2 FIG. 3 FIG. 4 FIG.C 3 6 1 1 3 For example, as shown in,and, after the first compensation transistor Tis turned off in the first sub-data writing phase P, the data writing transistor Tis turned on. By adopting this driving method, it is possible to avoid the data writing transistor Tapplying the data signal DATA to the gate electrode of the driving transistor DT while the first compensation transistor Tapplies the reference signal REF to the gate electrode of the driving transistor DT, so that a controlling manner of the driving circuit is more reliable and the driving current is more stable.

3 FIG. 4 FIG.C 6 7 8 1 1 1 2 1 2 For example, as shown inand, after the steps in the first sub-data writing phase P, the second sub-data writing phase Pand the third sub-data writing phase Pare completed, the voltage value of the gate electrode of the driving transistor DT and the voltage value of the first electrode of the first storage capacitor Care both equal to a value Vdata of the data voltage DATA, and the voltage value of the first electrode of the driving transistor DT is Vref−Vth+C/(C+C)×(Vdata−Vref). Here, for clarity, a capacitance value of the first storage capacitor and the first storage capacitor use a same reference sign C, and a capacitance value of the second storage capacitor and the second storage capacitor use a same reference sign C.

6 7 8 6 7 8 6 7 8 It should be noted that the steps corresponding to the first sub-data writing phase P, the second sub-data writing phase P, and the third sub-data writing phase Pare performed in sequence so that the driving current in the pixel circuit can be well controlled, but the embodiments of the present disclosure are not limited thereto. For example, in some embodiments, the steps corresponding to at least two of the first sub-data writing phase P, the second sub-data writing phase P, and the third sub-data writing phase Pmay be performed synchronously. For example, the steps corresponding to the first sub-data writing phase P, the second sub-data writing phase P, and the third sub-data writing phase Pmay be performed synchronously, and the embodiments of the present disclosure do not limit this.

2 FIG. 3 FIG. 4 101 1 200 Step S: setting the data scanning signal Gas an OFF signal to turn off the data writing circuit; 102 2 500 1 400 Step S: setting the second light-emitting control signal EMas an ON signal to turn on the second light-emitting control circuit, and keeping the first light-emitting control signal EMas an OFF signal to turn off the first light-emitting control circuit; 103 3 700 Step S: setting the reset control signal Gas an OFF signal to turn off the reset circuit; 104 1 400 100 100 400 b Step S: setting the first light-emitting control signal EMas an ON signal to turn on the first light-emitting control circuit, so that the second terminalof the driving circuitreceives the first power supply voltage ELVDD through the first light-emitting control circuit. For example, as shown inand, in the light-emitting phase, the driving method of the pixel circuit includes:

4 2 300 In the light-emitting phase, the first compensation control signal Gremains as an OFF signal to turn off the first compensation circuit.

1 FIG. 3 FIG. 9 1 400 2 500 2 300 3 700 101 1 200 200 100 100 m For example, as shown inand, in the first sub-light-emitting phase P, the first light-emitting control signal EMis an OFF signal to turn off the first light-emitting control circuit; the second light-emitting control signal EMis an OFF signal to turn off the second light-emitting control circuit; the first compensation control signal Gis an OFF signal to turn off the first compensation circuit; the reset control signal Gis an ON signal to turn on the reset circuit. In addition, corresponding to the step S, the data scanning signal Gis switched to an OFF signal to turn off the data writing circuit, so that the data writing circuitstops applying the data signal DATA to the control terminalof the driving circuit.

1 FIG. 3 FIG. 10 1 400 2 300 3 700 1 200 102 2 500 For example, as shown inand, in the second sub-light-emitting phase P, the first light-emitting control signal EMis an OFF signal to turn off the first light-emitting control circuit; the first compensation control signal Gis an OFF signal to turn off the first compensation circuit; the reset control signal Gis an ON signal to turn on the reset circuit; the data scanning signal Gis an OFF signal to turn off the data writing circuit. In addition, corresponding to the step S, the second light-emitting control signal EMis switched to an ON signal to turn on the second light-emitting control circuit.

1 FIG. 3 FIG. 11 1 400 2 300 1 200 2 500 103 3 700 For example, as shown inand, in the third sub-light-emitting phase P, the first light-emitting control signal EMis an OFF signal to turn off the first light-emitting control circuit; the first compensation control signal Gis an OFF signal to turn off the first compensation circuit; the data scanning signal Gis an OFF signal to turn off the data writing circuit; the second light-emitting control signal EMis an ON signal to turn on the second light-emitting control circuit. In addition, corresponding to the step S, the reset control signal Gis switched to an OFF signal to turn off the reset circuit.

1 FIG. 3 FIG. 12 2 300 1 200 2 500 3 700 104 1 400 For example, as shown inand, in the fourth sub-light-emitting phase P, the first compensation control signal Gis an OFF signal to turn off the first compensation circuit; the data scanning signal Gis an OFF signal to turn off the data writing circuit; the second light-emitting control signal EMis an ON signal to turn on the second light-emitting control circuit; the reset control signal Gis an OFF signal to turn off the reset circuit. In addition, corresponding to the step S, the first light-emitting control signal EMis switched to an ON signal to turn on the first light-emitting control circuit.

1 FIG. 3 FIG. 4 FIG.D 12 10 500 100 100 600 600 2 100 100 1 1 1 100 100 100 12 400 600 600 100 100 600 600 100 100 a a a m a a a For example, as shown inand, the step corresponding to the fourth sub-light-emitting phase Pis performed after the step corresponding to the second sub-light-emitting phase P. For example, when the second light-emitting control circuitis turned on, the voltage of the first terminalof the driving circuit, the voltage of the first electrodeof the light-emitting element, and the voltage of the second electrode of the second storage capacitor Care all reset voltage VINI, the voltage value of the first terminalof the driving circuithas a first variation, and the voltage of the first electrode of the first storage capacitor Calso has the first variation. Because a voltage between the two electrodes of the first storage capacitor Cwill not change suddenly, the voltage of the second electrode of the first storage capacitor C(that is, the voltage of the control terminalof the driving circuit) will also produce the above-first variation accordingly, so that the gate-source voltage Vgs of the driving transistor DT (as shown in) in the driving circuitremains unchanged. Then, in the fourth sub-light-emitting phase P, the first light-emitting control circuitis turned on to allow the light-emitting elementto emit light. By adopting this driving method, when the light-emitting elementemits light, a voltage difference between the first terminalof the driving circuitand the first electrodeof the light-emitting elementmay be eliminated, so as to reduce a risk of voltage jump at the first terminalof the driving circuit.

2 FIG. 3 FIG. 9 1 2 2 4 2 3 3 5 101 1 1 100 100 m Correspondingly, as shown inand, in the first sub-light-emitting phase P, the first light-emitting control signal EMis an OFF signal to turn off the first light-emitting control transistor T; the second light-emitting control signal EMis an OFF signal to turn off the second light-emitting control transistor T; the first compensation control signal Gis an OFF signal to turn off the first compensation transistor T; the reset control signal Gis an ON signal to turn on the reset transistor T. In addition, corresponding to the step S, the data scanning signal Gis switched to an OFF signal to turn off the data writing transistor T, so that the data signal DATA stops being applied to the control terminalof the driving circuit.

2 FIG. 3 FIG. 10 1 2 2 3 3 5 1 1 102 2 4 Correspondingly, as shown inand, in the second sub-light-emitting phase P, the first light-emitting control signal EMis an OFF signal to turn off the first light-emitting control transistor T; the first compensation control signal Gis an OFF signal to turn off the first compensation transistor T; the reset control signal Gis an ON signal to turn on the reset transistor T; the data scanning signal Gis an OFF signal to turn off the data writing transistor T. In addition, corresponding to the step S, the second light-emitting control signal EMis switched to an ON signal to turn on the second light-emitting control transistor T.

2 FIG. 3 FIG. 11 1 2 2 3 1 1 2 4 103 3 5 Correspondingly, as shown inand, in the third sub-light-emitting phase P, the first light-emitting control signal EMis an OFF signal to turn off the first light-emitting control transistor T; the first compensation control signal Gis an OFF signal to turn off the first compensation transistor T; the data scanning signal Gis an OFF signal to turn off the data writing transistor T; the second light-emitting control signal EMis an ON signal to turn on the second light-emitting control transistor T. In addition, corresponding to the step S, the reset control signal Gis switched to an OFF signal to turn off the reset transistor T.

3 FIG. 4 FIG.D 12 2 3 1 1 2 4 3 5 104 1 2 Correspondingly, as shown inand, in the fourth sub-light-emitting phase P, the first compensation control signal Gis an OFF signal to turn off the first light-emitting control transistor T; the data scanning signal Gis an OFF signal to turn off the data writing transistor T; the second light-emitting control signal EMis an ON signal to turn on the second light-emitting control transistor T; the reset control signal Gis an OFF signal to turn off the reset transistor T. In addition, corresponding to the step S, the first light-emitting control signal EMis switched to an ON signal to turn on the first light-emitting control transistor T.

2 FIG. 3 FIG. 4 FIG.D 12 10 4 2 1 1 12 3 For example, as shown in,and, the step corresponding to the fourth sub-light-emitting phase Pis performed after the step corresponding to the second sub-light-emitting phase P. For example, when the second light-emitting control transistor Tis turned on, the voltage of the first electrode of the driving transistor DT, the voltage of the first electrode of the light-emitting element OLED, and the voltage of the second electrode of the second storage capacitor Care all reset voltage VINI, the voltage value of the first electrode of the driving transistor DT has a first variation, and the voltage of the first electrode of the first storage capacitor Calso has the first variation, and then the voltage of the second electrode of the first storage capacitor C(that is, the voltage of the gate electrode of the driving transistor DT) will also produce the above first variation accordingly, so that the gate-source voltage Vgs of the driving transistor DT remains unchanged. Then, in the fourth sub-light-emitting phase P, the first light-emitting control transistor Tis turned on to allow the light-emitting element OLED to emit light. By adopting this driving method, when the light-emitting element OLED emits light, the voltage difference between the first electrode of the driving transistor DT and the first electrode of the light-emitting element OLED may be eliminated to reduce the risk of voltage jump of the first electrode of the driving transistor DT.

3 FIG. 4 FIG.D 9 10 11 12 1 1 2 1 1 1 2 1 1 2 For example, as shown inand, when the steps in the first sub-light-emitting phase P, the second sub-light-emitting phase P, the third sub-light-emitting phase Pand the fourth sub-light-emitting phase Pare completed, because the voltage value of the first electrode of the driving transistor DT is Vini, a variation thereof is ΔV=Vini−[Vref−Vth+(Vdata−Vref)×C/(C+C)], so that the voltage value of the gate electrode of the driving transistor DT and the voltage value of the first electrode of the first storage capacitor Care both equal to Vdata−[Vref−Vth+C/(C+C)×(Vdata−Vref)−Vini], and the gate-source voltage Vgs of the driving transistor DT is Vdata−Vref+Vth−C/(C+C)×(Vdata−Vref).

2 I=K×(Vgs−Vth), where K is a conductivity coefficient of the driving transistor DT. A value I of the driving current flowing through the light-emitting element may be obtained according to a formula below:

That is:

I=K V V C C C 2 ×[(data−ref)×2/(1+2)]

According to the above formula, the value I of the driving current flowing through the light-emitting element is no longer related to the threshold voltage Vth of the driving transistor, so that compensation for the pixel circuit may be implemented, the problem of a drift of the threshold voltage Vth caused by a technological process and long-term operation of the driving transistor can be solved, and its impact on the driving current can be eliminated, thereby improving the display effect of the display apparatus using the pixel circuit.

5 FIG. 6 FIG. 5 FIG. 7 FIG.A 5 FIG. 7 FIG.B 5 FIG. 7 FIG.C 5 FIG. 7 FIG.D 5 FIG. 7 FIG.A 7 FIG.D is a schematic diagram of another pixel circuit provided by an embodiment of the present disclosure;is a signal timing diagram corresponding to the pixel circuit shown in;is a schematic diagram of the pixel circuit inin a third sub-reset phase;is a schematic diagram of the pixel circuit inin a second sub-compensation phase;is a schematic diagram of the pixel circuit inin a third sub-data writing phase;is a schematic diagram of the pixel circuit inin a fourth sub-light-emitting phase. In addition, transistors marked with dotted lines intoare all in an OFF state in a corresponding phase.

5 FIG. 2 FIG. 2 FIG. 102 101 1 3 102 For example, as shown in, a difference between the pixel circuitand the pixel circuitshown inis that the data transistor Tand the first compensation transistor Tare different in terms of structure. For other structures in the pixel circuit, please refer to a relevant description ofin the above embodiment, which will not be repeated here.

101 1 3 1 2 1 1 3 2 1 3 2 FIG. For example, in the pixel circuitshown in, the data writing transistor Tand the first compensation transistor Tare transistors controlled independently of each other, the data scanning signal terminal Gand the first compensation control signal terminal Gare different signal terminals independent of each other, and the data signal terminal DATA and the reference signal terminal REF are different signal terminals independent of each other. For example, the data writing transistor Tis turned on or off under control of the data scanning signal G, the first compensation transistor Tis turned on or off under control of the first compensation control signal G, and the data writing transistor Tand the first compensation transistor Tare controlled independently.

5 FIG. 1 3 1 2 1 For example, as shown in, the data writing transistor Talso serves the first compensation transistor T, the data scanning signal Galso serves the first compensation control signal G, the first electrode of the data writing transistor Tis also electrically connected to the reference signal terminal REF to receive the reference signal REF, the data signal terminal DATA also serves the reference signal terminal REF, and is configured to provide the data signal DATA or the reference signal REF in different time periods respectively.

6 FIG. 2 FIG. 3 FIG. 6 FIG. 102 101 1 2 3 2 1 For example, as shown in, during a driving process of the pixel circuit, an operating state (for example, the ON or OFF state) of each transistor is same as that of the pixel circuitshown in. Compared with the timing diagram shown in, timing states of the first light-emitting control signal EM, the second light-emitting control signal EMand the reset control signal Gin the timing diagram inremain unchanged, except that a timing distribution of the first compensation control signal Gis omitted, and a timing state of the data scanning signal Gis different.

6 FIG. 7 FIG.A 1 2 1 1 3 1 1 1 For example, as shown inand, in the first sub-reset phase Pand the second sub-reset phase P, the data scanning signal Gis an OFF signal so that the data writing transistor Tis in the OFF state. In the third sub-reset phase P, the data scanning signal Gis an ON signal so that the data writing transistor Tis in the ON state, and the first electrode of the data writing transistor Tis electrically connected to the reference signal terminal REF to receive the reference signal REF, and the reference signal REF is applied to the gate electrode of the driving transistor DT.

6 FIG. 7 FIG.B 4 5 1 1 1 For example, as shown inand, in the first sub-compensation phase Pand the second sub-compensation phase P, the data scanning signal Gremains as an ON signal so that the data writing transistor Tis in the ON state, and the first electrode of the data writing transistor Tis electrically connected to the reference signal terminal REF to receive the reference signal REF, and the reference signal REF is applied to the gate electrode of the driving transistor DT.

6 FIG. 7 FIG.C 6 7 1 1 8 1 1 1 For example, as shown inand, in the first sub-data writing phase Pand the second sub-data writing phase P, the data scan signal Gis an OFF signal so that the data writing transistor Tis in the OFF state. In the third sub-data writing phase P, the data scanning signal Gis an ON signal to turn on the data writing transistor T, and the first electrode of the data writing transistor Tis electrically connected to the data signal terminal DATA to receive the data signal DATA, and the data signal DATA is applied to the gate electrode of the driving transistor DT.

6 FIG. 7 FIG.D 4 1 1 For example, as shown inand, in the light-emitting phase, the data scanning signal Gis an OFF signal so that the data writing transistor Tis in the OFF state.

As described above, by allowing the data writing transistor multiplexed as the first compensation transistor, the data signal terminal may receive different signals in different operating phases, so as to simplify a structure of the pixel circuit while satisfying an operating requirement of the pixel circuit and causing a controlling manner thereof to be more flexible.

8 FIG. is a schematic block diagram of another pixel circuit provided by at least one embodiment of the present disclosure.

8 FIG. 1 FIG. 1 FIG. 10 20 400 20 For example, as shown in, compared with the pixel circuitshown in, the pixel circuitis different in that the first light-emitting control circuitis removed. For other structures in the pixel circuit, please refer to a relevant description ofin the above embodiment, which will not be repeated here.

8 FIG. 100 100 100 For example, as shown in, the second terminal of the driving circuitis directly electrically connected to the first voltage terminal ELVDD to receive the first power supply voltage ELVDD, that is, no other transistors or capacitors are provided between the second terminal of the driving circuitand the first voltage terminal ELVDD, and the second terminal of the driving circuitis electrically connected to the first voltage terminal ELVDD through a wire.

9 FIG. 8 FIG. 10 FIG. 9 FIG. 11 FIG.A 9 FIG. 11 FIG.B 9 FIG. 11 FIG.C 9 FIG. 11 FIG.D 9 FIG. 11 FIG.A 11 FIG.D is a circuit diagram of an implementation example of the pixel circuit shown in;is a signal timing diagram corresponding to the pixel circuit shown in;is a schematic diagram of the pixel circuit shown inin a third sub-reset phase;is a schematic diagram of the pixel circuit shown inin a second sub-compensation phase;is a schematic diagram of the pixel circuit shown inin a third sub-data writing phase; andis a schematic diagram of the pixel circuit shown inin a fourth sub-light-emitting phase. In addition, transistors marked with dotted lines intoare all in an OFF state in a corresponding phase.

9 FIG. 1 FIG. 103 101 2 For example, as shown in, a difference between the pixel circuitand the pixel circuitshown inis that the first light-emitting control transistor Tis omitted, and other structures are the same.

9 FIG. 10 FIG. 2 FIG. 3 FIG. 10 FIG. 103 101 1 For example, as shown inand, in a driving process of the pixel circuit, an operating state (for example, the ON or OFF state) of each transistor is same as the pixel circuitshown in. Compared with the timing diagram shown in, a timing distribution corresponding to the first light-emitting control signal EMis omitted in the timing diagram shown in.

10 FIG. 11 FIG.A 3 1 1 2 4 3 5 2 3 For example, as shown inand, in the third sub-reset phase P, the data scanning signal Gremains as a low-level signal to turn off the data writing transistor T; the second light-emitting control signal EMis a high-level signal to turn on the second light-emitting control transistor T; the reset control signal Gis a high-level signal, so that the reset transistor Tis in the ON state; the first compensation control signal Gis a high-level signal to turn on the first compensation transistor T. Because the gate-source voltage Vgs of the driving transistor DT is greater than its threshold voltage Vth in this phase, the driving transistor DT is in the ON state. In addition, the second terminal of the driving transistor DT receives the first power supply voltage ELVDD, so that the driving transistor DT is charged.

10 FIG. 11 FIG.B 5 1 200 2 3 300 700 2 500 For example, as shown inand, in the second sub-compensation phase P, the data scanning signal Gremains as an OFF signal to turn off the data writing circuit; the first compensation control signal Gand the reset control signal Gare both ON signals, so that the first compensation circuitand the reset circuitare both in an ON state; the second light-emitting control signal EMremains as an OFF signal to turn off the second light-emitting control circuit. The first power supply voltage ELVDD charges the driving transistor DT until the driving transistor DT is turned off, and the voltage value Vs at the first electrode of the driving transistor DT is equal to Vref−Vth.

10 FIG. 11 FIG.C 8 2 4 3 5 2 3 1 1 For example, as shown inand, in the third sub-data writing phase P, the second light-emitting control signal EMis an OFF signal to turn off the second light-emitting control transistor T; the reset control signal Gis an ON signal, so that the reset transistor Tis in the ON state; the first compensation control signal Gis an OFF signal to turn off the first compensation transistor T; the data scanning signal Gis switched to an ON signal to turn on the data writing transistor T, so that the data signal DATA is written into the gate electrode of the driving transistor DT. In addition, the second terminal of the driving transistor DT receives the first power supply voltage ELVDD, so that the driving transistor DT is charged.

10 FIG. 11 FIG.D 12 2 3 1 1 2 4 3 5 For example, as shown inand, in the fourth sub-light-emitting phase P, the first compensation control signal Gis an OFF signal to turn off the first light-emitting control transistor T; the data scanning signal Gis an OFF signal to turn off the data writing transistor T; the second light-emitting control signal EMis an ON signal to turn on the second light-emitting control transistor T; the reset control signal Gis an OFF signal to turn off the reset transistor T; the second terminal of the driving transistor DT keeps receiving the first power supply voltage ELVDD, so that the light-emitting element OLED emits light.

10 FIG. 11 FIG.C 8 103 103 For example, as shown inand, mobility of the driving transistor is positively correlated with temperature, that is, when the temperature rises, the mobility increases; and the driving current is positively correlated with the gate-source voltage Vgs of the driving circuit. In the third sub-data writing phase P, when the data signal DATA is written into the gate electrode of the driving transistor DT and the driving transistor DT is charged, for example, when the temperature of the pixel circuitis high, the mobility is large, and accordingly, the voltage at the first electrode of the driving transistor DT may be high within a certain charging time, so that the gate-source voltage Vgs of the driving transistor DT is small, and thus the driving current is not too large. For example, when the temperature of the pixel circuitis low, the mobility is small, and accordingly, the voltage at the first electrode of the driving transistor DT may be low within a certain charging time, so that the gate-source voltage Vgs of the driving transistor DT is large, and thus the driving current is not too small.

8 2 Therefore, in the third sub-data writing phase P, by removing the first light-emitting control transistor T(that is, removing the first light-emitting control circuit), the second electrode of the driving transistor DT continues to receive the first power supply voltage ELVDD, the mobility of the driving transistor DT at different temperatures may be compensated to reduce the impact of temperature change on the driving current in the pixel circuit.

4 FIG.E 4 FIG.E 3 FIG. 1 8 is a signal timing diagram of another driving method provided by at least one embodiment of the present disclosure. For example, a difference between the signal timing diagram shown inand the signal timing diagram shown inis that a timing distribution of the first light-emitting control signal EMin the third sub-data writing phase Pis different, and timing distributions of the other signals are the same.

2 FIG. 5 FIG. 3030 For example, for some pixel circuits provided by the embodiments of the present disclosure, such as the pixel circuit inand the pixel circuit inmentioned above, the step Sin the driving method of the pixel circuit further includes: setting the first light-emitting control signal as an ON signal to turn on the first light-emitting control circuit, so that the second terminal of the driving circuit receives the first power supply voltage.

1 FIG. 4 FIG.E 8 1 200 1 400 100 100 2 500 3 700 2 300 b For example, as shown inand, in the third sub-data writing phase P, when the data scanning signal Gis an ON signal to turn on the data writing circuit, the first light-emitting control signal EMis an ON signal to turn on the first light-emitting control circuit, so that the second terminalof the driving circuitreceives the first power supply voltage ELVDD; the second light-emitting control signal EMremains as an OFF signal to turn off the second light-emitting control circuit; the reset control signal Gremains as an ON signal, so that the reset circuitis in the ON state; the first compensation control signal Gis an OFF signal to turn off the first compensation circuit.

4 FIG.C 4 FIG.E 1 1 1 2 100 100 2 4 3 5 2 3 b Accordingly, as shown inand, in the third sub-data writing phase, the data scanning signal Gis switched to an ON signal to turn on the data writing transistor T, so that the data signal DATA is written into the gate electrode of the driving transistor DT; the first light-emitting control signal EMis switched to an ON signal to turn on the first light-emitting control transistor T, and the first power supply voltage ELVDD is applied to the second terminalof the driving circuit; and the second light-emitting control signal EMremains as an OFF signal to turn off the second light-emitting control transistor T; the reset control signal Gremains as an ON signal, so that the reset transistor Tis in the ON state; the first compensation control signal Gremains as an OFF signal to turn off the first compensation transistor T.

In this way, when the temperature of the pixel circuit is high, the mobility is large, and accordingly, the voltage of the first electrode of the driving transistor may be made higher, so that the gate-source voltage Vgs of the driving transistor DT is small, and the driving current is not too large. On the contrary, when the temperature of the pixel circuit is low, the mobility is low, and accordingly, the voltage at the first electrode of the driving transistor may be low, so that the gate-source voltage Vgs of the driving transistor is large, and the driving current is not too small.

2 Therefore, in the third sub-data writing phase, by omitting the first light-emitting control transistor Tand causing the second electrode of the driving transistor to continue to receive the first power supply voltage, the mobility of the driving transistor DT at different temperatures may be compensated to reduce the impact of temperature change on the driving current in the pixel circuit.

12 FIG. 13 FIG. 12 FIG. 14 FIG.A 12 FIG. 14 FIG.B 12 FIG. 14 FIG.C 12 FIG. 14 FIG.A 14 FIG.C is a schematic diagram of another pixel circuit provided by an embodiment of the present disclosure;is a signal timing diagram corresponding to the pixel circuit shown in;is a schematic diagram of the pixel circuit inin a second sub-compensation phase;is a schematic diagram of the pixel circuit inin a third sub-data writing phase; andis a schematic diagram of the pixel circuit inin a fourth sub-light-emitting phase. In addition, transistors marked with dotted lines intoare all in an OFF state in a corresponding phase.

12 FIG. 9 FIG. 9 FIG. 104 103 1 3 104 For example, as shown in, a difference between the pixel circuitand the pixel circuitshown inis that the data transistor Tand the first compensation transistor Tare different in terms of structure. For other structures in the pixel circuit, please refer to a relevant description ofin the above embodiment, which will not be repeated here.

103 1 3 1 2 1 1 3 2 1 3 9 FIG. For example, in the pixel circuitshown in, the data writing transistor Tand the first compensation transistor Tare transistors controlled independently of each other, the data scanning signal terminal Gand the first compensation control signal terminal Gare different signal terminals independent of each other, and the data signal terminal DATA and the reference signal terminal REF are different signal terminals independent of each other. For example, the data writing transistor Tis turned on or off under control of the data scanning signal G, the first compensation transistor Tis turned on or off under control of the first compensation control signal G, and the data writing transistor Tand the first compensation transistor Tare controlled independently.

12 FIG. 9 FIG. 1 3 1 2 1 For example, as shown in, the data writing transistor Talso serves the first compensation transistor T, the data scanning signal Galso serves the first compensation control signal G(see), the first electrode of the data writing transistor Tis also electrically connected to the reference signal terminal REF to receive the reference signal REF, the data signal terminal DATA also serves the reference signal terminal REF, and is configured to provide the data signal DATA or the reference signal REF in different time periods.

13 FIG. 9 FIG. 10 FIG. 13 FIG. 104 103 2 3 2 1 For example, as shown in, during a driving process of the pixel circuit, an operating state (for example, the ON or OFF state) of each transistor is same as that of the pixel circuitshown in. Compared with the timing diagram shown in, timing states of the second light-emitting control signal EMand the reset control signal Gin the timing diagram inremain unchanged, except that a timing distribution of the first compensation control signal Gis omitted, and a timing state of the data scanning signal Gis different.

13 FIG. 12 FIG. 1 2 1 1 3 1 1 1 For example, as shown inand, in the first sub-reset phase Pand the second sub-reset phase P, the data scanning signal Gis an OFF signal so that the data writing transistor Tis in the OFF state. In the third sub-reset phase P, the data scanning signal Gis an ON signal so that the data writing transistor Tis in the ON state, and the first electrode of the data writing transistor Tis electrically connected to the reference signal terminal REF to receive the reference signal REF, and the reference signal REF is applied to the gate electrode of the driving transistor DT.

13 FIG. 14 FIG.A 4 5 1 1 1 For example, as shown inand, in the first sub-compensation phase Pand the second sub-compensation phase P, the data scanning signal Gremains as an ON signal so that the data writing transistor Tis in the ON state, and the first electrode of the data writing transistor Tis electrically connected to the reference signal terminal REF to receive the reference signal REF, and the reference signal REF is applied to the gate electrode of the driving transistor DT.

13 FIG. 14 FIG.B 6 7 1 1 8 1 1 1 For example, as shown inand, in the first sub-data writing phase Pand the second sub-data writing phase P, the data scanning signal Gis an OFF signal so that the data writing transistor Tis in the OFF state. In the third sub-data writing phase P, the data scanning signal Gis an ON signal to turn on the data writing transistor T, and the first electrode of the data write transistor Tis electrically connected to the data signal terminal DATA to receive the data signal DATA, and the data signal DATA is applied to the gate electrode of the driving transistor DT.

13 FIG. 14 FIG.C 4 1 1 For example, as shown inand, in the light-emitting phase, the data scanning signal Gis an OFF signal so that the data writing transistor Tis in the OFF state.

104 12 FIG. 9 FIG. As described above, by allowing the data writing transistor to be multiplexed as the first compensation transistor, the data signal terminal may receive different signals in different operating phases, so as to simplify the structure of the pixel circuit while satisfying an operating requirement of the pixel circuit and causing a controlling manner thereof to be more flexible. For other structures and technical effects of the pixel circuitshown in, please refer to the relevant description ofin the above embodiment, which will not be repeated here.

15 FIG. is a schematic block diagram of another pixel circuit provided by at least one embodiment of the present disclosure.

15 FIG. 1 FIG. 1 FIG. 10 30 900 30 For example, as shown in, compared with the pixel circuitshown in, the pixel circuitdiffers in that an auxiliary compensation circuitis added. For other structures in the pixel circuit, please refer to the relevant description ofin the above embodiment, which will not be repeated here.

15 FIG. 18 FIG.A 30 900 900 900 3 900 900 2 500 500 700 700 900 900 600 600 m a b a b a For example, as shown inand, the pixel circuitincludes an auxiliary compensation circuit, a control terminalof the auxiliary compensation circuitis configured to receive an auxiliary compensation signal EM, a first terminalof the auxiliary compensation circuitis electrically connected to the second electrode of the second storage capacitor C, the second terminalof the second light-emitting control circuit, and the first terminalof the reset circuit, and a second terminalof the auxiliary compensation circuitis electrically connected to the first electrodeof the light-emitting element.

16 FIG. 15 FIG. 17 FIG. 18 FIG.A 15 FIG. 18 FIG.B 15 FIG. 18 FIG.C 15 FIG. 18 FIG.D 15 FIG. 18 FIG.A 18 FIG.D is a circuit diagram of an implementation example of the pixel circuit shown in;is a signal timing diagram of another driving method provided by at least one embodiment of the present disclosure;is a schematic diagram of the pixel circuit shown inin a third sub-reset phase;is a schematic diagram of the pixel circuit shown inin a second sub-compensation phase;is a schematic diagram of the pixel circuit shown inin a third sub-data writing phase;is a schematic diagram of the pixel circuit shown inin a fourth sub-light-emitting phase. In addition, transistors marked with dotted lines intoare all in an OFF state in a corresponding phase.

16 FIG. 2 FIG. 2 FIG. 105 101 6 105 For example, as shown in, a difference between the pixel circuitand the pixel circuitshown inis that an auxiliary compensation transistor Tis added. For other structures and technical effects in the pixel circuit, please refer to the relevant description ofin the above embodiment, which will not be repeated here.

16 FIG. 15 FIG. 900 6 6 3 3 6 2 4 6 600 600 6 4 6 3 3 3 2 6 105 a For example, as shown in, the auxiliary compensation circuit(see) includes an auxiliary compensation transistor T, a gate electrode of the auxiliary compensation transistor Tis electrically connected to an auxiliary compensation control terminal EMto receive an auxiliary compensation control signal EM, a first electrode of the auxiliary compensation transistor Tis electrically connected to the second electrode of the second storage capacitor Cand the second electrode of the second light-emitting control transistor T, and a second electrode of the auxiliary compensation transistor Tis electrically connected to the first electrodeof the light-emitting element. For example, the gate electrode of the auxiliary compensation transistor Tand the gate electrode of the second light-emitting control transistor Tare independent of each other and are not electrically connected. For example, the auxiliary compensation transistor Tis turned on or off under control of the auxiliary compensation control signal EM, the auxiliary compensation control terminal EMis an independent control terminal, and the auxiliary compensation control signal EMand the second light-emitting control signal EMare different signals. For example, the auxiliary compensation transistor Tmay be an N-type transistor, and a type thereof may be same or different from types of other transistors in the pixel circuit, and the embodiments of the present disclosure do not limit this.

17 FIG. 2 FIG. 3 FIG. 17 FIG. 105 101 3 For example, as shown in, during a driving process of the pixel circuit, an operating state (for example, the ON or OFF state) of each transistor is same as the pixel circuitshown in. Compared with the timing diagram shown in, a timing distribution of the auxiliary compensation control signal EMis added to the timing diagram in.

17 FIG. 18 FIG.D 1 2 4 3 6 6 7 3 6 7 3 For example, as shown into, in the reset phase, the compensation phase, and the light-emitting phase, the auxiliary compensation control signal EMis an ON signal, so that the auxiliary compensation transistor Tis in an ON state. For example, in the first sub-data writing phase Pand the second sub-data writing phase P, the auxiliary compensation control signal EMis an ON signal, but the embodiments of the present disclosure are not limited thereto. For example, in some embodiments, in the first sub-data writing phase Pand the second sub-data writing phase P, the auxiliary compensation control signal EMmay also be an OFF signal.

17 FIG. 18 FIG.C 8 3 6 6 2 For example, as shown inand, in the third sub-data writing phase P, the auxiliary compensation control signal EMis an OFF signal, so that the auxiliary compensation transistor Tis in an OFF state. Because the light-emitting element OLED has a capacitor, and when the auxiliary compensation transistor Tis turned on, the capacitor in the light-emitting element OLED is connected in series with the second storage capacitor C.

17 FIG. 18 FIG.C 8 1 6 2 2 Therefore, as shown inand, in the third sub-data writing phase P, when the data writing transistor Tis turned on and the data signal DATA is written into the gate electrode of the driving transistor DT, the auxiliary compensation transistor Tis turned off, so that the impact of the capacitance in the light-emitting element OLED on the voltage of the second terminal of the second storage capacitor Cmay be reduced, so that the voltage value of the second terminal of the second storage capacitor Cis equal to the value of the reset voltage Vini, and the voltage of the first terminal of the driving transistor DT may be caused to be more stable.

19 FIG. 20 FIG. 19 FIG. 21 FIG. is a schematic block diagram of another pixel circuit provided by at least one embodiment of the present disclosure.is a circuit diagram of an implementation example of the pixel circuit shown in;is a signal timing diagram of another driving method provided by at least one embodiment of the present disclosure.

19 FIG. 15 FIG. 15 FIG. 30 40 900 900 40 m For example, as shown in, compared with the pixel circuitshown in, a pixel circuitdiffers in that a connection manner of the control electrodeof the auxiliary compensation circuitis different. For other structures in the pixel circuit, please refer to a relevant description ofin the above embodiment, which will not be repeated here.

20 FIG. 6 4 6 4 2 3 6 4 2 6 4 2 2 6 4 2 For example, as shown in, the gate electrode of the auxiliary compensation transistor Tis electrically connected to the gate electrode of the second light-emitting control transistor T, the auxiliary compensation transistor Tand the second light-emitting control transistor Tshare a gate electrode, the second light-emitting control signal EMis used as the auxiliary compensation control signal EM, and a type of the auxiliary compensation transistor Tis same as a type of the second light-emitting control transistor T. Therefore, when the second light-emitting control signal EMis an ON signal, the auxiliary compensation transistor Tand the second light-emitting control transistor Tare both turned on in response to the second light-emitting control signal EM; when the second light-emitting control signal EMis an OFF signal, the auxiliary compensation transistor Tand the second light-emitting control transistor Tare both turned off in response to the second light-emitting control signal EM.

22 FIG.A 20 FIG. 22 FIG.B 20 FIG. 22 FIG.C 20 FIG. 22 FIG.D 20 FIG. is a schematic diagram of the pixel circuit inin a third sub-reset phase;is a schematic diagram of the pixel circuit inin a second sub-compensation phase;is a schematic diagram of the pixel circuit inin a third sub-data writing phase; andis a schematic diagram of the pixel circuit inin a fourth sub-light-emitting phase.

21 FIG. 22 FIG.A 1 2 6 4 6 For example, as shown inand, in the reset phase, the second light-emitting control signal EMis a high-level signal, and the auxiliary compensation transistor Tand the second light-emitting control transistor Tare both in an ON state, so that the reset signal VINI may be applied to the first terminal of the light-emitting element OLED through the auxiliary compensation transistor T.

21 FIG. 22 FIG.B 2 2 6 4 For example, as shown inand, in the compensation phase, the second light-emitting control signal EMis a low-level signal, and the auxiliary compensation transistor Tand the second light-emitting control transistor Tare both in an OFF state to prevent the light-emitting element OLED from emitting light in this phase.

21 FIG. 22 FIG.C 3 2 6 4 2 For example, as shown inand, in the data writing phase, the second light-emitting control signal EMis a low-level signal, the auxiliary compensation transistor Tand the second light-emitting control transistor Tare both in the OFF state, and the voltage value of the second electrode of the second storage capacitor Cis equal to the reset voltage value Vini, so that the voltage of the first electrode of the driving transistor DT may be more stable.

21 FIG. 22 FIG.D 9 1 8 1 8 2 6 4 For example, as shown inand, in the first sub-light-emitting phase P, the data scanning signal Gis switched from a high-level signal in the third sub-data writing phase Pto a low-level signal, and the data writing transistor Tis switched from the ON state in the third sub-data writing phase Pto the OFF state, so that the gate electrode of the driving transistor DT stops receiving the data signal DATA. The second light-emitting control signal EMremains a low-level signal, and the auxiliary compensation transistor Tand the second light-emitting control transistor Tare both in the OFF state.

6 4 2 6 1 2 In this way, the auxiliary compensation transistor Tand the second light-emitting control transistor Tmay be controlled by the second light-emitting control signal EM, which may simplify the pixel structure and cause the driving method to be more convenient. In the meantime, a risk of the auxiliary compensation transistor Tbeing in the ON state may be reduced during a process of the data writing transistor Tswitching to the OFF state, thereby causing the voltage at the second electrode of the second storage capacitor Cto be stable.

23 FIG. 24 FIG. 23 FIG. 25 FIG. is a schematic block diagram of another pixel circuit provided by at least one embodiment of the present disclosure.is a circuit diagram of an implementation example of the pixel circuit shown in; andis a signal timing diagram of another driving method provided by at least one embodiment of the present disclosure.

23 FIG. 15 FIG. 15 FIG. 30 50 900 50 For example, as shown in, compared with the pixel circuitshown in, a pixel circuitdiffers in that a connection manner of the auxiliary compensation circuitis different. For other structures of the pixel circuit, please refer to the relevant description ofin the above embodiment, which will not be repeated here.

23 FIG. 50 900 900 900 3 900 900 2 700 700 900 900 600 600 500 500 900 900 3 900 m a a b a b m For example, as shown in, the pixel circuitincludes an auxiliary compensation circuit, the control terminalof the auxiliary compensation circuitis configured to receive the auxiliary compensation signal EM, the first terminalof the auxiliary compensation circuitis electrically connected to the second electrode of the second storage capacitor Cand the first terminalof the reset circuit, and the second terminalof the auxiliary compensation circuitis electrically connected to the first electrodeof the light-emitting elementand the second terminalof the second light-emitting control circuit. For example, the control terminalof the auxiliary compensation circuitmay be an independent control terminal, and the auxiliary compensation signal EMis an independent control signal to control activation or deactivation of the auxiliary compensation circuit, but the embodiments of the present disclosure are not limited thereto.

23 FIG. 24 FIG. 16 FIG. 107 105 6 For example, as shown inand, a difference between a pixel circuitand a pixel circuitshown inis that a connection manner of the auxiliary compensation transistor Tis different. For other structures and technical effects, please refer to relevant description of the above embodiments, which will not be repeated here.

23 FIG. 24 FIG. 900 6 6 3 3 6 2 5 6 600 600 4 a For example, as shown inand, the auxiliary compensation circuitincludes an auxiliary compensation transistor T, a gate electrode of the auxiliary compensation transistor Tis electrically connected to an auxiliary compensation control terminal EMto receive an auxiliary compensation control signal EM, a first electrode of the auxiliary compensation transistor Tis electrically connected to the second electrode of the second storage capacitor Cand the first electrode of the reset transistor T, and a second electrode of the auxiliary compensation transistor Tis electrically connected to the first electrodeof the light-emitting elementand the second electrode of the second light-emitting control transistor T.

24 FIG. 6 5 6 5 3 3 6 5 3 6 5 3 3 6 5 3 For example, as shown in, the gate electrode of the auxiliary compensation transistor Tis electrically connected to the gate electrode of the reset transistor T, the auxiliary compensation transistor Tand the reset transistor Tshare a gate electrode, the reset control signal Gis used as the auxiliary compensation control signal EM, and a type of the auxiliary compensation transistor Tis same as a type of the reset transistor T. For example, when the reset control signal Gis an ON signal, the auxiliary compensation transistor Tand the reset transistor Tare both turned on in response to the reset control signal G; when the reset control signal Gis an OFF signal, the auxiliary compensation transistor Tand the reset transistor Tare both turned off in response to the reset control signal G.

26 FIG.A 24 FIG. 26 FIG.B 24 FIG. 26 FIG.C 24 FIG. 26 FIG.D 24 FIG. is a schematic diagram of the pixel circuit inin a third sub-reset phase;is a schematic diagram of the pixel circuit inin a second sub-compensation phase;is a schematic diagram of the pixel circuit inin a third sub-data writing phase; andis a schematic diagram of the pixel circuit inin a fourth sub-light-emitting phase.

25 FIG. 26 FIG.A 1 1 12 3 4 6 5 107 2 3 3 6 5 For example, as shown inand, in the first sub-reset phase P, the first light-emitting control signal EMis switched from a high-level signal in the fourth sub-light-emitting phase Pto a low-level signal, and the reset control signal Gremains as a low-level signal, thereby avoiding a risk of forming a current path from the second electrode of the driving transistor DT, through the second light-emitting control transistor Tand the auxiliary compensation transistor T, and then to the second electrode of the reset transistor Tin this phase, thereby improving a device safety in the driving circuit. In the second sub-reset phase Pand the third sub-reset phase P, the reset control signal Gis switched to a high-level signal to turn on the auxiliary compensation transistor Tand the reset transistor T, so that the reset voltage may be applied to the first electrode of the light-emitting element OLED.

25 FIG. 26 FIG.B 26 FIG.C 2 3 3 6 5 2 For example, as shown in,and, in the compensation phaseand the data writing phase, the reset control signal Gremains as a high-level signal, so that the auxiliary compensation transistor Tand the reset transistor Tare both in the ON state, so that a voltage at the second electrode of the second storage capacitor Cremains as a reset voltage.

25 FIG. 26 FIG.D 9 10 3 6 5 11 12 3 6 5 9 10 11 1 2 12 1 For example, as shown inand, in the first sub-light-emitting phase Pand the second sub-light-emitting phase P, the reset control signal Gremains a high-level signal, so that the auxiliary compensation transistor Tand the reset transistor Tare both in the ON state. In the third sub-light-emitting phase Pand the fourth sub-light-emitting phase P, the reset control signal Gis a low-level signal, so that the auxiliary compensation transistor Tand the reset transistor Tare both in the OFF state. In the first sub-light-emitting phase P, the second sub-light-emitting phase Pand the third sub-light-emitting phase P, the first light-emitting control signal EMis a low-level signal, so that the first light-emitting control transistor Tis in the OFF state; in the fourth sub-light-emitting phase P, the first light-emitting control signal EMis switched to a high-level signal, so that the first power supply voltage ELVDD is applied to the second electrode of the driving transistor DT, and the light-emitting element OLED is in a light-emitting state.

By providing an auxiliary compensation transistor between the first electrode of the light-emitting element and the second electrode of the second storage capacitor, the impact of the capacitance of the light-emitting element on the voltage of the second electrode of the second storage capacitor may be reduced, so that the voltage of the second electrode of the second storage capacitor is more stable, and the voltage of the first electrode of the driving transistor is more stable.

6 2 5 6 600 600 4 6 5 6 4 1 6 2 2 a For example, in some embodiments, when the first electrode of the auxiliary compensation transistor Tis electrically connected to the second electrode of the second storage capacitor Cand the first electrode of the reset transistor T, and the second electrode of the auxiliary compensation transistor Tis electrically connected to the first electrodeof the light-emitting elementand the second electrode of the second light-emitting control transistor T, the gate electrode of the auxiliary compensation transistor Tand the gate electrode of the reset transistor Tmay also be independent of each other and not electrically connected. For example, the auxiliary compensation transistor Tmay also share a gate electrode with the second light-emitting control transistor T. In this way, when the data writing transistor Tis turned on and the data signal DATA is written into the gate electrode of the driving transistor DT, the auxiliary compensation transistor Tis turned off to reduce the impact of the capacitance in the light-emitting element OLED on the voltage of the second terminal of the second storage capacitor C, so that the voltage value of the second terminal of the second storage capacitor Cis equal to the value Vini of the reset voltage, and the voltage of the first terminal of the driving transistor DT may be more stable.

6 2 5 6 600 600 4 6 6 a For example, in some embodiments of the present disclosure, when the first electrode of the auxiliary compensation transistor Tis electrically connected to the second electrode of the second storage capacitor Cand the first electrode of the reset transistor T, and the second electrode of the auxiliary compensation transistor Tis electrically connected to the first electrodeof the light-emitting elementand the second electrode of the second light-emitting control transistor T, the gate electrode of the auxiliary compensation transistor Tmay be an independent electrode, and the embodiments of the present disclosure do not limit a setting manner of the gate electrode of the auxiliary compensation transistor T.

An embodiment of the present disclosure further provides a method for reducing impact of temperature change on a magnitude of a driving current.

3 FIG. 4 FIG.A 1 2 2 5 2 For example, as shown inand, after the reset phaseis completed, when the compensation phaseis entered, the voltage of the first electrode of the driving transistor DT is the reset voltage VINI. In the compensation phase, for example, in the second sub-compensation phase P, the first light-emitting control transistor Tis turned on, so that the driving transistor DT is charged until the driving transistor DT is turned off, thereby causing the gate-source voltage Vgs of the driving transistor DT to be equal to a threshold voltage Vth thereof, that is, causing the voltage of the first electrode of the driving transistor DT to be Vs=Vref−Vth.

3 FIG. 4 FIG.A However, in some cases, as shown inand, the pixel circuit may be interfered by some factors during an actual operation. For example, a charging time of the driving transistor DT may be insufficient, which may cause the driving transistor DT not to be completely turned off, and the voltage Vs of the first electrode of the driving transistor DT is less than a theoretical value Vref−Vth derived above, so that the driving current in the light-emitting phase is small. In addition, for the pixel circuit using an oxide material, a luminous brightness of the light-emitting element may be affected by temperature change, which is mainly due to mobility of an oxide transistor changing with temperature. For example, when the temperature rises, the mobility of the oxide transistor will increase accordingly, which will cause the driving current to increase; conversely, when the temperature decreases, the mobility of the oxide transistor will decrease accordingly, which will cause the driving current to increase. Therefore, when the compensation phase is completed, the voltage value of the first electrode of the driving transistor DT is crucial to the luminous brightness of the light-emitting element.

101 2 FIG. It should be noted that the method for reducing the impact of temperature change on the driving current provided in the embodiment of the present disclosure is applicable to the pixel circuit provided in the embodiment of the present disclosure, and the pixel circuitshown inis taken as an example for explanation below.

27 FIG. is a schematic diagram of a reset voltage changing with temperature in at least one embodiment of the present disclosure.

For example, in at least one embodiment of the present disclosure, a value of the reset signal is adjustable. For example, the reset signal is a non-constant signal, which may be adjusted according to an operating requirement of the pixel circuit. For example, the reset signal may be a DC signal or may be a non-DC signal.

4 FIG.A For example, as shown in, the reset signal VINI is a reset voltage. The method for reducing the impact of temperature change on the driving current provided by the embodiment of the present disclosure includes: as an ambient temperature of the pixel circuit increases, setting the reset voltage Vini to increase accordingly.

For example, the reset signal VINI includes at least a first reset signal and a second reset signal, the first reset signal corresponds to a first display temperature, the second reset signal corresponds to a second display temperature, the first display temperature is lower than the second display temperature, and a value of the first reset signal is less than a value of the second reset signal. For example, when the temperature of the pixel circuit increases from the first display temperature to the second display temperature, the value of the reset signal increases from the value of the first reset signal to the value of the second reset signal.

4 FIG.A 27 FIG. 1 2 102 1 2 2 For example, as shown inand, the value of the first reset signal may be Vini, the value of the second reset signal may be Vini, the first display temperature may be 30° C., and the second display temperature may be 60° C. For example, when the temperature of the pixel circuitincreases, for example, from the first display temperature to the second display temperature, the value of the reset voltage may increase accordingly, that is, from Vinito Vini. Thus, when the reset phase is completed, the voltage value of the first electrode of the driving transistor DT may be increased to Viniaccordingly.

4 FIG.B 1 1 2 2 2 1 1 2 For example, as shown in, before charging, when an initial value of the voltage of the first electrode of the driving transistor DT is Vini, after a charging time D, the voltage value of the first electrode of the driving transistor DT is Vs. For example, when the initial value of the voltage of the first electrode of the driving transistor DT is Vini, after the charging time D, the voltage value of the first electrode of the driving transistor DT is Vs, where Vsis greater than Vs. Moreover, when the compensation phase is completed, and when the driving transistor DT is not completely turned off (for example, because of the aforementioned insufficient charging time, etc.), the voltage value of the first electrode of the driving transistor DT (that is, Vsand Vs) is less than Vref-Vth.

4 FIG.C 4 FIG.D 1 1 1 2 2 1 1 2 1 1 1 2 2 1 1 2 For example, as shown in, when the data writing phase is completed, the voltage value of the first electrode of the driving transistor DT increases from Vs+(Vdata−Vref)×C/(C+C) to Vs+ (Vdata−Vref)×C/(C+C). Thus, as shown in, when entering the light-emitting phase, because the gate voltage value of the driving transistor DT is Vdata, the gate-source voltage Vgs of the driving transistor DT drops from Vdata−[Vs+(Vdata−Vref)×C/(C+C)] to Vdata−[Vs+(Vdata−Vref)×C/(C+C)].

2 I=K×(Vgs−Vth), where K is a conductivity coefficient of the driving transistor DT. A value I of the driving current flowing through the light-emitting element may be obtained according to a formula below:

That is, when the gate-source voltage Vgs of the driving transistor DT decreases, the value I of the driving current will decrease.

Therefore, when the temperature of the pixel circuit increases, the mobility of the driving transistor will increase, thereby increasing the driving current. By increasing the reset voltage, an increase of the driving current may be suppressed, and the magnitude of the driving current in the pixel circuit can be within a reasonable range, so that the driving current is more stable.

Table 1 shows a data distribution between the reset voltage and the driving current in the embodiments of the present disclosure. For example, as shown in Table 1, in the compensation phase, when the charging time of the driving transistor is 50 μs, when the reset voltage increases from 1.2V to 1.4V, the voltage value Vs of the second electrode of the driving transistor increases from 1.711V to 1.739V, and the stable driving current in the light-emitting phase decreases from 72.4 nA to 70.3 nA. When the reset voltage increases from 1.4V to 1.6V, the voltage value of the second electrode of the driving transistor increases from 1.739V to 1.784V, and the stable driving current in the light-emitting phase decreases from 70.3 nA to 67.3 nA. It can be seen that increasing the reset voltage can effectively suppress the increase of the driving current in the light-emitting phase.

TABLE 1 When charging time is Stable driving current in the Vini(V) 50 μs, Vs(V) light-emitting phase(nA) 1.2 1.711 72.4 1.4 1.739 70.3 1.6 1.784 67.3

28 FIG. is a schematic diagram of brightness of a light-emitting element changing with grayscale in at least one embodiment of the present disclosure.

28 FIG. 1 2 3 1 2 3 For example, as shown in, a curve Lrepresents a curve of change between the brightness and the grayscale of the light-emitting element at 30° C.; a curve Land a curve Lrepresent curves of change between the brightness and the grayscale of the light-emitting element at 50° C., and reset voltage values corresponding to the curve Land the curve Lare equal, and are both less than a reset voltage value corresponding to the curve L.

28 FIG. 1 2 1 3 For example, as shown in, by comparing the curve Land the curve L, it can be seen that when the temperature of the pixel circuit increases from 30° C. to 50° C., at a same grayscale, the brightness of the light-emitting element has a significant deviation, that is, the brightness of the light-emitting element at 50° C. is greater than the brightness at 30° C. By comparing the curve Land the curve L, it can be seen that when the temperature of the pixel circuit increases from 30° C. to 50° C., by increasing the reset voltage, a brightness deviation of the pixel circuit at 30° C. and 50° C. may be reduced, which is conducive to good uniformity of the brightness of the light-emitting element.

For example, when the temperature or the driving current of the pixel circuit is monitored by a detection manner, the driving current may be changed to a reasonable value by changing a magnitude of the reset signal to reduce the impact of temperature change.

For example, the pixel circuit corresponds to a plurality of display frame cycles, and each display frame cycle includes at least a reset phase, a compensation phase, a data writing phase and a light-emitting phase described in the embodiments of the present disclosure. For example, in some embodiments, a display frame cycle may include at least one refresh frame, for example, may include a plurality of refresh frames, but the embodiments of the present disclosure are not limited thereto. For example, the reset phase, the compensation phase, the data writing phase and the light-emitting phase in the embodiments of the present disclosure are all located within the refresh frame. For example, in some other embodiments, a display frame cycle may include at least one refresh frame and at least one hold frame. For example, the hold frame may include a hold reset phase, a hold stress application phase and a hold light-emitting phase.

For example, when the display frame cycle has only a plurality of refresh frames but no hold frame, a driving mode of a display panel using the pixel circuit is a high refresh driving mode, for example, its refresh frequency is above 120 Hz. For example, when the display frame cycle has a plurality of refresh frames and at least one hold frame, the plurality of refresh frames and at least one hold frame are alternately arranged, and the driving mode of the display panel using the pixel circuit is a low refresh driving mode. For example, a duration of the hold frame may be ½, ⅓, 1/10, 1/20, 1/30 or 1/60 of a duration of the refresh frame, and the embodiments of the present disclosure do not limit this.

2 2 2 1 For example, in at least one embodiment of the present disclosure, a first reset signal is adjusted to a second reset signal during a reset signal adjustment period. For example, the reset signal adjustment period may be located between two adjacent display frame cycles, so that the second reset signal may be written before a start of a next display frame cycle, and a value of the second reset signal in the next display frame cycle remains as Vini, and after a certain charging time, the voltage value of the first electrode of the driving transistor is Vs, where Vsis greater than the voltage value Vsof the first electrode of the driving transistor corresponding to the first reset signal.

1 2 1 2 2 1 For example, in at least one embodiment of the present disclosure, the reset signal adjustment period is located within a display frame cycle, and the reset signal adjustment period may overlap at least partially with any of the reset phase, the compensation phase, the data writing phase, and the light-emitting phase. For example, within a display frame cycle, the reset signal adjustment period may overlap at least partially with the reset phase. For example, in a part of the reset phase (for example, the second sub-reset phase in the aforementioned embodiment), a value of the reset signal is equal to the value of the first reset signal Vini, and in another part of the reset phase (for example, the third sub-reset phase in the aforementioned embodiment), the reset signal is adjusted to the second reset signal, and its value is equal to the value of the second reset signal Vini. Thus, after the reset signal adjustment period, the voltage value of the first electrode of the driving transistor is adjusted from Vsto Vs, where Vsis greater than Vs.

1 2 1 2 2 1 For example, in at least one embodiment of the present disclosure, the reset signal adjustment period is located within a display frame cycle, and the reset signal adjustment period does not overlap with any of the reset phase, the compensation phase, the data writing phase, and the light-emitting phase. For example, the reset adjustment period can be located between the reset phase and the compensation phase. For example, in a part of the reset phase (such as the third sub-reset phase in the aforementioned embodiment), the value of the reset signal is equal to the value of the first reset signal Vini, and in a part of the compensation phase (such as the first sub-compensation phase in the aforementioned embodiment), the reset signal is adjusted to a second reset signal, and its value is equal to the value of the second reset signal Vini. Thus, after the reset signal adjustment period, the voltage value of the first electrode of the driving transistor is adjusted from Vsto Vs, where Vsis greater than Vs.

29 FIG. is a schematic diagram of a reset voltage changing with temperature in at least one embodiment of the present disclosure.

For example, in some embodiments of the present disclosure, when an area of a light-emitting region of the light-emitting element is different, a parasitic capacitance of the light-emitting element itself is different. For example, the larger the light-emitting region of the light-emitting element, the greater the parasitic capacitance of the light-emitting element itself. For example, for some display panels, the display panel includes a first sub-pixel, a second sub-pixel, and a third sub-pixel; the first sub-pixel is configured to emit red light, the second sub-pixel is configured to emit green light, and the third sub-pixel is configured to emit blue light. A light-emitting region of a light-emitting element of the first sub-pixel has a first light-emitting area, a light-emitting region of a light-emitting element of the second sub-pixel has a second light-emitting area, and a light-emitting region of a light-emitting element of the third sub-pixel has a third light-emitting area; and the first light-emitting area is smaller than the second light-emitting area, and the second light-emitting area is smaller than the third light-emitting area. A first parasitic capacitance of the light-emitting element of the first sub-pixel itself is less than a second parasitic capacitance of the light-emitting element of the second sub-pixel itself, and the second parasitic capacitance of the light-emitting element of the second sub-pixel itself is less than a third parasitic capacitance of the light-emitting element of the third sub-pixel itself.

1 For example, when reset voltages of the first sub-pixel, the second sub-pixel, and the third sub-pixel are all equal to the value of the first reset signal Viniin the reset phase, and in a case where driving currents are the same, when the temperature of the pixel circuits of the three sub-pixels increases from the first display temperature to the second display temperature, there is a first voltage increase amount between the first electrode and the second electrode of the light-emitting element of the first sub-pixel, there is a second voltage increase amount between the first electrode and the second electrode of the light-emitting element of the second sub-pixel, there is a third voltage increase amount between the first electrode and the second electrode of the light-emitting element of the third sub-pixel, and the first voltage increase amount is greater than the second voltage increase amount, and the second voltage increase amount is greater than the third voltage increase amount. As a result, a first current increase amount of a driving current of the light-emitting element of the first sub-pixel is greater than a second current increase amount of a driving current of the light-emitting element of the second sub-pixel, and the second current increase amount of the driving current of the light-emitting element of the second sub-pixel is greater than an increase amount of a driving current of the light-emitting element of the third sub-pixel.

In order to balance the impact of temperature increase on the driving current, it is necessary to increase values of the reset signals received by the first sub-pixel, the second sub-pixel and the third sub-pixel respectively, and a reset signal increase amount corresponding to the first sub-pixel is greater than a reset signal increase amount corresponding to the second sub-pixel, and the reset signal increase amount corresponding to the second sub-pixel is greater than a reset signal increase amount corresponding to the third sub-pixel, so that a gate-source voltage reduction amount in the pixel circuit of the first sub-pixel is greater than a gate-source voltage reduction amount in the pixel circuit of the second sub-pixel, and the gate-source voltage reduction amount in the pixel circuit of the second sub-pixel is greater than a gate-source voltage reduction amount in the pixel circuit of the third sub-pixel. Accordingly, a driving current reduction amount of the first sub-pixel is greater than a driving current reduction amount of the second sub-pixel, and the driving current reduction amount of the second sub-pixel is greater than a driving current reduction amount of the third sub-pixel, thereby causing the driving current of each sub-pixel to be in a stable state.

Therefore, when the light-emitting areas of the light-emitting elements of a plurality of pixel circuits are different, and when the temperature at which the pixel circuit is located increases, the impact of the temperature increase on the driving current may be balanced by causing a relatively large increase amount of the reset signal value corresponding to the light-emitting element with a smaller light-emitting area.

For example, in some other embodiments of the present disclosure, for some display panels, the display panel includes a first sub-pixel, a second sub-pixel, and a third sub-pixel; the first sub-pixel is configured to emit red light, the second sub-pixel is configured to emit green light, and the third sub-pixel is configured to emit blue light. The light-emitting element of the first sub-pixel has a first light-emitting efficiency, the light-emitting element of the second sub-pixel has a second light-emitting efficiency, and the light-emitting element of the third sub-pixel has a third light-emitting efficiency, and the first light-emitting efficiency is greater than the second light-emitting efficiency, and the second light-emitting efficiency is greater than the third light-emitting efficiency.

1 For example, when the reset voltages of the first sub-pixel, the second sub-pixel, and the third sub-pixel are all equal to the value of the first reset signal Viniin the reset phase, and in a case where the driving currents are the same, when the temperature of the pixel circuits of the three sub-pixels increases from the first display temperature to the second display temperature, in order to ensure that the luminous brightness remains unchanged, a voltage increase amount required for the light-emitting element of the first sub-pixel is less than a voltage increase amount required for the light-emitting element of the second sub-pixel, and the voltage increase amount required for the light-emitting element of the second sub-pixel is less than a voltage increase amount required for the light-emitting element of the third sub-pixel. Thus, an increase amount in the driving current of the light-emitting element of the first sub-pixel is less than an increase amount in the driving current of the light-emitting element of the second sub-pixel, and the increase amount in the driving current of the light-emitting element of the second sub-pixel is less than an increase amount in the driving current of the light-emitting element of the third sub-pixel.

In order to balance the impact of the temperature increase on the driving current, it is necessary to increase the values of the reset signals received by the first sub-pixel, the second sub-pixel and the third sub-pixel respectively, and the reset signal increase amount corresponding to the first sub-pixel is less than the reset signal increase amount corresponding to the second sub-pixel, and the reset signal increase amount corresponding to the second sub-pixel is less than the reset signal increase amount corresponding to the third sub-pixel, so that the gate-source voltage reduction amount in the pixel circuit of the first sub-pixel is less than the gate-source voltage reduction amount in the pixel circuit of the second sub-pixel, and the gate-source voltage reduction amount in the pixel circuit of the second sub-pixel is less than the gate-source voltage reduction amount in the pixel circuit of the third sub-pixel. Accordingly, the driving current reduction amount of the first sub-pixel is less than the driving current reduction amount of the second sub-pixel, and the driving current reduction amount of the second sub-pixel is less than the driving current reduction amount of the third sub-pixel, thereby causing the driving current of each sub-pixel to be in a stable state.

Therefore, when luminous efficiencies of the light-emitting elements of a plurality of pixel circuits are different, and when the temperature of the pixel current increases, the impact of temperature increase on the driving current may be balanced by causing a relatively large increase amount of the reset signal value corresponding to the light-emitting element with a smaller luminous efficiency.

29 FIG. For example, as shown in, in some embodiments of the present disclosure, the first sub-pixel corresponds to a curve R, the second sub-pixel corresponds to a curve G, and the first sub-pixel corresponds to a curve B. On the one hand, because the first light-emitting area corresponding to the first sub-pixel is smaller than the second light-emitting area of the second sub-pixel, the second light-emitting area of the second sub-pixel is smaller than the third light-emitting area. When the temperature rises, for example, from 30° C. to 60° C., an increase amount in a reset voltage of the first sub-pixel is greater than an increase amount in a reset voltage of the second sub-pixel and an increase amount in a reset voltage of the third sub-pixel. On the other hand, because a luminous efficiency of the light-emitting element of the third sub-pixel is lower than a luminous efficiency of the light-emitting element of the second sub-pixel, and a luminous efficiency of the first sub-pixel is substantially same as the luminous efficiency of the light-emitting element of the second sub-pixel, when the temperature rises, the increase amount in the reset voltage of the third sub-pixel is greater than the increase amount in the reset voltage of the second sub-pixel, thereby causing the driving currents of the sub-pixels emitting different colors of light to be all in a stable state.

29 FIG. For example, in some embodiments of the present disclosure, referring to, because a reset voltage of a first color sub-pixel is relatively close to a reset voltage of a third color sub-pixel, the first color sub-pixel and the third color sub-pixel may correspond to a same reset voltage, and the second color sub-pixel may correspond to a reset voltage alone, thereby reducing difficulty in adjustment.

30 FIG. is a schematic diagram of a reference voltage changing with temperature in at least one embodiment of the present disclosure.

4 FIG.A For example, as shown in, a value of the reference signal REF may also be adjustable, which may be a direct current signal or may be a non-direct current signal. For example, the reference signal REF may be a reference voltage Vref, and the method for reducing the impact of temperature change on the luminous brightness provided by the embodiment of the present disclosure includes: as the ambient temperature of the pixel circuit increases, setting the reference voltage Vref to decrease accordingly.

4 FIG.A 27 FIG. 1 2 1 2 For example, as shown inand, when the temperature of the pixel circuit increases, for example, from 0° C. to 30° C., or from 30° C. to 60° C., the reference voltage Vref may be increased accordingly, for example, from Vrefto Vref. For example, when the reset phase is completed, the driving transistor DT approaches the OFF state, so the voltage value of the first electrode of the driving transistor DT is correspondingly reduced from Vref−Vth to Vref−Vth, so that the gate-source voltage Vgs of the driving transistor DT may be reduced, and the driving current in the light-emitting phase may decrease.

When the temperature of the pixel circuit increases, the mobility of the driving transistor increases and the driving current increases, therefore, by reducing the reference voltage, the increase of the driving current may be suppressed, and the magnitude of the driving current in the pixel circuit may be within a reasonable range, so that the driving current is more stable.

For example, in at least one embodiment of the present disclosure, the first power supply voltage may be a constant voltage or may be a non-constant voltage. For example, a value of the first power supply voltage may also be adjustable. For example, when the operating requirement of the pixel circuit is met, power consumption may be reduced by lowering the first power supply voltage.

For example, in at least one embodiment of the present disclosure, the second power supply voltage may be a constant voltage or may be a non-constant voltage. For example, a value of the second power supply voltage may also be adjustable. For example, when the operating requirement of the pixel circuit is met, the brightness of the light-emitting element can be adjusted by adjusting the second power supply voltage.

1 FIG. 10 100 300 600 780 At least one embodiment of the present disclosure further provides a pixel circuit. Referring to, the pixel circuitincludes a driving circuit, a first compensation circuit, a light-emitting element, and a reset control circuit. That is, the pixel circuit may not include the second light-emitting control circuit of the pixel circuit in the above embodiment. For other structures and driving methods of the pixel circuit, please refer to the relevant description of the above embodiments, which will not be repeated here.

1 FIG. 100 100 100 100 100 100 1 100 100 2 100 100 3 100 100 100 600 100 600 600 m a b m a b a b As shown in, the driving circuitincludes a control terminal, a first terminal, and a second terminal. The control terminalof the driving circuitis electrically connected to the first node N, the first terminalof the driving circuitis electrically connected to the second node N, and the second terminalof the driving circuitis electrically connected to the third node N. The driving circuitis configured to control the magnitude of the driving current flowing through the first terminaland the second terminal. For example, the driving current may be used to drive the light-emitting elementto emit light. For example, in the light-emitting phase, the driving circuitmay provide the light-emitting elementwith the driving current to drive the light-emitting elementto emit light.

1 FIG. 2 FIG. 300 300 300 300 300 300 300 2 300 300 300 300 2 300 300 1 300 100 100 2 300 1 1 100 100 1 100 100 m a b c m a b c m m a As shown in, the first compensation circuitincludes a control terminal, a first terminal, a second terminal, and a third terminal. The control terminalof the first compensation circuitis configured to receive a first compensation control signal G, the first terminalof the first compensation circuitis electrically connected to a reference signal terminal REF to receive a reference signal REF, the second terminalof the first compensation circuitis electrically connected to the second node N, and the third terminalof the first compensation circuitis electrically connected to the first node N. The first compensation circuitis configured to apply the reference signal REF to the control terminalof the driving circuitin response to the first compensation control signal G. For example, the first compensation circuitmay include a first storage capacitor C(see), a first electrode of the first storage capacitor Cis electrically connected to the control terminalof the driving circuit, and a second electrode of the first storage capacitor Cis electrically connected to the first terminalof the driving circuit, but the embodiments of the present disclosure are not limited thereto.

1 FIG. 600 600 600 600 600 100 100 600 600 600 600 600 a b a a b For example, as shown in, the light-emitting elementincludes a first electrodeand a second electrode, the first electrodeof the light-emitting elementis electrically connected to the first terminalof the driving circuit, the second electrodeof the light-emitting elementis electrically connected to a second voltage terminal VSS to receive a second power supply voltage VSS, and the light-emitting elementis configured to emit light driven by the driving current. For example, the second voltage terminal VSS may be grounded, that is, the second power supply voltage VSS may be OV. For example, the second power supply voltage VSS may be a negative voltage. For example, the light-emitting elementmay be an organic light-emitting diode (OLED). For example, the light-emitting elementmay also be other types of electroluminescent devices such as inorganic light-emitting diodes, quantum-dot light-emitting elements, etc. The embodiments of the present disclosure do not limit the type of the light-emitting element.

1 FIG. 780 780 780 780 780 780 780 3 780 780 100 100 780 780 780 780 600 600 780 600 600 100 100 3 m a b c m a a b c a a a As shown in, the reset control circuitincludes a control terminal, a first terminal, a second terminal, and a third terminal. The control terminalof the reset control circuitis configured to receive a reset control signal G, the first terminalof the reset control circuitis electrically connected to the first terminalof the driving circuit, the second terminalof the reset control circuitis electrically connected to a reset signal terminal VINI to receive a reset signal VINI, the third terminalof the reset control circuitis electrically connected to the first electrodeof the light-emitting element, and the reset control circuitis configured to apply the reset signal VINI to the first electrodeof the light-emitting elementand/or the first terminalof the driving circuitin response to the reset control signal G.

1 FIG. 780 780 100 100 780 780 780 600 600 100 600 600 100 100 10 a a b a a a As shown in, the first terminalof the reset control circuitis electrically connected to the first terminalof the driving circuit, and the second terminalof the reset control circuitis electrically connected to the reset signal terminal VINI. Thus, the reset signal from the reset signal terminal VINI needs to pass through the reset control circuitbefore it may be applied to the first electrodeof the light-emitting elementand/or the first terminal of the driving circuit, thereby reducing the impact of the fluctuation of the reset signal on the voltage of the first electrodeof the light-emitting elementand the first terminalof the driving circuit, and reducing the risk of introducing noise into the pixel circuit, thereby causing the driving current to be more stable to improve the display effect.

With development of an OLED display technology, an oxide process is often used in OLED display products because of its high uniformity. A coupling effect of some capacitors of the pixel driving circuit fabricated by the oxide process will introduce noise in the display phase, so that the driving current output by the pixel driving circuit is unstable, affecting reliability of the pixel driving circuit.

31 FIG. 48 FIG. 1 FIG. toare schematic diagrams of other implementation examples of the pixel circuit shown in.

31 FIG. 31 FIG. is a structural schematic diagram of another pixel driving circuit provided in an embodiment of the present disclosure. As shown in, the pixel driving circuit provided in the embodiment of the present disclosure may include: a driving sub-circuit, a first control sub-circuit, a second control sub-circuit, a third control sub-circuit and a storage sub-circuit.

1 FIG. 31 FIG. 1 FIG. 31 FIG. 1 FIG. 31 FIG. 1 FIG. 31 FIG. 1 FIG. 31 FIG. For example, in some embodiments of the present disclosure, the driving circuit and the connection relationship incorrespond to the driving sub-circuit inand subsequent embodiments; the data writing circuit and the first compensation circuit and the connection relationship incorrespond to the first control sub-circuit and the storage sub-circuit inand subsequent embodiments; the first light-emitting control circuit and the second light-emitting control circuit incorrespond to the second control sub-circuit inand subsequent embodiments; the light-emitting element incorresponds to the light-emitting device inand subsequent embodiments; the reset control circuit and the connection relationship incorrespond to the third control sub-circuit inand subsequent embodiments.

31 FIG. 1 2 3 3 1 2 1 2 1 1 1 2 1 2 2 3 4 2 4 3 1 2 1 3 3 1 1 3 1 3 As shown in, the driving sub-circuit is electrically connected to a first node N, a second node Nand a third node Nrespectively, and is configured to provide a driving current to the third node Nunder a control of signals of the first node Nand the second node N; the first control sub-circuit is electrically connected to a first scan signal line G, a second scan signal line G, a data signal line Data, a reference signal line REF and the first node Nrespectively, and is configured to provide a signal of the data signal line Data or the reference signal line REF to the first node Nunder a control of signals of the first scan signal line Gand the second scan signal line G; the second control sub-circuit is electrically connected to a first light-emitting signal line EM, a second light-emitting signal line EM, a first power line VDD, the second node N, the third node Nand a fourth node Nrespectively, and is configured to provide the second node Nwith a signal of the first power line VDD and provide the fourth node Nwith the signal of the third node Nunder control of signals of the first light-emitting signal line EMand the second light-emitting signal line EM; the third control sub-circuit is electrically connected to a first reset signal line Reset, an auxiliary signal line VX and the third node Nrespectively, and is configured to control a signal of the third node Nunder control of a signal of the first reset signal line Resetand a signal of the auxiliary signal line VX; the storage sub-circuit is electrically connected to the first node Nand the third node Nrespectively, and is configured to store a voltage difference of between the signal of the first node Nand the signal of third node N.

31 FIG. 4 In an exemplary implementation, as shown in, the pixel driving circuit is electrically connected to the light-emitting device L through the fourth node N.

4 In an exemplary implementation, the light-emitting device L may include a first electrode (anode), an organic light-emitting layer and a second electrode (cathode) stacked on each other. Exemplarily, the anode of the light-emitting device L is electrically connected to the fourth node N, and the cathode of the light-emitting device L is electrically connected to a second power line VSS.

In an exemplary implementation, the light-emitting device L may include a current driven device, and may use a current light-emitting diode, such as a micro light-emitting diode (Micro LED) or a mini light-emitting diode (Mini LED) or an organic light-emitting diode (OLED) or a quantum-dot light-emitting diode (QLED). A typical size (e.g., length) of the Micro LED may be less than 100 μm, such as 10 μm to 50 μm. A typical size (e.g., length) of the Mini LED may be about 100 μm to 300 μm, such as 120 μm to 260 μm.

In an exemplary implementation, the organic light-emitting layer may include a stacked hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), an emitting layer (EML), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an exemplary implementation, the hole injection layer of all sub-pixels may be a common layer connected together, the electron injection layer of all sub-pixels may be a common layer connected together, the hole transport layer of all sub-pixels may be a common layer connected together, the electron transport layer of all sub-pixels may be a common layer connected together, the hole blocking layer of all sub-pixels may be a common layer connected together, emitting layers of adjacent sub-pixels may have a small overlap, or may be isolated, and electron blocking layers of adjacent sub-pixels may have a small overlap, or may be isolated.

In an exemplary implementation, the first power line VDD continuously provides a high-level signal, and the signal of the first power line VDD is a direct current signal.

In an exemplary implementation, the second power line VSS continuously provides a low-level signal, and a signal of the second power line VSS is a direct current signal.

In an exemplary implementation, the reference signal line REF continuously provides a low-level signal, and a signal of the reference signal line REF is a direct current signal. Exemplarily, a voltage of the signal of the reference signal line REF may be OV.

1 2 2 1 In an exemplary implementation, the pixel driving circuit is located in a display substrate, and content displayed by the display substrate includes a plurality of display frames. In any display frame, a signal of the first scan signal line Gis a pulse signal, and a signal of the second scan signal line Gis a pulse signal. A time period in which the signal of the second scan signal line Gis a valid level signal occurs before a time period in which the signal of the first scan signal line Gis a valid level signal.

An embodiment of the present disclosure provides a pixel driving circuit, including: a driving sub-circuit, a first control sub-circuit, a second control sub-circuit, a third control sub-circuit and a storage sub-circuit; the driving sub-circuit is electrically connected to a first node, a second node and a third node respectively, and is configured to provide the third node with a driving current under control of signals of the first node and the second node; the first control sub-circuit is electrically connected to a first scan signal line, a second scan signal line, a data signal line, a reference signal line and the first node respectively, and is configured to provide the first node with a signal of a data signal line or a reference signal line under a control of signals of the first scan signal line and the second scan signal line; the second control sub-circuit is electrically connected to the first light-emitting signal line, the second light-emitting signal line, the first power line, the second node, the third node and the fourth node respectively, and is configured to provide the second node with the signal of the first power line and provide the fourth node with the signal of the third node under control of signals of the first light-emitting signal line and the second light-emitting signal line; the third control sub-circuit is electrically connected to the first reset signal line, the auxiliary signal line and the third node respectively, and is configured to control the signal of the third node under control of a signal of the first reset signal line and a signal of the auxiliary signal line; the storage sub-circuit is electrically connected to the first node and the third node respectively, and is configured to store a voltage difference between the signal of the first node and the signal of the third node. In the present disclosure, the signal of the third node may be controlled through the signals of the first reset signal line and the auxiliary signal line by setting the third control sub-circuit, thereby avoiding introduction of noise in the display phase, maintaining stability of the driving current output by the pixel driving circuit, and improving reliability of the pixel driving circuit.

1 1 2 In an exemplary implementation, an operating process of the pixel driving circuit includes a display phase, and the display phase includes: a writing phase and a light-emitting phase, in which the light-emitting phase occurs after the writing phase, and the signal of the first scan signal line Gis a valid level signal in the writing phase. The signals of the first light-emitting signal line EMand the second light-emitting signal line EMare both valid level signals in the light-emitting phase, and a time period in which the writing phase occurs is a writing time period.

32 FIG. 31 FIG. 32 FIG. 1 3 4 3 6 8 2 6 1 6 6 5 2 5 2 3 8 8 4 is an equivalent circuit diagramincluding the third control sub-circuit shown in. As shown in, in an exemplary implementation, the third control sub-circuit may also be electrically connected to a third reset signal line Resetand an initial signal line INIT respectively, and is configured to provide the fourth node Nwith a signal of the initial signal line under a control of a signal of the third reset signal line Reset. Exemplarily, the third control sub-circuit may include: a sixth transistor T, an eighth transistor Tand a second capacitor C. A control electrode of the sixth transistor Tis electrically connected to the first reset signal line Reset, a first electrode of the sixth transistor Tis electrically connected to the auxiliary signal line VX, and a second electrode of the sixth transistor Tis electrically connected to a fifth node N; a first terminal of the second capacitor Cis electrically connected to the fifth node N, and a second terminal of the second capacitor Cis electrically connected to the third node N; a first electrode of the eighth transistor Tis electrically connected to the initial signal line INIT, and a second electrode of the eighth transistor Tis electrically connected to the fourth node N.

32 FIG. 4 In an exemplary implementation, as shown in, a signal of the auxiliary signal line VX is a non-direct current signal and is electrically connected to the fourth node N.

32 FIG. For example, in some embodiments, as shown in, a signal value of the initial signal line INIT is adjustable to reduce the impact of temperature change on the magnitude of the driving current. Regarding an adjustment manner of the signal value of the initial signal line INIT, please refer to an adjustment manner for the value of the reset signal in the above embodiment, which will not be repeated here.

32 FIG. 3 4 2 3 2 1 2 2 3 3 In an exemplary implementation, as shown in, in the present disclosure, the third node Nand the fourth node Nmay be reset before the writing time period by allowing the signal of the second light-emitting signal line EMto be a valid level signal in a part of the time period when the signal of the third reset signal line Resetis a valid level signal, so as to ensure a display uniformity of the pixel driving circuit. In the present disclosure, the voltage values of the signals at both terminals of the second capacitor Cin the light-emitting phase may be same by allowing the signals of the first reset signal line Resetand the second light-emitting signal line EMto be valid level signals in at least part of the time period after the writing time period, which avoids the impact of the second capacitor Con the third node Nin the light-emitting phase, avoids the introduction of noise at the third node N, maintains the stability of the driving current output by the pixel driving circuit, and improves the reliability of the pixel driving circuit.

33 FIG. 31 FIG. 33 FIG. 2 2 3 5 2 6 7 2 6 6 5 7 2 7 5 7 3 2 5 2 3 is an equivalent circuit diagramincluding the third control sub-circuit shown in. As shown in, in an exemplary implementation, the third control sub-circuit may also be electrically connected to a second reset signal line Reset, and is also configured to provide the third node Nwith a signal of the fifth node Nunder control of a signal of the second reset signal line Reset. Exemplarily, the third control sub-circuit may include: a sixth transistor T, a seventh transistor T, and a second capacitor C. A first electrode of the sixth transistor Tis electrically connected to the auxiliary signal line VX, and a second electrode of the sixth transistor Tis electrically connected to the fifth node N; a control electrode of the seventh transistor Tis electrically connected to the second reset signal line Reset, a first electrode of the seventh transistor Tis electrically connected to the fifth node N, and a second electrode of the seventh transistor Tis electrically connected to the third node N; a first terminal of the second capacitor Cis electrically connected to the fifth node N, and a second terminal of the second capacitor Cis electrically connected to the third node N.

33 FIG. In an exemplary implementation, as shown in, the signal of the auxiliary signal line VX may be a direct current signal, and may be same as the signal of any one of the initial signal line INIT, the reference signal line REF, and the first power line VDD.

33 FIG. For example, in some embodiments, as shown in, a signal value of the auxiliary signal line VX is adjustable to reduce the impact of temperature change on the magnitude of the driving current. For the adjustment manner of the signal value of the auxiliary signal line VX, please refer to the adjustment manner of the reset signal value in the above embodiment, which will not be repeated here.

33 FIG. 3 4 2 2 1 2 2 2 3 In an exemplary implementation, as shown in, in the present disclosure, the third node Nand the fourth node Nmay be reset before the writing time period by allowing the signals of the second reset signal line Resetand the second light-emitting signal line EMto be valid level signals in a part of the time period when the signal of the first reset signal line Resetis a valid level signal, so as to ensure a display uniformity of the pixel driving circuit. In the present disclosure, the voltage values of the signals at both terminals of the second capacitor Cin the light-emitting phase may be same by allowing the signal of the second reset signal line Resetto be a valid level signal in at least part of the time period after the writing time period, which avoids the impact of the second capacitor Con the third node Nin the light-emitting phase, avoids the introduction of noise in the display phase, maintains the stability of the driving current output by the pixel driving circuit, and improves the reliability of the pixel driving circuit.

34 FIG. 31 FIG. 35 FIG. 31 FIG. 34 FIG. 35 FIG. 3 4 3 4 3 8 8 3 8 8 4 is an equivalent circuit diagramincluding the third control sub-circuit shown in, andis an equivalent circuit diagramincluding the third control sub-circuit shown in. In an exemplary implementation, as shown inand, the third control sub-circuit may also be electrically connected to the third reset signal line Resetand the initial signal line INIT respectively, and is configured to provide the fourth node Nwith the signal of the initial signal line under the control of the signal of the third reset signal line Reset. Exemplarily, the third control sub-circuit may also include: an eighth transistor T, a control electrode of the eighth transistor Tis electrically connected to the third reset signal line Reset, a first electrode of the eighth transistor Tis electrically connected to the initial signal line, and a second electrode of the eighth transistor Tis electrically connected to the fourth node N.

4 34 FIG. 35 FIG. In an exemplary embodiment, the signal of the auxiliary signal line VX is a direct current signal, and the signal of the auxiliary signal line VX is the same as the signal of any one of the initial signal line, the reference signal line REF and the first power line VDD; or, the signal of the auxiliary signal line VX is a non-direct current signal, and the signal of the auxiliary signal line VX is electrically connected to the fourth node N.is illustrated by taking that the signal of the auxiliary signal line VX is a direct current signal, andis illustrated by taking that the signal of the auxiliary signal line VX is a no-direct current signal.

34 FIG. For example, in some embodiments, as shown in, the signal value of the auxiliary signal line VX is the same as the signal value of the initial signal line VINI, and the signal value of the initial signal line VINI is adjustable, so as to reduce the impact of temperature change on the magnitude of the driving current. For the adjustment manner of the signal value of the initial signal line VINI, please refer to the adjustment manner of the reset signal value in the above embodiment, which will not be repeated here.

35 FIG. For example, in some embodiments, as shown in, the signal value of the initial signal line VINI is adjustable to reduce the impact of temperature change on the magnitude of the driving current. For the adjustment method of the signal value of the initial signal line VINI, please refer to the adjustment method of the reset signal value in the above embodiment, which will not be repeated here.

34 FIG. 35 FIG. 1 3 4 2 3 2 2 2 3 In an exemplary embodiment, as shown inand, when the signal of the first reset signal line Resetis a valid level signal, the signal of the third reset signal line is a valid level signal, and the signal of the second reset signal line is an invalid level signal. When the signal of the second reset signal line is a valid level signal, the signal of the first reset signal line is an invalid level signal. In the present disclosure, the third node Nand the fourth node Nmay be reset before the writing time period by allowing the signal of the second light-emitting signal line EMto be a valid level signal in a part of the time period when the signal of the first reset signal line Resetis a valid level signal, so as to ensure a display uniformity of the pixel driving circuit. In the present disclosure, the voltage values of the signals at both terminals of the second capacitor Cin the light-emitting phase may be same by allowing the signal of the second reset signal line Resetto be a valid level signal in at least part of the time period after the writing time period, which avoids the impact of the second capacitor Con the third node Nin the light-emitting phase, avoids the introduction of noise in the display phase, maintains the stability of the driving current output by the pixel driving circuit, and improves the reliability of the pixel driving circuit.

36 FIG. 31 FIG. 37 FIG. 31 FIG. 36 FIG. 37 FIG. 5 6 3 4 3 6 8 2 6 1 6 5 6 3 8 3 8 8 4 2 2 5 is an equivalent circuit diagramincluding the third control sub-circuit shown in, andis an equivalent circuit diagramincluding the third control sub-circuit shown in. In an exemplary implementation, as shown inand, the third control sub-circuit may also be electrically connected to the third reset signal line Resetand the initial signal line INIT respectively, and is configured to provide the fourth node Nwith the signal of the initial signal line under the control of the signal of the third reset signal line Reset. Exemplarily, the third control sub-circuit may also include: a sixth transistor T, an eighth transistor T, and a second capacitor C. A control electrode of the sixth transistor Tis electrically connected to the first reset signal line Reset, a first electrode of the sixth transistor Tis electrically connected to the fifth node N, and a second electrode of the sixth transistor Tis electrically connected to the third node N; a control electrode of the eighth transistor Tis electrically connected to the third reset signal line Reset, a first electrode of the eighth transistor Tis electrically connected to the initial signal line INIT, and a second electrode of the eighth transistor Tis electrically connected to the fourth node N; a first terminal of the second capacitor Cis electrically connected to the auxiliary signal line VX, and a second terminal of the second capacitor Cis electrically connected to the fifth node N.

4 36 FIG. 37 FIG. In an exemplary implementation, the signal of the auxiliary signal line VX is a direct current signal, and the signal of the auxiliary signal line VX is the same as the signal of any one of the initial signal line, the reference signal line REF, and the first power line VDD; or, the signal of the auxiliary signal line VX is a non-direct current signal, and the signal of the auxiliary signal line VX is electrically connected to the fourth node N.is illustrated by taking the signal of the auxiliary signal line VX being a direct current signal as an example, andis illustrated by taking the signal of the auxiliary signal line VX being a non-direct current signal as an example.

36 FIG. For example, in some embodiments, as shown in, the signal value of the auxiliary signal line VX is the same as the signal value of the initial signal line VINI, and the signal value of the initial signal line VINI is adjustable, so as to reduce the impact of temperature change on the magnitude of the driving current. For the adjustment manner of the signal value of the initial signal line VINI, please refer to the adjustment manner for the value of the reset signal in the above embodiment, which will not be repeated here.

37 FIG. For example, in some embodiments, as shown in, the signal value of the initial signal line VINI is adjustable to reduce the impact of temperature change on the magnitude of the driving current. For the adjustment manner of the signal value of the initial signal line VINI, please refer to the adjustment manner for the value of the reset signal in the above embodiment, which will not be repeated here.

36 FIG. 37 FIG. 3 4 2 3 1 2 3 In an exemplary implementation, as shown inand, in the present disclosure, the third node Nand the fourth node Nmay be reset before the writing time period by allowing the signal of the second light-emitting signal line EMto be a valid level signal in a part of the time period when the signal of the first reset signal line Resetis a valid level signal, so as to ensure the display uniformity of the pixel driving circuit. In the present disclosure, the first reset signal line Resetis allowed to be an invalid level signal in a time period after the writing time period, so that the second capacitor Cwill not impact the third node N, which avoids the introduction of noise in the display phase, maintains the stability of the driving current output by the pixel driving circuit, and improves the reliability of the pixel driving circuit.

In an exemplary implementation, the initial signal line INIT continuously provides a low-level signal, and the signal of the initial signal line INIT is a direct current signal.

In an exemplary implementation, the voltage value of the signal of the initial signal line INIT may be less than the voltage value of the signal of the second power line VSS, which may avoid false light emission of the light-emitting device L, and improve the reliability of the pixel driving circuit.

32 FIG. 37 FIG. toonly show six exemplary structures of the third control sub-circuit. It is easy for those skilled in the art to understand that implementation of the third control sub-circuit is not limited thereto.

38 FIG. 38 FIG. 1 2 3 4 5 1 1 1 1 1 1 2 2 2 2 1 3 1 3 2 3 3 4 1 4 4 2 5 2 5 3 5 4 1 1 1 3 is a partial equivalent circuit diagram of another pixel driving circuit provided in an embodiment of the present disclosure. As shown in, in an exemplary implementation, the first control sub-circuit may include: a first transistor Tand a second transistor T; the driving sub-circuit may include: a third transistor T; the second control sub-circuit may include: a fourth transistor Tand a fifth transistor T; and the storage sub-circuit may include: a first capacitor C. A control electrode of the first transistor Tis electrically connected to the first scan signal line G, a first electrode of the first transistor Tis electrically connected to the data signal line Data, and a second electrode of the first transistor Tis electrically connected to the first node N; a control electrode of the second transistor Tis electrically connected to the second scan signal line G, a first electrode of the second transistor Tis electrically connected to the reference signal line REF, and a second electrode of the second transistor Tis electrically connected to the first node N; a control electrode of the third transistor Tis electrically connected to the first node N, a first electrode of the third transistor Tis electrically connected to the second node N, and a second electrode of the third transistor Tis electrically connected to the third node N; a control electrode of the fourth transistor Tis electrically connected to the first light-emitting signal line EM, a first electrode of the fourth transistor Tis electrically connected to the first power supply line VDD, and a second electrode of the fourth transistor Tis electrically connected to the second node N; a control electrode of the fifth transistor Tis electrically connected to the second light-emitting signal line EM, a first electrode of the fifth transistor Tis electrically connected to the third node N, and a second electrode of the fifth transistor Tis electrically connected to the fourth node N; a first terminal of the first capacitor Cis electrically connected to the first node N, and a second terminal of the first capacitor Cis electrically connected to the third node N.

38 FIG. only shows an exemplary structure of the driving sub-circuit, the first control sub-circuit, the second control sub-circuit and the storage sub-circuit. It is easy for those skilled in the art to understand that implementation of the driving sub-circuit, the first control sub-circuit, the second control sub-circuit and the storage sub-circuit is not limited thereto.

39 FIG. 38 FIG. 40 FIG. 38 FIG. 41 FIG. 38 FIG. 42 FIG. 38 FIG. 39 FIG. 42 FIG. 39 FIG. 40 FIG. 41 FIG. 42 FIG. 1 2 3 4 1 2 3 4 5 1 2 6 7 8 1 1 1 1 1 2 2 2 2 1 3 1 3 2 3 3 4 1 4 4 2 5 2 5 3 5 4 6 1 6 6 5 7 2 7 5 7 3 8 3 8 8 4 1 1 1 3 2 5 2 3 7 8 7 8 In an exemplary implementation,is an equivalent circuit diagramof the pixel driving circuit shown in,is an equivalent circuit diagramof the pixel driving circuit shown in,is an equivalent circuit diagramof the pixel driving circuit shown in, andis an equivalent circuit diagramof the pixel driving circuit shown in. As shown into, in an exemplary implementation, the first control sub-circuit in the pixel driving circuit includes: a first transistor Tand a second transistor T; the driving sub-circuit includes: a third transistor T; the second control sub-circuit includes: a fourth transistor Tand a fifth transistor T; the storage sub-circuit includes: a first capacitor C; the third control sub-circuit includes a second capacitor Cand a sixth transistor T; and the third control sub-circuit also includes: at least one transistor of a seventh transistor Tand an eighth transistor T. A control electrode of the first transistor Tis electrically connected to the first scan signal line G, a first electrode of the first transistor Tis electrically connected to the data signal line Data, and a second electrode of the first transistor Tis electrically connected to the first node N; a control electrode of the second transistor Tis electrically connected to the second scan signal line G, a first electrode of the second transistor Tis electrically connected to the reference signal line REF, and a second electrode of the second transistor Tis electrically connected to the first node N; a control electrode of the third transistor Tis electrically connected to the first node N, a first electrode of the third transistor Tis electrically connected to the second node N, and a second electrode of the third transistor Tis electrically connected to the third node N; a control electrode of the fourth transistor Tis electrically connected to the first light-emitting signal line EM, a first electrode of the fourth transistor Tis electrically connected to the first power supply line VDD, and a second electrode of the fourth transistor Tis electrically connected to the second node N; a control electrode of the fifth transistor Tis electrically connected to the second light-emitting signal line EM, a first electrode of the fifth transistor Tis electrically connected to the third node N, and a second electrode of the fifth transistor Tis electrically connected to the fourth node N; a control electrode of the sixth transistor Tis electrically connected to the first reset signal line Reset, a first electrode of the sixth transistor Tis electrically connected to the auxiliary signal line VX, and a second electrode of the sixth transistor Tis electrically connected to the fifth node N; a control electrode of the seventh transistor Tis electrically connected to the second reset signal line Reset, a first electrode of the seventh transistor Tis electrically connected to the fifth node N, and a second electrode of the seventh transistor Tis electrically connected to the third node N; a control electrode of the eighth transistor Tis electrically connected to the third reset signal line Reset, a first electrode of the eighth transistor Tis electrically connected to the initial signal line INIT, and a second electrode of the eighth transistor Tis electrically connected to the fourth node N; a first terminal of the first capacitor Cis electrically connected to the first node N, and a second terminal of the first capacitor Cis electrically connected to the third node N; a first terminal of the second capacitor Cis electrically connected to the fifth node N, and a second terminal of the second capacitor Cis electrically connected to the third node N.andare illustrated by taking an example that the third control sub-circuit further includes: a seventh transistor Tand an eighth transistor T,is illustrated by taking an example that the third control sub-circuit further includes: a seventh transistor T, andis illustrated by taking an example that the third control sub-circuit further includes: an eighth transistor T.

39 FIG. 40 FIG. 39 FIG. 40 FIG. 7 8 4 In an exemplary implementation, as shown inand, a signal of the auxiliary signal line VX in the pixel driving circuit in which the third control sub-circuit further includes the seventh transistor Tand the eighth transistor Tmay be a direct current signal or may be a non-direct current signal.is an example of the auxiliary signal line VX in the pixel driving circuit being a direct current signal and being the same as the signal of any one of the initial signal line INIT, the reference signal line REF and the first power line VDD.is an example of the auxiliary signal line VX in the pixel driving circuit being a non-direct current signal and being electrically connected to the fourth node N.

41 FIG. 7 In an exemplary implementation, as shown in, the signal of the auxiliary signal line VX in the pixel driving circuit in which the third control sub-circuit further includes the seventh transistor Tis a direct current signal, and is the same as the signal of any one of the initial signal line, the reference signal line and the first power line.

42 FIG. 8 8 4 In an exemplary implementation, as shown in, the signal of the auxiliary signal line VX in the pixel driving circuit in which the third control sub-circuit further includes the eighth transistor Tis a non-direct current signal, and the eighth transistor Tis electrically connected to the fourth node N.

1 8 In an exemplary implementation, any transistor among the first transistor Tto the eighth transistor Tmay adopt an oxide thin film transistor. An active layer of the oxide thin film transistor adopts an oxide semiconductor. The oxide thin film transistor has an advantage of low leakage current.

1 8 In an exemplary implementation, any transistor among the first transistor Tto the eighth transistor Tis an N-type transistor.

43 FIG. 38 FIG. 44 FIG. 38 FIG. 43 FIG. 44 FIG. 5 6 1 2 3 4 5 1 2 6 8 1 1 1 1 1 2 2 2 2 1 3 1 3 2 3 3 4 1 4 4 2 5 2 5 3 5 4 6 1 6 5 6 3 8 3 8 8 4 1 1 1 3 2 2 5 In an exemplary implementation,is an equivalent circuit diagramof the pixel driving circuit shown in, andis an equivalent circuit diagramof the pixel driving circuit shown in. As shown inand, the first control sub-circuit in the pixel driving circuit may include: a first transistor Tand a second transistor T; the driving sub-circuit may include: a third transistor T; the second control sub-circuit may include: a fourth transistor Tand a fifth transistor T; the storage sub-circuit may include: a first capacitor C; and the third control sub-circuit may include a second capacitor C, a sixth transistor Tand an eighth transistor T. A control electrode of the first transistor Tis electrically connected to the first scan signal line G, a first electrode of the first transistor Tis electrically connected to the data signal line Data, and a second electrode of the first transistor Tis electrically connected to the first node N; a control electrode of the second transistor Tis electrically connected to the second scan signal line G, a first electrode of the second transistor Tis electrically connected to the reference signal line REF, and a second electrode of the second transistor Tis electrically connected to the first node N; a control electrode of the third transistor Tis electrically connected to the first node N, a first electrode of the third transistor Tis electrically connected to the second node N, and a second electrode of the third transistor Tis electrically connected to the third node N; a control electrode of the fourth transistor Tis electrically connected to the first light-emitting signal line EM, a first electrode of the fourth transistor Tis electrically connected to the first power supply line VDD, and a second electrode of the fourth transistor Tis electrically connected to the second node N; a control electrode of the fifth transistor Tis electrically connected to the second light-emitting signal line EM, a first electrode of the fifth transistor Tis electrically connected to the third node N, and a second electrode of the fifth transistor Tis electrically connected to the fourth node N; a control electrode of the sixth transistor Tis electrically connected to the first reset signal line Reset, a first electrode of the sixth transistor Tis electrically connected to the fifth node N, and a second electrode of the sixth transistor Tis electrically connected to the third node N; a control electrode of the eighth transistor Tis electrically connected to the third reset signal line Reset, a first electrode of the eighth transistor Tis electrically connected to the initial signal line INIT, and a second electrode of the eighth transistor Tis electrically connected to the fourth node N; a first terminal of the first capacitor Cis electrically connected to the first node N, and a second terminal of the first capacitor Cis electrically connected to the third node N; a first terminal of the second capacitor Cis electrically connected to the auxiliary signal line VX, and a second terminal of the second capacitor Cis electrically connected to the fifth node N.

43 FIG. 44 FIG. 43 FIG. 44 FIG. 6 8 2 4 In an exemplary implementation, as shown inand, the signal of the auxiliary signal line VX in the pixel driving circuit in which the third control sub-circuit includes the sixth transistor T, the eighth transistor Tand the second capacitor Cmay be a direct current signal, or may be a non-direct current signal.is illustrated by taking an example that the signal of the auxiliary signal line VX in the pixel driving circuit is a direct current signal and is the same as the signal of any one of the initial signal line INIT, the reference signal line REF and the first power line VDD, andis illustrated by taking an example that the signal of the auxiliary signal line VX in the pixel driving circuit is a non-DC signal and is electrically connected to the fourth node N.

1 2 4 5 6 8 In an exemplary implementation, any transistor of the first transistor T, the second transistor T, the fourth transistor T, the fifth transistor T, the sixth transistor Tand the eighth transistor Tmay be an oxide thin film transistor. An active layer of the oxide thin film transistor adopts an oxide semiconductor. The oxide thin film transistor has an advantage of low leakage current.

1 2 4 5 6 8 In an exemplary implementation, any transistor of the first transistor T, the second transistor T, the fourth transistor T, the fifth transistor T, the sixth transistor T, and the eighth transistor Tis an N-type transistor.

39 FIG. 44 FIG. 1 2 4 In an exemplary implementation, in the pixel driving circuit provided into, a quantity of the first transistor T, the second transistor T, and the fourth transistor Tmay be at least one.

1 1 In an exemplary implementation, when a quantity of the first transistors Tmay be at least two, control electrodes of all the first transistors are electrically connected to the first scan signal line, at least two first transistors are arranged in series, a first electrode of a first one of the first transistors is electrically connected to the data signal line, and a second electrode of a last one of the first transistors is electrically connected to the first node N.

2 2 1 In an exemplary implementation, when a quantity of the second transistors Tmay be at least two, control electrodes of all the second transistors Tare electrically connected to the second scan signal line, at least two second transistors are arranged in series, a first electrode of a first one of the second transistors is electrically connected to the reference signal line, and a second electrode of a last one of the second transistors is electrically connected to the first node N.

45 FIG. 39 FIG. 40 FIG. 39 40 FIGS.and 39 40 FIGS.and 1 8 1 2 is an operating timing diagram of the pixel driving circuit provided inand. An exemplary embodiment of the present disclosure is illustrated below through an operating process of the pixel driving circuit illustrated in. The pixel driving circuit inincludes eight transistors (a first transistor Tto an eighth transistor T) and two capacitors (a first capacitor Cand a second capacitor C), and all of the eight transistors are N-type transistors.

39 40 FIGS.and In an exemplary implementation, the operating process of the pixel driving circuit provided inmay include the following phases.

1 2 2 1 3 1 1 2 2 2 1 1 1 1 6 5 5 5 2 3 5 8 3 4 1 3 3 3 2 2 3 4 2 3 4 1 1 2 1 4 7 A first phase Pis referred to as a first reset phase, the signals of the second scan signal line G, the second light-emitting signal line EM, the first reset signal line Resetand the third reset signal line Resetare high-level signals, and the signals of the first scan signal line G, the first light-emitting signal line EMand the second reset signal line Resetare low-level signals. The signal of the second scan signal line Gis a high-level signal, the second transistor Tis turned on, the signal of the reference signal line REF is written into the first node N, the signal of the first node Nis initialized (reset), and original charges at the first node Nare cleared. The signal of the first reset signal line Resetis a high-level signal, the sixth transistor Tis turned on, the signal of the auxiliary signal line VX is written into the fifth node N, the signal of the fifth node Nis initialized (reset), and original charges at the fifth node Nare cleared. The signals of the second light-emitting signal line EMand the third reset signal line Resetare high-level signals, the fifth transistor Tand the eighth transistor Tare turned on, and the signal of the initial signal line INIT is written into the third node Nand the fourth node Nrespectively. Because a voltage difference between the voltage value of the signal of the first node Nand the voltage value of the signal of the third node Nare greater than a threshold voltage of the third transistor T, at this time, the third transistor Tis turned on, and the signal of the initial signal line INIT is written into the second node N, and the signals of the second node N, the third node Nand the fourth node Nare initialized (reset), and original charges at the second node N, the third node Nand the fourth node Nare cleared. The signals of the first scan signal line G, the first light-emitting signal line EMand the second reset signal line Resetare low-level signals, and the first transistor T, the fourth transistor Tand the seventh transistor Tare turned off. In this phase, the light-emitting device L does not emit light.

2 1 3 2 1 2 1 2 1 6 5 5 3 8 4 4 2 2 1 1 4 3 4 2 3 3 3 3 1 1 3 2 1 2 1 5 A second phase Pis a threshold compensation phase, the signals of the first reset signal line Reset, the third reset signal line Reset, the second scan signal line G, and the first light-emitting signal line EMare high-level signals, and the signals of the second reset signal line Reset, the first scan signal line G, and the second light-emitting signal line EMare low-level signals. The signal of the first reset signal line Resetis a high-level signal, the sixth transistor Tis turned on, the signal of the auxiliary signal line VX is continuously written into the fifth node N, and the signal of the fifth node Nis continuously initialized (reset). The signal of the third reset signal line Resetis a high-level signal, the eighth transistor Tis turned on, the signal of the initial signal line INIT is continuously written into the fourth node N, and the signal of the fourth node Nis continuously initialized (reset). The signal of the second scan signal line Gis a high-level signal, the second transistor Tis turned on, the signal of the reference signal line REF is continuously provided to the first node N, the signal of the first light-emitting signal line EMis a high-level signal, the fourth transistor Tis turned on, and the signal of the first power line VDD is written into the third node Nthrough the turned-on fourth transistor T, the second node Nand the turned-on third transistor T, until the voltage of the signal of the third node Nis V=Vref−Vth, where Vref is a voltage value of the signal of the initial signal line REF, Vth is a threshold voltage of the third transistor T, at this time, the first capacitor Cstores a voltage difference Vth of the signals of the first node Nand the third node N. The signals of the second reset signal line Reset, the first scan signal line Gand the second light-emitting signal line EMare low-level signals, and the first transistor T, the fifth transistor Tand the seventh transistor are turned off. In this phase, the light-emitting device L does not emit light.

3 1 3 1 2 2 1 2 1 6 5 5 3 8 4 4 1 1 1 1 1 1 1 2 3 3 3 1 1 2 1 2 2 2 1 2 2 4 5 7 A third phase Pis a data writing phase, the signals of the first reset signal line Reset, the third reset signal line Resetand the first scan signal line Gare high-level signals, the signals of the second reset signal line Reset, the second scan signal line G, the first light-emitting signal line EMand the second light-emitting signal line EMare low-level signals, and the data signal line Data outputs the data voltage. The signal of the first reset signal line Resetis a high-level signal, the sixth transistor Tis turned on, the signal of the auxiliary signal line VX is continuously written into the fifth node N, and the signal of the fifth node Nis continuously initialized (reset). The signal of the third reset signal line Resetis a high-level signal, the eighth transistor Tis turned on, the signal of the initial signal line INIT is continuously written into the fourth node N, and the signal of the fourth node Nis continuously initialized (reset). The signal of the first scan signal line Gis a high-level signal, the first transistor Tis turned on, and the data voltage of the data signal line Data is written into the first node N. At this time, the voltage value of the first node Nis V=Vdata, where Vdata is a data voltage of the data signal line, and the signal of the first node Nhas a voltage jump from a voltage value of this phase compared to a voltage value of a previous phase. Therefore, under an action of the first capacitor Cand the second capacitor C, the signal of the third node Nalso has a voltage jump. At this time, the voltage value of the signal of the third node Nis V=Vref−Vth+(Vdata−Vref)*C/(C+C), where Cis a capacitance value of the first capacitor and Cis a capacitance value of the second capacitor. The signals of the second reset signal line Reset, the second scan signal line G, the first light-emitting signal line EMand the second light-emitting signal line EMare low-level signals, and the second transistor T, the fourth transistor T, the fifth transistor Tand the seventh transistor Tare turned off. In this phase, the light-emitting device L does not emit light.

4 2 3 2 1 1 1 2 3 8 4 4 2 5 3 3 1 1 1 1 1 1 2 2 7 3 5 1 1 1 2 1 2 4 6 A fourth phase Pis referred to as a second reset phase. The signals of the second reset signal line Reset, the third reset signal line Resetand the second light-emitting signal line EMare high-level signals, and the signals of the first reset signal line Reset, the first light-emitting signal line EM, the first scan signal line Gand the second scan signal line Gare low-level signals. The signal of the third reset signal line Resetis a high-level signal, the eighth transistor Tis turned on, and the signal of the initial signal line INIT is continuously written into the fourth node N, and the signal of the fourth node Nis continuously initialized (reset). The signal of the second light-emitting signal line EMis a high-level signal, the fifth transistor Tis turned on, the voltage of the signal of the third node Nis V=Vinit, where Vinit is a voltage value of the signal of the initial signal line, at this time, the first node Nis pulled down under an action of the first capacitor C, so that a voltage of the signal of the first node Nis V=Vdata−[Vref−Vth+(Vdata−Vref)*C/(C+C)]+Vinit, the signal of the second reset signal line Resetis a high-level signal, the seventh transistor Tis turned on, and the voltages of the signals of the third node Nand the fifth node Nremain consistent. The signals of the first reset signal line Reset, the first light-emitting signal line EM, the first scan signal line Gand the second scan signal line Gare low-level signals, and the first transistor T, the second transistor T, the fourth transistor Tand the sixth transistor Tare turned off. In this phase, the light-emitting device L does not emit light.

5 2 1 2 1 3 1 2 1 2 4 5 4 3 5 2 7 3 5 1 3 1 2 1 2 6 8 A fifth phase Pis a light-emitting phase, the signals of the second reset signal line Reset, the first light-emitting signal line EM, and the second light-emitting signal line EMare high-level signals, and the signals of the first reset signal line Reset, the third reset signal line Reset, the first scan signal line G, and the second scan signal line Gare low-level signals. The signals of the first light-emitting signal line EMand the second light-emitting signal line Resetare high-level signals, the fourth transistor Tand the fifth transistor Tare turned on, and the power supply voltage output by the first power line VDD provides a driving voltage to the first electrode of the light-emitting device L through the turned-on fourth transistor T, the third transistor T, and the fifth transistor T, to drive the light-emitting device L to emit light, the signal of the second reset signal line Resetis a high-level signal, the seventh transistor Tis turned on, and the voltages of the signals of the third node Nand the fifth node Nremain consistent. The signals of the first reset signal line Reset, the third reset signal line Reset, the first scan signal line G, and the second scan signal line Gare low-level signals, the first transistor T, the second transistor T, the sixth transistor T, and the eighth transistor Tare turned off. In this phase, the light-emitting device L emits light.

3 1 3 1 1 1 2 3 3 3 During a driving process of the pixel driving circuit, the driving current flowing through the third transistor T(a driving transistor) is determined by a voltage difference between the control electrode (also the first node N) and the second electrode (also the third node N) thereof. Because the voltage value Vof the signal of the first node is equal to Vdata−[Vref−Vth+(Vdata−Vref)*C/(C+C)]+Vinit, the voltage value Vof the signal of the third node Nis equal to Vinit, so the driving current of the third transistor Tis:

I=K Vgs−Vth =K*[V V Vth V V C C +C Vth] =K C C +C V V 2 2 2 *()data−[ref−+(data−ref)*1/(12)]−*[(2/(12))*(data−ref)].

3 3 3 Where I is a driving current flowing through the third transistor T, that is, the driving current for driving the light-emitting device L, K is a constant, and Vgs is a voltage difference between the control electrode of the third transistor Tand the second electrode of the third transistor T.

3 3 3 It can be seen from a derivation result of the above current formula that in the light-emitting phase, the driving current of the third transistor Tis no longer affected by a threshold voltage of the third transistor T, thereby eliminating the impact of the threshold voltage of the third transistor Ton the driving current, which can ensure a uniform display brightness of a display product and improve the display effect of the entire display product.

46 FIG. 41 FIG. 41 FIG. 41 FIG. 1 7 1 2 is an operating timing diagram of the pixel driving circuit provided in. An exemplary embodiment of the present disclosure is illustrated below through the operating process of the pixel driving circuit shown in. The pixel driving circuit inincludes seven transistors (a first transistor Tto a seventh transistor T) and two capacitors (a first capacitor Cand a second capacitor C), and all the seven transistors are N-type transistors.

41 FIG. In an exemplary implementation, the operating process of the pixel driving circuit provided inmay include the following phases.

1 2 2 1 2 1 1 2 2 1 1 1 1 2 2 5 6 7 5 3 4 3 4 5 3 4 5 1 1 1 4 A first phase Pis referred to as a first reset phase, the signals of the second scan signal line G, the second light-emitting signal line EM, the first reset signal line Resetand the second reset signal line Resetare high-level signals, and the signals of the first scan signal line Gand the first light-emitting signal line EMare low-level signals. The signal of the second scan signal line Gis a high-level signal, the second transistor Tis turned on, the signal of the reference signal line REF is written into the first node N, the signal of the first node Nis initialized (reset), and original charges in the first node Nare cleared. The signals of the first reset signal line Reset, the second reset signal line Reset, and the second light-emitting signal line EMare high-level signals, the fifth transistor T, the sixth transistor T, and the seventh transistor Tare turned on, the signal of the auxiliary signal line VX is sequentially written into the fifth node N, the third node N, and the fourth node N, the signals of the third node N, the fourth node N, and the fifth node Nare initialized (reset), and original charges in the third node N, the fourth node N, and the fifth node Nare cleared. The signals of the first scan signal line Gand the first light-emitting signal line EMare low-level signals, and the first transistor Tand the fourth transistor Tare turned off. In this phase, the light-emitting device L does not emit light.

2 1 2 1 2 1 2 1 6 5 5 2 2 1 1 4 3 4 2 3 3 3 3 1 1 3 2 1 2 1 5 A second phase Pis a threshold compensation phase, the signals of the first reset signal line Reset, the second scan signal line G, and the first light-emitting signal line EMare high-level signals, and the signals of the second reset signal line Reset, the first scan signal line G, and the second light-emitting signal line EMare low-level signals. The signal of the first reset signal line Resetis a high-level signal, the sixth transistor Tis turned on, and the signal of the auxiliary signal line VX is continuously written into the fifth node N, and the signal of the fifth node Nis continuously initialized (reset). The signal of the second scan signal line Gis a high-level signal, the second transistor Tis turned on, the signal of the reference signal line REF is continuously provided to the first node N, the signal of the first light-emitting signal line EMis a high-level signal, the fourth transistor Tis turned on, and the signal of the first power line VDD is written into the third node Nthrough the turned-on fourth transistor T, the second node Nand the turned-on third transistor T, until the voltage Vof the signal of the third node Nis equal to Vref−Vth, where Vref is a voltage value of the signal of the initial signal line REF, Vth is a threshold voltage of the third transistor T, at this time, the first capacitor Cstores a voltage difference Vth of the signals of the first node Nand the third node N. The signals of the second reset signal line Reset, the first scan signal line Gand the second light-emitting signal line EMare low-level signals, and the first transistor T, the fifth transistor Tand the seventh transistor are turned off. In this phase, the light-emitting device L does not emit light.

3 1 1 2 2 1 2 1 6 5 5 1 1 1 1 1 1 1 2 3 3 3 1 1 2 1 2 2 2 1 2 2 4 5 7 A third phase Pis a data writing phase, the signals of the first reset signal line Resetand the first scan signal line Gare high-level signals, the signals of the second reset signal line Reset, the second scan signal line G, the first light-emitting signal line EMand the second light-emitting signal line EMare low-level signals, and the data signal line Data outputs the data voltage. The signal of the first reset signal line Resetis a high-level signal, the sixth transistor Tis turned on, the signal of the auxiliary signal line VX is continuously written into the fifth node N, and the signal of the fifth node Nis continuously initialized (reset). The signal of the first scan signal line Gis a high-level signal, the first transistor Tis turned on, and the data voltage of the data signal line Data is written into the first node N. At this time, the voltage value of the first node NVis equal to Vdata, where Vdata is a data voltage of the data signal line, and the signal of the first node Nhas a voltage jump from the voltage value of this phase compared to the voltage value of a previous phase. Therefore, under an action of the first capacitor Cand the second capacitor C, the signal of the third node Nalso has a voltage jump. At this time, the voltage value Vof the signal of the third node Nis equal to Vref−Vth+(Vdata−Vref)*C/(C+C), where Cis a capacitance value of the first capacitor and Cis a capacitance value of the second capacitor. The signals of the second reset signal line Reset, the second scan signal line G, the first light-emitting signal line EMand the second light-emitting signal line EMare low-level signals, and the second transistor T, the fourth transistor T, the fifth transistor Tand the seventh transistor Tare turned off. In this phase, the light-emitting device L does not emit light.

4 2 2 1 1 1 2 2 5 3 3 1 1 1 1 1 1 2 2 7 3 5 1 1 1 2 1 2 4 6 A fourth phase Pis referred to as a second reset phase. The signals of the second reset signal line Resetand the second light-emitting signal line EMare high-level signals, and the signals of the first reset signal line Reset, the first light-emitting signal line EM, the first scan signal line G, and the second scan signal line Gare low-level signals. The signal of the second light-emitting signal line EMis a high-level signal, the fifth transistor Tis turned on, the voltage Vof the signal of the third node Nis equal to Vinit, Vinit is a voltage value of the signal of the initial signal line, at this time, the first node Nis pulled down under the action of the first capacitor C, so that the voltage Vof the signal of the first node Nis equal to Vdata−[Vref−Vth+(Vdata−Vref)*C/(C+C)]+Vinit, the signal of the second reset signal line Resetis a high-level signal, the seventh transistor Tis turned on, and the voltages of the signals of the third node Nand the fifth node Nremain consistent. The signals of the first reset signal line Reset, the first light-emitting signal line EM, the first scan signal line Gand the second scan signal line Gare low-level signals, and the first transistor T, the second transistor T, the fourth transistor Tand the sixth transistor Tare turned off. In this phase, the light-emitting device L does not emit light.

5 2 1 2 1 1 2 1 2 4 5 4 3 5 2 7 3 5 1 1 2 1 2 6 A fifth phase Pis a light-emitting phase, the signals of the second reset signal line Reset, the first light-emitting signal line EMand the second light-emitting signal line EMare high-level signals, and the signals of the first reset signal line Reset, the first scan signal line Gand the second scan signal line Gare low-level signals. The signals of the first light-emitting signal line EMand the second light-emitting signal line EMare high-level signals, the fourth transistor Tand the fifth transistor Tare turned on, and the power supply voltage output by the first power line VDD provides a driving voltage to the first electrode of the light-emitting device L through the turned-on fourth transistor T, the third transistor Tand the fifth transistor T, to drive the light-emitting device L to emit light, the signal of the second reset signal line Resetis a high-level signal, the seventh transistor Tis turned on, and the voltages of the signals of the third node Nand the fifth node Nremain consistent. The signals of the first reset signal line Reset, the first scan signal line Gand the second scan signal line Gare low-level signals, and the first transistor T, the second transistor Tand the sixth transistor Tare turned off. In this phase, the light-emitting device L emits light.

3 1 3 1 1 1 2 3 3 3 During a driving process of the pixel driving circuit, the driving current flowing through the third transistor T(a driving transistor) is determined by a voltage difference between the control electrode (also the first node N) and the second electrode (also the third node N) thereof. Because the voltage value Vof the signal of the first node is equal to Vdata−[Vref−Vth+(Vdata−Vref)*C/(C+C)]+Vinit, the voltage value Vof the signal of the third node Nis equal to Vinit, the driving current of the third transistor Tis:

I=K Vgs−Vth =K*[V V Vth V V C C +C Vth] =K C C +C V V 2 2 2 *()data−[ref−+(data−ref)*1/(12)]−*[(2/(12))*(data−ref)].

3 3 Where I is a driving current flowing through the third transistor T, that is, the driving current for driving the light-emitting device L, K is a constant, and Vgs is a voltage difference between the control electrode and the second electrode of the third transistor T.

3 3 3 It can be seen from a derivation result of the above current formula that in the light-emitting phase, the driving current of the third transistor Tis no longer affected by a threshold voltage of the third transistor T, thereby eliminating the impact of the threshold voltage of the third transistor Ton the driving current, which may ensure a uniform display brightness of a display product and improve the display effect of the entire display product.

47 FIG. 42 FIG. 42 FIG. 42 FIG. 1 6 8 1 2 is an operating timing diagram of the pixel driving circuit provided in. An exemplary embodiment of the present disclosure is illustrated below by an operating process of the pixel driving circuit shown in. The pixel driving circuit inincludes seven transistors (a first transistor Tto a sixth transistor T, and an eighth transistor T) and two capacitors (a first capacitor Cand a second capacitor C), and all the seven transistors are N-type transistors.

42 FIG. In an exemplary embodiment, the operating process of the pixel driving circuit provided inmay include the following phases.

1 2 2 1 3 1 1 2 2 1 1 1 1 6 5 5 5 2 3 5 8 3 4 1 3 3 3 2 2 3 4 2 3 4 1 1 1 4 A first phase Pis referred to as a first reset phase, the signals of the second scan signal line G, the second light-emitting signal line EM, the first reset signal line Resetand the third reset signal line Resetare high-level signals, and the signals of the first scan signal line Gand the first light-emitting signal line EMare low-level signals. The signal of the second scan signal line Gis a high-level signal, the second transistor Tis turned on, the signal of the reference signal line REF is written into the first node N, the signal of the first node Nis initialized (reset), and original charges at the first node Nare cleared. The signal of the first reset signal line Resetis a high-level signal, the sixth transistor Tis turned on, the signal of the auxiliary signal line VX is written into the fifth node N, the signal of the fifth node Nis initialized (reset), and original charges at the fifth node Nare cleared. The signals of the second light-emitting signal line EMand the third reset signal line Resetare high-level signals, the fifth transistor Tand the eighth transistor Tare turned on, and the signal of the initial signal line INIT is written into the third node Nand the fourth node Nrespectively. Because the difference between the voltage value of the signal of the first node Nand the voltage value of the signal of the third node Nare greater than the threshold voltage of the third transistor T, at this time, the third transistor Tis turned on, the signal of the initial signal line INIT is written into the second node N, the signals of the second node N, the third node Nand the fourth node Nare initialized (reset), and original charges in the second node N, the third node Nand the fourth node Nare cleared. The signals of the first scan signal line Gand the first light-emitting signal line EMare low-level signals, and the first transistor Tand the fourth transistor Tare turned off. In this phase, the light-emitting device L does not emit light.

2 1 3 2 1 1 2 1 6 5 5 3 8 4 4 2 2 1 1 4 3 4 2 3 3 3 3 1 1 3 1 2 1 5 A second phase Pis a threshold compensation phase, the signals of the first reset signal line Reset, the third reset signal line Reset, the second scan signal line Gand the first light-emitting signal line EMare high-level signals, and the signals of the first scan signal line Gand the second light-emitting signal line EMare low-level signals. The signal of the first reset signal line Resetis a high-level signal, the sixth transistor Tis turned on, the signal of the auxiliary signal line VX is continuously written into the fifth node N, and the signal of the fifth node Nis continuously initialized (reset). The signal of the third reset signal line Resetis a high-level signal, the eighth transistor Tis turned on, the signal of the initial signal line INIT is continuously written into the fourth node N, and the signal of the fourth node Nis continuously initialized (reset). The signal of the second scan signal line Gis a high-level signal, the second transistor Tis turned on, the signal of the reference signal line REF is continuously provided to the first node N, the signal of the first light-emitting signal line EMis a high-level signal, the fourth transistor Tis turned on, and the signal of the first power line VDD is written into the third node Nthrough the turned-on fourth transistor T, the second node Nand the turned-on third transistor T, until the voltage Vof the signal of the third node Nis equal to Vref−Vth, Vref is a voltage value of the signal of the initial signal line REF, Vth is a threshold voltage of the third transistor T, at this time, the first capacitor Cstores a voltage difference Vth of the signals of the first node Nand the third node N. The signals of the first scan signal line Gand the second light-emitting signal line EMare low-level signals, and the first transistor Tand the fifth transistor Tare turned off. In this phase, the light-emitting device L does not emit light.

3 1 3 1 2 1 2 1 6 5 5 3 8 4 4 1 1 1 1 1 1 1 2 3 3 3 1 1 2 1 2 2 1 2 2 4 5 A third phase Pis a data writing phase, the signals of the first reset signal line Reset, the third reset signal line Resetand the first scan signal line Gare high-level signals, the signals of the second scan signal line G, the first light-emitting signal line EMand the second light-emitting signal line EMare low-level signals, and the data signal line Data outputs the data voltage. The signal of the first reset signal line Resetis a high-level signal, the sixth transistor Tis turned on, the signal of the auxiliary signal line VX is continuously written into the fifth node N, and the signal of the fifth node Nis continuously initialized (reset). The signal of the third reset signal line Resetis a high-level signal, the eighth transistor Tis turned on, the signal of the initial signal line INIT is continuously written into the fourth node N, and the signal of the fourth node Nis continuously initialized (reset). The signal of the first scan signal line Gis a high-level signal, the first transistor Tis turned on, and the data voltage of the data signal line Data is written into the first node N. At this time, the voltage value Vof the first node Nis equal to Vdata, Vdata is a data voltage of the data signal line, and the signal of the first node Nhas a voltage jump from a voltage value of this phase compared to the voltage value of a previous phase. Therefore, under an action of the first capacitor Cand the second capacitor C, the signal of the third node Nalso has a voltage jump. At this time, the voltage value Vof the signal of the third node Nis equal to Vref−Vth+(Vdata−Vref)*C/(C+C), where Cis a capacitance value of the first capacitor and Cis a capacitance value of the second capacitor. The signals of the second scan signal line G, the first light-emitting signal line EMand the second light-emitting signal line EMare low-level signals, and the second transistor T, the fourth transistor Tand the fifth transistor Tare turned off. In this phase, the light-emitting device L does not emit light.

4 1 3 2 1 1 2 3 8 4 4 2 5 3 3 1 1 1 1 1 1 2 1 6 3 5 1 1 1 2 1 2 4 A fourth phase Pis referred to as a second reset phase. The first reset signal line Reset, the third reset signal line Resetand the second light-emitting signal line EMare high-level signals, and the signals of the first light-emitting signal line EM, the first scan signal line Gand the second scan signal line Gare low-level signals. The signal of the third reset signal line Resetis a high-level signal, the eighth transistor Tis turned on, and the signal of the initial signal line INIT is continuously written into the fourth node N, and the signal of the fourth node Nis continuously initialized (reset). The signal of the second light-emitting signal line EMis a high-level signal, the fifth transistor Tis turned on, and the voltage of the signal of the third node Nis V, which is equal to Vinit, Vinit is a voltage value of the signal of the initial signal line. At this time, the first node Nis pulled down under the action of the first capacitor C, so that the voltage of the signal of the first node Nis V, which is equal to Vdata−[Vref−Vth+(Vdata−Vref)*C/(C+C)]+Vinit, the signal of the first reset signal line Resetis a high-level signal, the sixth transistor Tis turned on, and the voltages of the third node Nand the fifth node Nsignals remain consistent. The signals of the first reset signal line Reset, the first light-emitting signal line EM, the first scan signal line Gand the second scan signal line Gare low-level signals, and the first transistor T, the second transistor Tand the fourth transistor Tare turned off. In this phase, the light-emitting device L does not emit light.

5 1 1 2 3 1 2 1 2 4 5 4 3 5 1 6 3 5 3 1 2 1 2 8 A fifth phase Pis a light-emitting phase, the signals of the first reset signal line Reset, the first light-emitting signal line EMand the second light-emitting signal line EMare high-level signals, and the signals of the third reset signal line Reset, the first scan signal line Gand the second scan signal line Gare low-level signals. The signals of the first light-emitting signal line EMand the second light-emitting signal line EMare high-level signals, the fourth transistor Tand the fifth transistor Tare turned on, and the power supply voltage output by the first power line VDD provides a driving voltage to the first electrode of the light-emitting device L through the turned-on fourth transistor T, the third transistor Tand the fifth transistor T, to drive the light-emitting device L to emit light, the signal of the first reset signal line Resetis a high-level signal, the sixth transistor Tis turned on, and the voltages of the signals of the third node Nand the fifth node Nremain consistent. The signals of the third reset signal line Reset, the first scan signal line Gand the second scan signal line Gare low-level signals, and the first transistor T, the second transistor Tand the eighth transistor Tare turned off. In this phase, the light-emitting device L emits light.

3 3 1 3 3 1 1 1 2 3 3 3 During a driving process of the pixel driving circuit, the driving current flowing through the third transistor T(a driving transistor) is determined by a voltage difference between the control electrode of the third transistor T(also the first node N) and the second electrode of the third transistor T(also the third node N). Because the voltage value of the signal of the first node is V, which is equal to Vdata−[Vref−Vth+(Vdata−Vref)*C/(C+C)]+Vinit, and the voltage value Vof the signal of the third node Nis equal to Vinit, the driving current of the third transistor Tis:

I=K Vgs−Vth =K*[V V Vth V V C C +C Vth] =K C C +C V V 2 2 2 *()data−[ref−+(data−ref)*1/(12)]−*[(2/(12))*(data−ref)].

3 3 3 Where I is a driving current flowing through the third transistor T, that is, the driving current for driving the light-emitting device L, K is a constant, and Vgs is a voltage difference between the control electrode of the third transistor Tand the second electrode of the third transistor T.

3 3 3 It can be seen from a derivation result of the above current formula that in the light-emitting phase, the driving current of the third transistor Tis no longer affected by a threshold voltage of the third transistor T, thereby eliminating the impact of the threshold voltage of the third transistor Ton the driving current, which can ensure a uniform display brightness of a display product and improve the display effect of the entire display product.

39 42 FIGS.to 3 5 2 2 For the pixel driving circuit provided in, in the fourth and fifth phases, the signals of the third node Nand the fifth node Nat both terminals of the second capacitor Cremain consistent, so that the third node of the pixel driving circuit will not be affected by a coupling effect of the second capacitor Cin the fifth phase, which may improve the stability of the driving current of the pixel driving circuit and improve the reliability of the pixel driving circuit.

48 FIG. 43 FIG. 44 FIG. 43 FIG. 44 FIG. 43 FIG. 44 FIG. 1 6 8 1 2 is an operating timing diagram of the pixel driving circuit provided inand. An exemplary embodiment of the present disclosure is illustrated by an operating process of the pixel driving circuit shown inand. The pixel driving circuit inandincludes seven transistors (a first transistor Tto a sixth transistor T, and an eighth transistor T) and two capacitors (a first capacitor Cand a second capacitor C), and all the seven transistors are N-type transistors.

43 FIG. 44 FIG. In an exemplary implementation, the operating process of the pixel driving circuit provided inandmay include the following phases.

1 2 2 1 3 1 1 2 2 1 1 1 1 6 5 5 5 2 3 5 8 3 4 1 3 3 3 2 2 3 4 2 3 4 1 1 1 4 A first phase Pis referred to as a first reset phase, the signals of the second scan signal line G, the second light-emitting signal line EM, the first reset signal line Resetand the third reset signal line Resetare high-level signals, and the signals of the first scan signal line Gand the first light-emitting signal line EMare low-level signals. The signal of the second scan signal line Gis a high-level signal, the second transistor Tis turned on, the signal of the reference signal line REF is written into the first node N, the signal of the first node Nis initialized (reset), and original charges at the first node Nare cleared. The signal of the first reset signal line Resetis a high-level signal, the sixth transistor Tis turned on, the signal of the auxiliary signal line VX is written into the fifth node N, the signal of the fifth node Nis initialized (reset), and original charges at the fifth node Nare cleared. The signals of the second light-emitting signal line EMand the third reset signal line Resetare high-level signals, the fifth transistor Tand the eighth transistor Tare turned on, and the signal of the initial signal line INIT is written into the third node Nand the fourth node Nrespectively. Because difference between the voltage value of the signal of the first node Nand the voltage value of the signal of the third node Nare greater than the threshold voltage of the third transistor T, at this time, the third transistor Tis turned on, and the signal of the initial signal line INIT is written into the second node N, and the signals of the second node N, the third node Nand the fourth node Nare initialized (reset), and original charges in the second node N, the third node Nand the fourth node Nare cleared. The signals of the first scan signal line Gand the first light-emitting signal line EMare low-level signals, and the first transistor Tand the fourth transistor Tare turned off. In this phase, the light-emitting device L does not emit light.

2 1 3 2 1 1 2 1 6 5 5 3 8 4 4 2 2 1 1 4 3 4 2 3 3 3 3 1 1 3 1 2 1 5 A second phase Pis a threshold compensation phase, the signals of the first reset signal line Reset, the third reset signal line Reset, the second scan signal line G, and the first light-emitting signal line EMare high-level signals, and the signals of the first scan signal line Gand the second light-emitting signal line EMare low-level signals. The signal of the first reset signal line Resetis a high-level signal, the sixth transistor Tis turned on, the signal of the auxiliary signal line VX is continuously written into the fifth node N, and the signal of the fifth node Nis continuously initialized (reset). The signal of the third reset signal line Resetis a high-level signal, the eighth transistor Tis turned on, the signal of the initial signal line INIT is continuously written into the fourth node N, and the signal of the fourth node Nis continuously initialized (reset). The signal of the second scan signal line Gis a high-level signal, the second transistor Tis turned on, the signal of the reference signal line REF is continuously provided to the first node N, the signal of the first light-emitting signal line EMis a high-level signal, the fourth transistor Tis turned on, and the signal of the first power line VDD is written into the third node Nthrough the turned-on fourth transistor T, the second node Nand the turned-on third transistor T, until the voltage Vof the signal of the third node Nis equal to Vref−Vth, Vref is a voltage value of the signal of the initial signal line REF, Vth is a threshold voltage of the third transistor T, at this time, the first capacitor Cstores a voltage difference Vth between the signal of the first node Nand the signal of the third node N. The signals of the first scan signal line Gand the second light-emitting signal line EMare low-level signals, and the first transistor Tand the fifth transistor Tare turned off. In this phase, the light-emitting device L does not emit light.

3 1 3 1 2 1 2 1 6 5 5 3 8 4 4 1 1 1 1 1 1 1 2 3 3 3 1 1 2 1 2 2 1 2 2 4 5 A third phase Pis a data writing phase, the signals of the first reset signal line Reset, the third reset signal line Resetand the first scan signal line Gare high-level signals, and the signals of the second scan signal line G, the first light-emitting signal line EMand the second light-emitting signal line EMare low-level signals, and the data signal line Data outputs the data voltage. The signal of the first reset signal line Resetis a high-level signal, the sixth transistor Tis turned on, the signal of the auxiliary signal line VX is continuously written into the fifth node N, and the signal of the fifth node Nis continuously initialized (reset). The signal of the third reset signal line Resetis a high-level signal, the eighth transistor Tis turned on, the signal of the initial signal line INIT is continuously written into the fourth node N, and the signal of the fourth node Nis continuously initialized (reset). The signal of the first scan signal line Gis a high-level signal, the first transistor Tis turned on, and the data voltage of the data signal line Data is written into the first node N. At this time, the voltage value Vof the first node Nis equal to Vdata, Vdata is a data voltage of the data signal line, and the signal of the first node Nhas a voltage jump from a voltage value of this phase compared to a voltage value of a previous phase. Therefore, under an action of the first capacitor Cand the second capacitor C, the signal of the third node Nalso has a voltage jump. At this time, the voltage value Vof the signal of the third node Nis equal to Vref−Vth+(Vdata−Vref)*C/(C+C), Cis a capacitance value of the first capacitor and Cis a capacitance value of the second capacitor. The signals of the second scan signal line G, the first light-emitting signal line EMand the second light-emitting signal line EMare low-level signals, and the second transistor T, the fourth transistor Tand the fifth transistor Tare turned off. In this phase, the light-emitting device L does not emit light.

4 3 2 1 1 1 2 3 8 4 4 2 5 3 3 1 1 1 1 1 1 2 1 1 1 2 1 2 4 6 A fourth phase Pis referred to as a second reset phase. The signals of the third reset signal line Resetand the second light-emitting signal line EMare high-level signals, and the signals of the first reset signal line Reset, the first light-emitting signal line EM, the first scan signal line G, and the second scan signal line Gare low-level signals. The signal of the third reset signal line Resetis a high-level signal, the eighth transistor Tis turned on, and the signal of the initial signal line INIT is continuously written into the fourth node N, and the signal of the fourth node Nis continuously initialized (reset). The signal of the second light-emitting signal line EMis a high-level signal, the fifth transistor Tis turned on, and the voltage Vof the signal of the third node Nis equal to Vinit, and Vinit is a voltage value of the signal of the initial signal line. At this time, the first node Nis pulled down under an action of the first capacitor C, so that the voltage Vof the signal of the first node Nis equal to Vdata−[Vref−Vth+(Vdata−Vref)*C/(C+C)]+Vinit. The signals of the first reset signal line Reset, the first light-emitting signal line EM, the first scan signal line Gand the second scan signal line Gare low-level signals, and the first transistor T, the second transistor T, the fourth transistor Tand the sixth transistor Tare turned off. In this phase, the light-emitting device L does not emit light.

5 1 2 1 3 1 2 1 2 4 5 4 3 5 1 6 3 5 1 3 1 2 1 2 6 8 A fifth phase Pis a light-emitting phase, the signals of the first light-emitting signal line EMand the second light-emitting signal line EMare high-level signals, and the signals of the first reset signal line Reset, the third reset signal line Reset, the first scan signal line Gand the second scan signal line Gare low-level signals. The signals of the first light-emitting signal line EMand the second light-emitting signal line EMare high-level signals, the fourth transistor Tand the fifth transistor Tare turned on, and the power supply voltage output by the first power line VDD provides a driving voltage to the first electrode of the light-emitting device L through the turned-on fourth transistor T, the third transistor Tand the fifth transistor T, to drive the light-emitting device L to emit light, the signal of the first reset signal line Resetis a high-level signal, the sixth transistor Tis turned on, and the voltages of the signals of the third node Nand the fifth node Nremain consistent. The signals of the first reset signal line Reset, the third reset signal line Reset, the first scan signal line Gand the second scan signal line Gare low-level signals, and the first transistor T, the second transistor T, the sixth transistor Tand the eighth transistor Tare turned off. In this phase, the light-emitting device L emits light.

3 3 1 3 3 1 1 1 2 3 3 3 During a driving process of the pixel driving circuit, the driving current flowing through the third transistor T(a driving transistor) is determined by a voltage difference between the control electrode of the third transistor T(also the first node N) and the second electrode (also the third node N) of the third transistor T. Because the voltage value Vof the signal of the first node is equal to Vdata−[Vref−Vth+(Vdata−Vref)*C/(C+C)]+Vinit, and the voltage value Vof the signal of the third node Nis equal to Vinit, the driving current of the third transistor Tis:

I=K Vgs−Vth =K*[V V Vth V V C C +C Vth] =K C C +C V V 2 2 2 *()data−[ref−+(data−ref)*1/(12)]−*[(2/(12))*(data−ref)].

3 3 3 Where I is a driving current flowing through the third transistor T, that is, the driving current for driving the light-emitting device L, K is a constant, and Vgs is a voltage difference between the control electrode of the third transistor Tand the second electrode of the third transistor T.

3 3 3 It can be seen from a derivation result of the above current formula that in the light-emitting phase, the driving current of the third transistor Tis no longer affected by a threshold voltage of the third transistor T, thereby eliminating the impact of the threshold voltage of the third transistor Ton the driving current, which may ensure a uniform display brightness of a display product and improve the display effect of the entire display product.

43 FIG. 44 FIG. 2 3 6 2 For the pixel driving circuit provided inand, in the fourth phase and the fifth phase, the second capacitor Cis disconnected from the third node Nthrough the sixth transistor Twhich is turned-off, so that the third node of the pixel driving circuit will not be affected by a coupling effect of the second capacitor Cin the fifth phase, which may improve the stability of the driving current of the pixel driving circuit and improve the reliability of the pixel driving circuit.

100 Step, providing, by a driving sub-circuit, a driving current to a third node under a control of signals of a first node and a second node. 200 1 Step, providing, by a first control sub-circuit, a signal of a data signal line or a reference signal line to the first node Nunder a control of signals of a first scan signal line and a second scan signal line. 300 Step, providing, by a second control sub-circuit, a signal of a first power line to the second node and providing a signal of the third node to a fourth node under a control of signals of a first light-emitting signal line and a second light-emitting signal line. 400 Step, controlling, by a third control sub-circuit, the signal of the third node under a control of a signal of a first reset signal line and a signal of an auxiliary signal line. 500 Step, storing, by a storage sub-circuit, a voltage difference between the signal of the first node and the signal of the third node. An embodiment of the present disclosure further provides a driving method for a pixel driving circuit, which is configured to drive the pixel driving circuit. The driving method for the pixel driving circuit may include:

41 41 FIG. 110 Step, in the first phase, valid level signals are provided to the second scan signal line, the second light-emitting signal line, the first reset signal line and the second reset signal line, the first control sub-circuit provides the signal of the reference signal line to the first node, the third control sub-circuit provides the signal of the auxiliary signal line to the fifth node, and provides the signal of the fifth node to the third node, and the second control sub-circuit provides the signal of the fourth node to the third node. 120 Step, in the second phase, valid level signals are provided to the first reset signal line, the second scan signal line and the first light-emitting signal line, the first control sub-circuit provides the signal of the reference signal line to the first node, the third control sub-circuit provides the signal of the auxiliary signal line to the fifth node, the second control sub-circuit provides the signal of the first power line to the second node to charge the first node, and the storage sub-circuit stores the voltage difference between the signal of the first node and the signal of the third node. 130 Step, in the third phase, the signals provided to the first reset signal line and the first scan signal line are high-level signals, the first control sub-circuit provides the signal of the data signal line to the first node, and the third control sub-circuit provides the signal of the auxiliary signal line to the fifth node. 140 Step, in the fourth phase, valid level signals are provided to the second reset signal line and the second light-emitting signal line, the third control sub-circuit provides the signal of the third node to the fifth node, and the second control sub-circuit provides the signal of the fourth node to the third node. 150 Step, in the fifth phase, valid level signals are provided to the second reset signal line, the first light-emitting signal line and the second light-emitting signal line, the second control sub-circuit provides the signal of the first power line to the second node, and provides the signal of the third node to the fourth node, the driving sub-circuit provides a driving current to the third node under control of the signal of the first node and the signal of the second node, and the third control sub-circuit provides the signal of the third node to the fifth node. An embodiment of the present disclosure further provides a driving method of a pixel driving circuit, which is configured to drive the pixel driving circuit provided in FIG.. An operating process of the pixel driving circuit includes: a first phase to a fifth phase. The driving method of the pixel driving circuit provided inmay include:

42 FIG. 42 FIG. 210 Step, in the first phase, valid level signals are provided to the second scan signal line, the second light-emitting signal line, the first reset signal line and the third reset signal line, the first control sub-circuit provides the signal of the reference signal line to the first node, the third control sub-circuit provides the signal of the auxiliary signal line to the fifth node, and provides the signal of the initial signal line to the fourth node, and the second control sub-circuit provides the signal of the fourth node to the third node; 220 Step, in the second phase, providing valid level signals to the first reset signal line, the third reset signal line, the second scan signal line and the first light-emitting signal line, the first control sub-circuit provides the signal of the reference signal line to the first node, the third control sub-circuit provides the signal of the auxiliary signal line to the fifth node, and provides the signal of the initial signal line to the fourth node, the second control sub-circuit provides the signal of the first power line to the second node to charge the first node, and the storage sub-circuit stores the voltage difference between the signal of the first node and the signal of the third node. 230 Step: in the third phase, the signals provided to the first reset signal line, the third reset signal line and the first scan signal line are high-level signals, the first control sub-circuit provides the signal of the data signal line to the first node, the third control sub-circuit provides the signal of the auxiliary signal line to the fifth node, and provides the signal of the initial signal line to the fourth node. 240 Step: in the fourth phase, valid level signals are provided to the first reset signal line, the third reset signal line and the second light-emitting signal line, the third control sub-circuit provides the signal of the initial signal line to the fourth node, and provides the signal of the auxiliary signal line to the fifth node, the second control sub-circuit provides the signal of the fourth node to the third node. 250 Step: in the fifth phase, valid level signals are provided to the first reset signal line, the first light-emitting signal line and the second light-emitting signal line, the second control sub-circuit provides the signal of the first power line to the second node, and the signal of the third node to the fourth node, the driving sub-circuit provides the driving current to the third node under the control of the signal of the first node and the signal of the second node, and the third control sub-circuit provides the signal of the auxiliary signal line to the fifth node. An embodiment of the present disclosure further provides a driving method of a pixel driving circuit, which is configured to drive the pixel driving circuit provided in. An operating process of the pixel driving circuit includes: the first phase to the fifth phase. The driving method of the pixel driving circuit provided inmay include:

39 FIG. 40 FIG. 39 FIG. 40 FIG. 310 Step, in the first phase, valid level signals are provided to the second scan signal line, the second light-emitting signal line, the first reset signal line and the third reset signal line, the first control sub-circuit provides the signal of the reference signal line to the first node, the third control sub-circuit provides the signal of the auxiliary signal line to the fifth node, and provides the signal of the initial signal line to the fourth node, and the second control sub-circuit provides the signal of the fourth node to the third node. 320 Step, in the second phase, valid level signals are provided to the first reset signal line, the third reset signal line, the second scan signal line and the first light-emitting signal line, the first control sub-circuit provides a signal of the reference signal line to the first node, the third control sub-circuit provides a signal of the auxiliary signal line to the fifth node, and provides a signal of the initial signal line to the fourth node, the second control sub-circuit provides a signal of the first power line to the second node to charge the first node, and the storage sub-circuit stores the voltage difference between the signal of the first node and the signal of the third node. 330 Step, in the third phase, the signals to the first reset signal line, the third reset signal line and the first scan signal line are high-level signals, the first control sub-circuit provides the signal of the data signal line to the first node, the third control sub-circuit provides the signal of the auxiliary signal line to the fifth node, and provides the signal of the initial signal line to the fourth node. 340 Step, in the fourth phase, the second reset signal line, the third reset signal line and the second light-emitting signal line are provided with valid level signals, the third control sub-circuit provides the signal of the initial signal line to the fourth node, and provides the signal of the third node to the fifth node, and the second control sub-circuit provides the signal of the fourth node to the third node. 350 Step, in the fifth phase, the second reset signal line, the first light-emitting signal line and the second light-emitting signal line are provided with valid level signals, the second control sub-circuit provides the signal of the first power line to the second node, and provides the signal of the third node to the fourth node. The driving sub-circuit provides a driving current to the third node under the control of the signal of the first node and of the signal of the second node, and the third control sub-circuit provides the signal of the third node to the fifth node. An embodiment of the present disclosure further provides a driving method of a pixel driving circuit, which is configured to drive the pixel driving circuit provided inand. An operating process of the pixel driving circuit includes: a first phase to a fifth phase. The driving method of the pixel driving circuit provided inandmay include:

43 FIG. 44 FIG. 43 FIG. 44 FIG. 410 Step, in the first phase, the second scan signal line, the second light-emitting signal line, the first reset signal line and the third reset signal line are provided with valid level signals, the first control sub-circuit provides the signal of the reference signal line to the first node, the third control sub-circuit provides the signal of the third node to the fifth node, and provides the signal of the initial signal line to the fourth node, and the second control sub-circuit provides the signal of the fourth node to the third node. 420 Step, in the second phase, valid level signals are provided to the first reset signal line, the third reset signal line, the second scan signal line and the first light-emitting signal line, the first control sub-circuit provides the signal of the reference signal line to the first node, the third control sub-circuit provides the signal of the third node to the fifth node, and provides the signal of the initial signal line to the fourth node, the second control sub-circuit provides the signal of the first power line to the second node to charge the first node, and the storage sub-circuit stores the voltage difference between the signal of the first node and the signal of the third node. 430 Step, in the third phase, the signals provided to the first reset signal line, the third reset signal line and the first scan signal line are high-level signals, the first control sub-circuit provides the signal of the data signal line to the first node, the third control sub-circuit provides the signal of the initial signal line to the fourth node, and provides the signal of the third node to the fifth node. 440 Step: in the fourth phase, valid level signals are provided to the third reset signal line and the second light-emitting signal line, the third control sub-circuit provides the signal of the initial signal line to the fourth node, and the second control sub-circuit provides the signal of the fourth node to the third node. 450 Step: in the fifth phase, valid level signals are provided to the first light-emitting signal line and the second light-emitting signal line, the second control sub-circuit provides the signal of the first power line to the second node, and provides the signal of the third node to the fourth node. The driving sub-circuit provides a driving current to the third node under the control of the signal of the first node and the signal of the second node. An embodiment of the present disclosure further provides a driving method of a pixel driving circuit, which is configured to drive the pixel driving circuit provided inand. An operating process of the pixel driving circuit includes: a first phase to a fifth phase. The driving method of the pixel driving circuit provided inandmay include:

At least one embodiment of the present disclosure further provides a display apparatus, which includes a pixel circuit provided by any embodiment of the present disclosure. The display apparatus may be, for example, an organic light-emitting diode display apparatus, a quantum-dot light-emitting diode display apparatus, or other types of apparatuses with display functions. The embodiments of the present disclosure do not limit this.

Other structures and functions of the display apparatus provided by the embodiments of the present disclosure may be implemented with reference to conventional technologies, and the embodiments of the present disclosure are not limited thereto. For technical effects of the display apparatus provided by the embodiments of the present disclosure, please refer to the above description of the technical effects of the pixel circuit provided by the embodiments of the present disclosure, which will not be repeated here.

For example, the display apparatus provided by at least one embodiment of the present disclosure may be a display panel, a mobile phone, a tablet computer, a television, a display, a laptop, a digital photo frame, a navigator, or any other product or component with a display function, and the embodiments of the present disclosure do not limit this.

For example, the display apparatus provided by the embodiments of the present disclosure has a display region, and the display region is provided with a plurality of pixel driving circuits.

In an exemplary embodiment, the display apparatus may include a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array, the timing controller is connected to the data driver respectively, the scan driver, and the light-emitting driver, the data driver is connected to a plurality of data signal lines respectively, the scan driver is connected to a plurality of scan signal lines respectively, and the light-emitting driver is connected to a plurality of light-emitting signal lines respectively. The pixel array may include a plurality of sub-pixels, at least one sub-pixel may include a circuit unit and a light-emitting device connected to the circuit unit, the circuit unit may include a pixel driving circuit, and the pixel driving circuit may be respectively connected to the scan signal line, the light-emitting signal line, and the data signal line.

The scan signal line includes: a first scan signal line, a second scan signal line, a first reset signal line, a second reset signal line, and a third reset signal line. The light-emitting signal line includes: a first light-emitting signal line and a second light-emitting signal line.

In an exemplary implementation, the timing controller may provide a grayscale value and a control signal suitable for a specification of the data driver to the data driver, provide a clock signal, a scan start signal, and the like suitable for a specification of the scan driver to the scan driver, and provide a clock signal, an emission stop signal, and the like suitable for a specification of the light-emitting driver to the light-emitting driver.

In an exemplary implementation, the data driver may generate a data voltage to be provided to the data signal line using the grayscale value and the control signal received from the timing controller. For example, the data driver may sample the grayscale value using the clock signal, and apply the data voltage corresponding to the grayscale value to the data signal line in units of pixel rows.

In an exemplary implementation, the scan driver may generate a scan signal to be provided to the scan signal line by receiving a clock signal, a scan start signal, and the like from the timing controller. For example, the scan driver may sequentially provide a scan signal having a turn-on level pulse to the scan signal line. For example, the scan driver may be constructed in a form of a shift register, and may generate a scan signal by sequentially transmitting a scan start signal provided in a form of a turn-on level pulse to a next-level circuit under control of a clock signal.

In an exemplary implementation, the light-emitting driver may generate an emission signal to be provided to the light-emitting signal line by receiving a clock signal, an emission stop signal and the like from a timing controller. For example, the light-emitting driver may sequentially provide an emission signal having a turn-off level pulse to the light-emitting signal line. For example, the light-emitting driver may be constructed in the form of a shift register, and may generate an emission signal by sequentially transmitting an emission stop signal provided in a form of an turn-off level pulse to a next-level circuit under the control of a clock signal.

In an exemplary implementation, the display substrate may include a plurality of pixel units P arranged in a matrix, at least one of the plurality of pixel units P includes a first sub-pixel emitting a first color light, a second sub-pixel emitting a second color light, and a third sub-pixel emitting a third color light, and the first sub-pixel, the second sub-pixel, and the third sub-pixel each include a pixel driving circuit and a light-emitting device. The pixel driving circuits in the first sub-pixel, the second sub-pixel, and the third sub-pixel are respectively connected to the scan signal line, the data signal line, and the light-emitting signal line, and the pixel driving circuit is configured to receive a data voltage transmitted by the data signal line under a control of the scan signal line and the light-emitting signal line, and output a corresponding current to the light-emitting device. The light-emitting devices in the first sub-pixel, the second sub-pixel, and the third sub-pixel are respectively connected to the pixel driving circuits of the sub-pixels, and the light-emitting device is configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel.

In an exemplary implementation, the first sub-pixel may be a red sub-pixel (R) emitting red light, the second sub-pixel may be a blue sub-pixel (B) emitting blue light, and the third sub-pixel may be a green sub-pixel (G) emitting green light. In an exemplary implementation, a shape of the sub-pixel may be rectangular, rhombus, pentagonal, or hexagonal.

In an exemplary implementation, the pixel unit may include three sub-pixels, and the three sub-pixels may be arranged in a horizontal parallel, a vertical parallel or in a square manner, etc., which is not limited in the present disclosure.

In an exemplary implementation, the pixel unit may include four sub-pixels, and the four sub-pixels may be arranged in a horizontal parallel, a vertical parallel or a square manner, etc., which is not limited in the present disclosure.

On a plane perpendicular to the display substrate, the display substrate may include a driving structure layer arranged on a substrate, a light-emitting structure layer arranged on a side of the driving structure layer away from the substrate, and an encapsulation structure layer arranged on a side of the light-emitting structure layer away from the substrate. In some possible implementations, the display substrate may include other film layers, such as a touch structure layer, etc., which is not limited in the present disclosure.

In an exemplary implementation, the substrate may be a rigid substrate or a flexible substrate, the rigid substrate may be, but not limited to, one or more of glass and conductive foil; the flexible substrate may be, but not limited to, one or more of polyethylene terephthalate, ethylene glycol terephthalate, polyether ether ketone, polystyrene, polycarbonate, polyarylate, polyarylester, polyimide, polyvinyl chloride, polyethylene, and textile fiber.

In an exemplary implementation, the driving structure layer may include a plurality of transistors and storage capacitors constituting a pixel driving circuit, and the light-emitting structure layer may include an anode, a pixel definition layer, an organic light-emitting layer and a cathode, the anode is connected to a drain electrode of the transistor through a via hole, the organic light-emitting layer is connected to the anode, and the cathode is connected to the organic light-emitting layer, and the organic light-emitting layer emits light of corresponding colors driven by the anode and the cathode.

In an exemplary implementation, the encapsulation structure layer may include a first encapsulation layer, a second encapsulation layer and a third encapsulation layer stacked on each other, the first encapsulation layer and the third encapsulation layer may be made of inorganic materials, and the second encapsulation layer may be made of organic materials, and the second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer, so as to ensure that external water vapor cannot enter the light-emitting structure layer.

In an exemplary implementation, a touch structure layer may include a first touch insulating layer disposed on the encapsulation structure layer, a first touch metal layer disposed on the first touch insulating layer, a second touch insulating layer covering the first touch metal layer, a second touch metal layer disposed on the second touch insulating layer, and a touch protection layer covering the second touch metal layer, the first touch metal layer may include a plurality of bridging electrodes, the second touch metal layer may include a plurality of first touch electrodes and second touch electrodes, and the first touch electrode or the second touch electrode may be connected to the bridging electrode through a via hole.

The drawings of the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure, and for other structures, please refer to a general design.

To ensure clarity, in the accompanying drawings used to describe the embodiments of the present disclosure, thickness and dimensions of the layers or microstructures are exaggerated. It should be understood that when an element such as a layer, a film, a region or a substrate is referred to as being “on” or “under” another element, the element may be “directly” “on” or “under” another element, or there may be an intermediate element.

Proportions of the drawings in the present disclosure may be used as a reference for actual processes, but are not limited thereto. For example, a width-to-length ratio of the channel, a thickness and spacing of each film layer, a width and spacing of each signal line, may be adjusted according to actual needs. A quantity of pixels in the display substrate and a quantity of sub-pixels in each pixel are not limited to quantities shown in the drawings. The drawings described in the present disclosure are only structural schematic diagrams, and one method of the present disclosure is not limited to the shape or value shown in the drawings.

Ordinal numbers such as “first”, “second”, and “third” in this specification are set to avoid confusion among components and are not intended to limit quantities.

In this specification, for convenience, terms indicating the orientation or positional relationships such as “middle”, “upper”, “lower”, “front”, “back”, “vertical”, “horizontal”, “top”, “bottom”, “inner”, “outer” and the like are used to illustrate the positional relationships of the components with reference to the drawings. These terms are solely for purpose of describing the specification and simplifying the description, and do not imply or suggest that the indicated apparatus or component must have a specific orientation, or be constructed and operated in a specific orientation, so it cannot be understood as a limitation of this present disclosure. The positional relationships of components may change depending on the described orientation of each component. Thus, the terms used in the specification are not limitative and may be replaced or adjusted as appropriate according to specific circumstances.

In this specification, unless otherwise clearly specified and limited, terms “install”, “connect” and “link” should be understood in a broad sense. For example, it may be a fixed connection, or a detachable connection, or an integral connection; it may be a mechanical connection, or an electrical connection; it may be a direct connection, or an indirect connection through an intermediate, or a communicative connection between two elements. For a person of ordinary skill in the art, specific meanings of the above terms in this disclosure may be understood according to specific circumstances.

In this specification, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode and a source electrode. The transistor has a channel region between the drain electrode (a drain electrode terminal, a drain region or a drain electrode) and the source electrode (a source electrode terminal, a source region or a source electrode), and current can flow through the drain electrode, the channel region and the source electrode. Note that in this specification, the channel region refers to a region where the current mainly flows.

In this specification, “electrical connection” includes a case where components are connected together through an element having a certain electrical function. “Elements having a certain electrical function” are not particularly limited as long as they can transmit and receive electrical signals between the connected components. Examples of “elements having a certain electrical function” include not only electrodes and wirings, but also a switching element such as a transistor, a resistor, an inductor, a capacitor, and other elements having various functions.

In this specification, “arranged on a same layer” used refers to a structure formed by patterning two (or more) structures through a same patterning process, and these structures may be made of same or different materials. For example, materials of precursors used to form multiple structures arranged on the same layer may be the same, while final materials may either be same or different.

Although the implementations disclosed in the present disclosure are as described above, the contents described are only embodiments adopted to facilitate understanding of the present disclosure and are not intended to limit the present disclosure. Any modifications or variations in the form and details of implementation made by those skilled in the art, without departing from the spirit and scope of the disclosure, are considered to fall within the scope of the present disclosure, but the scope of patent protection of the present disclosure shall still be subject to the scope defined by the appended claims.

(1) The accompanying drawings of the embodiments of the present disclosure relate only to the structures involved with the embodiments of the present disclosure, and other structures can be referred to the usual design. (2) Features in the same embodiment and different embodiments of the present disclosure may be combined with each other without conflict. There are the following points to be clarified:

The foregoing is only an exemplary embodiment of the present disclosure and is not intended to limit the scope of protection of the present disclosure, which is determined by the appended rights.