Genetic Algorithm Accelerator and Control Method Thereof

This application claims the priority benefit of Korean Patent Application No. 10-2025-0037520 filed on Mar. 24, 2025 in the Korean Intellectual Property Office, the disclosures of which are incorporated herein by reference.

An embodiment relates to a memristive crossbar array-based genetic algorithm accelerator capable of accelerating operations for performing a genetic algorithm, and a control method thereof.

A genetic algorithm is a probabilistic optimization technique searching for an optimal solution based on biological evolutionary principles. The genetic algorithm may operate in a manner of generating a next-generation population through operations including selection, crossover, and mutation in an initial population, and evaluating a fitness of each individual. Due to these characteristics, the genetic algorithm may be effectively utilized for optimization of various problems.

During crossover and mutation processes being major operations of the genetic algorithm, many calculations are required, and in particular, as the size of a population increases, a computational burden increases. To solve this, various hardware-based acceleration techniques have been studied. For example, hardware implementation of a genetic algorithm using an FPGA (Field Programmable Gate Array) has been studied from an early stage, and dedicated processors based on an ASIC (Application Specific Integrated Circuit) have also been developed together.

However, existing FPGA and ASIC-based genetic algorithm accelerators may contribute to improving an operation speed, but there is still a limit in achieving high performance due to a bottleneck phenomenon between data movement and computation. Particularly, in the existing accelerator structure, due to the separation of a processor and a memory, since a process of reading, processing, and re-storing information of a population from the memory is repeated, there is a problem requiring many clock cycles.

In order to overcome such limitations, there is a need for a new approach minimizing movement between a memory and a processor by simultaneously performing data storage and computation, and solving problems of computation speed and energy efficiency of existing hardware-based accelerators.

This Summary is provided to introduce a selection of concepts in a simplified form that is further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.

In order to solve the above-described problems, an embodiment provides a genetic algorithm accelerator and a control method thereof capable of accelerating an operation of a genetic algorithm by utilizing a memristor-based crossbar array structure.

An example embodiment of the present invention may provide a genetic algorithm accelerator including a crossbar array block in which a plurality of memristor devices are connected in a crossbar array structure, wherein resistance states of the memristor devices are set based on a chromosome such that each row of the crossbar array structure simulates the chromosome.

According to an embodiment, the crossbar array block may include a first row simulating a first parent chromosome, a second row simulating a second parent chromosome, and remaining rows simulating a child chromosome in which a part of the first parent chromosome and a part of the second parent chromosome are mixed.

According to an embodiment, the child chromosome is generated by crossing over the part of the first parent chromosome and the part of the second parent chromosome based on a plurality of preset crossover points.

According to an embodiment, the child chromosome is generated by mapping the part of the first parent chromosome to the remaining rows based on the plurality of preset crossover points, and mapping the part of the second parent chromosome to a region to which the part of the first parent chromosome is not mapped.

According to an embodiment, the resistance states of some memristor devices in the crossbar array block are changed according to a preset algorithm.

According to an embodiment, the resistance states of some memristor devices in the crossbar array block are set to a relatively high resistance state through a reset operation, and thereafter the resistance states of some other memristor devices are set to a relatively low resistance state through a set operation.

According to an embodiment, the genetic algorithm accelerator further includes an evaluation circuit calculating fitness of the chromosome by performing a weighted sum operation based on preset weights corresponding to the respective memristor devices for each row comprised in the crossbar array block.

According to an embodiment, the evaluation circuit is based on a winner-take-all circuit.

According to an embodiment, the genetic algorithm accelerator further includes a readout circuit externally reading out a chromosome evaluated to have the highest fitness by the evaluation circuit.

According to an embodiment, each of the plurality of memristor devices comprises a selector transistor to prevent a sneak path current by allowing a current to flow when the corresponding memristor device is activated.

An example embodiment of the present invention may provide method for controlling a genetic algorithm accelerator including a crossbar array block in which a plurality of memristor devices are connected in a crossbar array structure, wherein resistance states of the memristor devices are set based on a chromosome such that each row of the crossbar array structure simulates the chromosome.

According to an embodiment, the crossbar array block includes a first row simulating a first parent chromosome, a second row simulating a second parent chromosome, and remaining rows simulating a child chromosome in which a part of the first parent chromosome and a part of the second parent chromosome are mixed.

According to an embodiment, the child chromosome is generated by crossing over the part of the first parent chromosome and the part of the second parent chromosome based on a plurality of preset crossover points.

According to an embodiment, the child chromosome is generated by mapping the part of the first parent chromosome to the remaining rows based on the plurality of preset crossover points, and mapping the part of the second parent chromosome to a region to which the part of the first parent chromosome is not mapped.

According to an embodiment, the resistance states of some memristor devices in the crossbar array block are changed according to a preset algorithm.

According to an embodiment, the resistance states of some memristor devices in the crossbar array block are set to a relatively high resistance state through a reset operation, and thereafter the resistance states of some other memristor devices are set to a relatively low resistance state through a set operation.

According to an embodiment, the genetic algorithm accelerator further comprises an evaluation circuit calculating fitness of the chromosome by performing a weighted sum operation based on preset weights corresponding to the respective memristor devices for each row comprised in the crossbar array block.

According to an embodiment, the evaluation circuit is based on a winner-take-all circuit.

According to an embodiment, the genetic algorithm accelerator further comprises a readout circuit externally reading out a chromosome evaluated to have the highest fitness by the evaluation circuit.

According to an embodiment, each of the plurality of memristor devices comprises a selector transistor to prevent a sneak path current by allowing a current to flow when the corresponding memristor device is activated.

According to a genetic algorithm accelerator and a control method thereof according to an embodiment, accelerating an operation of a genetic algorithm utilizing a memristor-based crossbar array structure resolves a data movement and computation bottleneck phenomenon, and remarkably improves computation efficiency by maximizing parallel computation.

Throughout the drawings and the detailed description, the same reference numerals may refer to the same, or like, elements. The drawings may not be to scale, and the relative size, proportions, and depiction of elements in the drawings may be exaggerated for clarity, illustration, and convenience.

The advantages and features of the present invention, and methods for achieving the same, will become apparent with reference to the embodiments described below in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed herein and may be implemented in various different forms. These embodiments are provided merely to make the disclosure of the present invention complete and to fully convey the scope of the invention to those skilled in the art to which the present invention pertains, and the present invention is defined only by the scope of the appended claims.

The terms used in the present specification will be briefly described, and the present invention will then be described in detail.

The terms used in the present invention have been selected from generally used terms that are widely employed at present while taking into consideration the functions in the present invention. However, these terms may vary depending on the intention of those skilled in the art, precedents, the emergence of new technologies, or the like. In certain cases, terms arbitrarily selected by the applicant may also be used, and in such cases, the meanings of the terms will be described in detail in the corresponding portions of the description of the invention. Accordingly, the terms used in the present invention should be construed based not merely on the names of the terms but on the meanings of the terms and the overall contents of the present invention.

Throughout the present specification, when a portion is described as including a certain component, this means that the portion may further include other components rather than excluding other components, unless otherwise specifically stated. In addition, the terms such as “part,” “module,” and “unit” used in the present specification may refer to a unit that processes at least one function or operation.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art to which the present invention pertains can readily practice the invention. In the drawings, portions not related to the description are omitted in order to clearly explain the present invention.

Terms including ordinal numbers such as “first” and “second” may be used to describe various components, but the components are not limited by these terms. These terms are used only for the purpose of distinguishing one component from another. For example, a first component may be referred to as a second component without departing from the scope of the present invention, and similarly, a second component may also be referred to as a first component. The term “and/or” includes any one of a plurality of associated items or a combination of a plurality of associated items.

1 Hereinafter, the genetic algorithm acceleratorand the control method thereof of an embodiment will be described.

1 The genetic algorithm acceleratorand the control method thereof of an embodiment are technologies for accelerating a genetic algorithm. The genetic algorithm is a probabilistic optimization technique searching for an optimal solution by imitating a natural evolutionary process, and may search for the optimal solution by repeating a process of generating a new population by performing operations including crossover and mutation in an initial population, and selecting superior chromosome by evaluating a fitness in each population.

1 FIG. is a flowchart of a genetic algorithm according to an embodiment.

1 FIG. Referring to, the genetic algorithm may include a process of calculating a fitness of each chromosome in an initial population, evaluating the fitness according to a criterion, and then selecting a most superior chromosome as a parent chromosome. Furthermore, the genetic algorithm may include a process of generating a child chromosome through crossover and mutation processes from the parent chromosome in order to generate a new population. Accordingly, the genetic algorithm may quickly converge to an optimal solution, and may exhibit high performance in various optimization problems.

1 The genetic algorithm acceleratorand the control method thereof of an embodiment are based on in-memory processing, thereby being capable of performing data storage and computation simultaneously.

1 2 FIG. Specifically, the genetic algorithm acceleratorand the control method thereof of an embodiment may perform data storage and computation simultaneously utilizing a memristor.is a schematic diagram illustrating a memristor and an operating principle thereof according to an embodiment. The memristor has a characteristic of changing a resistance value according to a previous voltage or current state by remembering a current flow path. If a voltage is applied in a specific direction, then the memristor may change to a low resistance state (ON) decreasing resistance, and if a voltage in an opposite direction is applied, then the memristor may transition to a high resistance state (OFF) increasing resistance. Since this resistance value is maintained even if power is turned off, the memristor may be used as a non-volatile memory.

The memristor-based crossbar array structure means that memristors having resistance values varying according to a history of a flowed current are arranged in an array structure having rows and columns. Accordingly, the memristor-based crossbar array structure may combine a memory function of the memristor and a parallel processing function of the array.

1 The genetic algorithm acceleratorand the control method thereof of an embodiment may accelerate a genetic algorithm utilizing the memristor-based crossbar array structure. Accordingly, an embodiment may remarkably improve the operation speed of the genetic algorithm, minimize a bottleneck phenomenon according to data movement, and maximize energy efficiency. Furthermore, an embodiment may overcome limitations of an existing hardware-based genetic algorithm accelerator, and effectively perform a large-scale parallel operation, improving optimal solution search performance.

1 Hereinafter, the genetic algorithm acceleratorof an embodiment will be described.

1 210 The genetic algorithm acceleratorof an embodiment may simulate a plurality of chromosomes utilizing memristor devicesarranged in a crossbar array structure, and may perform a genetic algorithm operation through a process of evaluating a fitness of each chromosome and selecting and reading out a chromosome having the highest fitness.

3 FIG. Here, a chromosome may mean a data structure expressing an individual solution in the genetic algorithm.is a schematic diagram illustrating a chromosome according to an embodiment. In general, the chromosome includes genetic information, and may include a bit string of a specific length to express the genetic information digitally.

3 FIG. The chromosome may include a parent chromosome and a child chromosome. Referring to, parent chromosomes Pr1 and Pr2 may mean original chromosomes serving as a reference for performing a crossover operation, and child chromosomes Ch1 to Ch6 may mean new chromosomes generated by combining some gene data of the parent chromosomes. A specific portion of the child chromosome is selected from a first parent chromosome, and a remaining portion is selected from a second parent chromosome, being generated by performing a crossover operation.

4 FIG. 5 FIG. 1 1 is a schematic diagram of the genetic algorithm acceleratorof an embodiment, andis a block diagram of the genetic algorithm acceleratorof an embodiment.

4 5 FIGS.and 1 20 13 11 30 40 1 Referring to, the genetic algorithm acceleratorof an embodiment may include a crossbar array block, a row voltage driver, a column voltage driver, an evaluation circuit, and a readout circuit. The genetic algorithm acceleratorof an embodiment may further include a processor providing signals, a memory storing data, a DFF (D Flip-Flop), and the like, in addition to the configuration described above.

13 11 20 13 11 20 The row voltage driverand the column voltage driverare driving circuits applying a voltage required to perform a genetic algorithm operation in the crossbar array block. The row voltage driverand the column voltage drivermay individually select each row and column of the crossbar array blockto supply a specific voltage, allowing a selected row to simulate a chromosome.

13 11 20 30 13 11 210 13 11 210 11 13 30 The row voltage driverand the column voltage drivermay allow other components including the crossbar array blockand the evaluation circuitto store and update respective chromosome data during a genetic algorithm operation process including crossover, mutation, and fitness evaluation to be described later. In one embodiment, during a crossover operation, the row voltage drivermay select a row storing a parent chromosome, and the column voltage drivermay determine a column generating a child chromosome, applying a voltage based thereon. Furthermore, during a mutation operation, in order to change resistance states of some memristor devicesin a row simulating a specific chromosome, the row voltage drivermay select a row of a corresponding chromosome, and the column voltage drivermay supply a voltage to change the resistance state of a selected memristor device. In addition, during a fitness evaluation process, the column voltage drivermay apply a voltage reflecting a preset weight value to each column, and the row voltage drivermay transfer data to the evaluation circuitbased on this, allowing an operation of all chromosomes to be performed.

13 11 That is, it may be understood that the following genetic algorithm operation process is achieved by the row voltage driverand the column voltage driveroperating by a user manipulation or a preset algorithm to provide a voltage to respective components.

20 210 210 210 210 210 1 0 The crossbar array blockmay include a plurality of memristor devicesconnected in a crossbar array structure. The crossbar array structure is formed in a form where a plurality of rows and columns cross, and each of the plurality of memristor devicesmay be disposed at an intersection where a row and a column cross. The memristor deviceshave a characteristic changing their resistance states if a specific voltage is applied, utilizing this to store data or perform calculations. That is, each memristor devicemay have a specific resistance state, utilizing this to represent information. For example, the memristor devicesmay store information on digital data by setting bitto a low resistance state (ON) andto a high resistance state (OFF).

210 210 210 210 210 According to an embodiment, the memristor devicesmay further include a selector transistor. During a genetic algorithm operation process, a sneak path current may flow to an unintended memristor devicein addition to a memristor deviceintended for a resistance change. Due to this, a sneak path current problem may occur during crossover and mutation operation processes described later, but if the memristor devicesfurther include a selector transistor, then a current may be allowed to flow when the memristor devicesare activated, preventing such a sneak path current from occurring, preventing power overhead.

20 13 11 210 210 20 210 210 Each row and column of the crossbar array blockmay be connected to the row voltage driverand the column voltage driver, applying a voltage to a specific row or column thereby to set or read a state of the memristor devices. The resistance states of the memristor devicesmay be adjusted according to whether a voltage is applied and a magnitude thereof, performing an operation within the crossbar array thereby. Due to the crossbar array structure of the crossbar array block, the resistance states of the memristor devicesmay be individually changed, and resistance states of a plurality of memristor devicesmay be simultaneously changed.

20 210 210 13 11 210 The crossbar array blockmay have the resistance states of the memristor devicesset based on a chromosome, allowing each row included therein to simulate the chromosome. In the crossbar array, each row may be allocated as a data region storing one chromosome, and each column may correspond to an individual gene bit constituting the chromosome. Data constituting the chromosome may be written to the memristor devicesthrough the row voltage driverand the column voltage driver, and a resistance state of a specific memristor devicemay be changed according to a given voltage condition.

6 7 FIGS.and 20 are schematic diagrams of a chromosome simulation process of the crossbar array blockaccording to an embodiment.

6 7 FIGS.and 6 FIG. 210 20 11 13 210 Referring to, the memristor devicesof the crossbar array blockmay have resistance states changed to simulate a specific chromosome according to voltages provided from the column voltage driverand the row voltage driver. According to the embodiment of, if the parent chromosome is 010011, then the memristor devicesin a row simulating this may be sequentially set to a high resistance state, a low resistance state, a high resistance state, a high resistance state, a low resistance state, and a low resistance state.

210 20 210 20 210 6 7 FIGS.and IM W IM The memristor devicesof the crossbar array blockmay simulate a chromosome by voltages according to a plurality of clock cycles. A clock cycle may mean a time unit required for one operation to be completed within a circuit. In one clock cycle, a change in resistance may be induced by providing a voltage to the memristor devicesof the crossbar array blockthrough a control circuit including a DFF and a multiplexer according to a clock signal, allowing data to be inputted or read out thereby. Referring to the embodiments of, the memristor devicesmay change or maintain resistance depending on whether a row voltage is Vor GND and whether a column voltage is Vor V, simulating a chromosome according to this.

1 In the genetic algorithm acceleratorof an embodiment, the clock cycle may determine a timing performing crossover and mutation operations. In one embodiment, a part of a parent chromosome is selected in a specific clock cycle, changing data for a specific column based on this, generating a child chromosome thereby. A process of simulating a chromosome according to a clock cycle and generating a child chromosome will be described later.

20 20 210 The crossbar array blockmay include a first row simulating a first parent chromosome, a second row simulating a second parent chromosome, and remaining rows simulating a child chromosome mixing a part of the first parent chromosome and a part of the second parent chromosome. In the crossbar array of the crossbar array block, the first row and the second row may be allocated to store the first parent chromosome and the second parent chromosome respectively, and the memristor devicesof each row may be set to resistance states reflecting genetic data of the corresponding parent chromosome.

20 20 20 210 210 210 13 11 7 FIG. Remaining rows excluding the first row and the second row in the crossbar array of the crossbar array blockmay store the child chromosome. The crossbar array blockmay store the child chromosome generated from the parent chromosome through a crossover operation. Referring to, in one row of the crossbar array block, the memristor devicesin a specific region or column are set to data of the first parent chromosome, and the memristor devicesin another region or column are set to data of the second parent chromosome, being stored. In the process of performing such a crossover operation, a gene value of a selected parent chromosome may be copied to a resistance state of a corresponding memristor device, and such data transmission may be controlled through the row voltage driverand the column voltage driver.

The child chromosome may be generated by crossing over parts of the first parent chromosome and the second parent chromosome based on a plurality of preset crossover points. As described above, the child chromosome may be generated by crossing over parts of the first parent chromosome and the second parent chromosome. In the crossbar array, each row is allocated to store one chromosome, and rows storing the child chromosome may be configured by selectively combining some data of the parent chromosome through a crossover operation. A crossover point may be set to a predefined specific column position, and a crossover operation may be performed by copying genes of different parent chromosomes based on the corresponding crossover point. Furthermore, if a plurality of crossover points exist, then a child chromosome may be generated in a manner combining data of different parent chromosomes respectively in multiple divided regions, allowing the child chromosome to form a new combination while maintaining some characteristics of the parent chromosome thereby.

According to an embodiment, the number of crossover points may be set to a number satisfying Equation 1 below.

CP CK Here, Nmay mean the number of crossover points, P may mean the number of chromosomes in a population, and Nmay mean the number of clock cycles required to complete all crossover operations during one generation.

20 13 11 210 The child chromosome may be generated by mapping a part of the first parent chromosome to rows of the crossbar array blockbased on the plurality of crossover points, and mapping a part of the second parent chromosome to an unassigned region. Rows storing the child chromosome within the crossbar array may be allocated as a data region performing a crossover operation, and a part of the parent chromosome may be mapped to a specific column position of each row according to a preset crossover point. The crossover point becomes a reference for exchanging data between parent chromosomes within the child chromosome, and genetic data before the corresponding crossover point is copied from the first parent chromosome, and an unspecified region thereafter may be set to reflect data of the second parent chromosome. Such a mapping process may be performed in a manner applying a voltage utilizing the row voltage driverand the column voltage driver, determining a gene value of the child chromosome by adjusting a resistance state of a selected memristor device. Furthermore, if a plurality of crossover points exist, then data of the parent chromosome may be mapped by being divided into a plurality of sections according to positions of the crossover points, being arranged to generate child chromosomes of various combinations thereby.

6 7 FIGS.and 6 FIG. 6 FIG. 7 FIG. 1 2 1 2 Referring to,illustrates a process performing an initial crossover. DFFand DFFstore data of a first parent chromosome and a second parent chromosome respectively, having a structure selectively applying this data to specific rows and columns of a crossbar array through multiplexers MXand MX. In the initial crossover process, as shown in, some regions may be updated based on the first parent chromosome data based on a preset crossover point.illustrates a process performing a subsequent crossover. In the subsequent crossover process, by updating a remaining region not updated with the first parent chromosome in a previous operation utilizing second parent chromosome data, a child chromosome subjected to a crossover operation based on a crossover point is generated, being stored in each row.

6 7 FIGS.and 210 20 Referring to the embodiments of, the memristor devicesof the crossbar array blockmay simulate a chromosome as a total of six clock cycles Cycle #1 to #6 proceed from a first clock cycle to a sixth clock cycle.

6 FIG. 20 Referring to the embodiment of, the crossbar array blockmay simulate a first parent chromosome and a part thereof during an initial crossover operation process.

1 3 4 20 1 2 1 3 4 W In a first clock cycle Cycle #1, a part of the first parent chromosome may be copied to the left region of a first row H, a third row H, and a fourth row Hof the crossbar array block. To this end, in the first clock cycle Cycle #1, voltages of a first left line Vand a second line Vare set to Vin a vertical line, and voltages of a first row H, a third row H, and a fourth row Hmay be set to GND in a horizontal line.

1 3 6 20 3 4 1 3 6 W Next, in a second clock cycle Cycle #2, a part of the first parent chromosome may be copied to a middle region of the first row H, the third row H, and a sixth row Hof the crossbar array block. To this end, in the second clock cycle Cycle #2, voltages of a third line Vand a fourth line Vare set to Vin the vertical line, and voltages of the first row H, the third row H, and the sixth row Hmay be set to GND in the horizontal line.

1 5 6 20 5 6 1 5 6 W Next, in a third clock cycle Cycle #3, a part of the first parent chromosome may be copied to a right region of the first row H, a fifth row H, and the sixth row Hof the crossbar array block. To this end, in the third clock cycle Cycle #3, voltages of a fifth line Vand a sixth line Vare set to Vin the vertical line, and voltages of the first row H, the fifth row H, and the sixth row Hmay be set to GND in the horizontal line.

7 FIG. 20 Referring to the embodiment of, the crossbar array blockmay simulate a second parent chromosome and a part thereof in a region not simulated during the initial crossover operation process during a subsequent crossover operation process.

2 5 6 20 1 2 2 5 6 W In a fourth clock cycle Cycle #4, a part of the second parent chromosome may be copied to a left region of the second row H, the fifth row H, and the sixth row Hof the crossbar array block. To this end, in the fourth clock cycle Cycle #4, voltages of the first left line Vand the second line Vare set to Vin the vertical line, and voltages of the second row H, the fifth row H, and the sixth row Hmay be set to GND in the horizontal line.

2 4 5 20 3 4 2 4 5 W Next, in a fifth clock cycle Cycle #5, a part of the second parent chromosome may be copied to a middle region of the second row H, the fourth row H, and the fifth row Hof the crossbar array block. To this end, in the fifth clock cycle Cycle #5, voltages of the third line Vand the fourth line Vare set to Vin the vertical line, and voltages of the second row H, the fourth row H, and the fifth row Hmay be set to GND in the horizontal line.

2 3 4 20 5 6 2 3 4 W Next, in a sixth clock cycle Cycle #6, a part of the second parent chromosome may be copied to the right region of the second row H, the third row H, and the fourth row Hof the crossbar array block. To this end, in the sixth clock cycle Cycle #6, voltages of the fifth line Vand the sixth line Vare set to Vin the vertical line, and voltages of the second row H, the third row H, and the fourth row Hmay be set to GND in the horizontal line.

20 210 210 210 13 11 210 210 210 210 210 210 8 8 FIGS.A andB The crossbar array blockmay simulate a mutation by changing resistance states of some memristor devices.are schematic diagrams of a mutation operation process according to an embodiment. A mutation operation may be performed by changing a resistance state of a memristor deviceselected within the crossbar array, and for this purpose, a voltage may be applied to a memristor deviceat a specific position utilizing the row voltage driverand the column voltage driver. The memristor devicebeing a mutation target may be selected according to a preset probability or rule, and the selected memristor devicemay be transitioned from an existing resistance state to an opposite state. For example, a memristor deviceoriginally in a low resistance state (ON) may transition to a high resistance state (OFF), and conversely, a memristor devicein a high resistance state (OFF) may be changed to a low resistance state (ON). Such a mutation operation may be performed within a specific clock cycle, and after the mutation is applied, voltage application may be adjusted to maintain the changed state of the memristor device. Furthermore, the mutation operation may be performed in parallel within the crossbar array to simultaneously mutate selected memristor devicesthereby.

20 210 210 210 210 210 20 13 11 The crossbar array blockmay have resistance states of some memristor devicesset to a relatively high resistance state through a reset operation, and thereafter resistance states of some other memristor devicesmay be set to a relatively low resistance state through a set operation. The reset operation may be performed in a manner applying a specific voltage to a selected memristor deviceto increase resistance state, setting the corresponding memristor deviceto a high resistance state (OFF) thereby. The set operation is performed in an opposite manner to the reset operation, and applies a different voltage condition to a selected memristor deviceto decrease resistance state, being set to a low resistance state (ON) thereby. Such reset and set operations may be sequentially performed by selecting a specific row and column within the crossbar array block, being performed by controlling an applied voltage utilizing the row voltage driverand the column voltage driver.

30 20 30 The evaluation circuitmay evaluate the fitness of a chromosome simulated by each row of the crossbar array block. The evaluation circuitmay be arranged in a structure receiving chromosome data stored in each row of the crossbar array as an input, calculating fitness according to predefined criteria.

9 FIG. 30 is a schematic diagram illustrating the evaluation circuitand a fitness evaluation process thereof according to an embodiment.

210 30 210 30 210 30 The memristor devicesof each row indicate a gene value of a corresponding chromosome, and the evaluation circuitmay calculate fitness based on the state of each memristor device. To this end, the evaluation circuitmay be arranged to apply an input voltage in units of columns of the crossbar array, and allow a corresponding voltage to be converted into a current according to resistance states of the memristor devices. A converted current value is summed through an operation circuit, and the fitness of a chromosome simulated by a corresponding row may be determined utilizing this value. A fitness operation method may be performed by a weighted sum operation or a method calculating the number satisfying a specific condition, and to this end, the evaluation circuitmay include a function outputting an operation result. Furthermore, the evaluated fitness value may be compared with other chromosomes through a comparison circuit operable to select a chromosome having a high fitness or perform an additional genetic operation thereby.

30 210 20 20 210 30 210 210 The evaluation circuitmay calculate the fitness of a chromosome by performing a weighted sum operation based on preset weights corresponding to respective memristor devicesfor each row included in the crossbar array block. In the crossbar array block, each row stores one chromosome, and each memristor devicemay represent an individual gene value of a corresponding chromosome. The evaluation circuitmay apply a voltage to which a weight is applied based on a state of a memristor devicecorresponding to each column in order to calculate a fitness of a chromosome, and a corresponding voltage may be converted into a current according to resistance states of the memristor devices. A converted current is summed through an operation circuit, being output as a final fitness value. A weight may be set according to predefined criteria, performing a role adjusting a contribution of each gene value according to characteristics of an optimization problem a chromosome intends to solve. Furthermore, a weighted sum operation result may be transferred to a fitness comparison circuit operable to perform a comparison with other chromosomes or an additional genetic operation thereby.

30 30 The evaluation circuitmay be based on a winner-take-all circuit. The winner-take-all circuit is a circuit selecting and outputting an input having the highest value among a plurality of input values, identifying a chromosome having the highest fitness by comparing fitness of a chromosome stored by each row within the crossbar array. The evaluation circuitcalculates fitness of each chromosome, and then performs a comparison operation through the winner-take-all circuit, selecting a chromosome having the highest fitness according to a comparison result. To this end, the winner-take-all circuit may operate in a manner receiving each fitness value as an input, and activating an input having a maximum value satisfying a specific criterion. A selected chromosome may be transmitted to a separate circuit to be utilized as a parent chromosome for a subsequent genetic operation, and an additional comparison operation may be performed as needed. According to an embodiment, the winner-take-all circuit may be implemented as a multi-stage comparison structure, being operable to select a plurality of chromosomes having high fitness thereby.

40 30 40 40 210 40 210 40 10 FIG. The readout circuitmay read out a chromosome evaluated to have the highest fitness by the evaluation circuitto the outside.is a schematic diagram illustrating a process reading out a chromosome from the readout circuitaccording to an embodiment. The readout circuitmay operate in a manner activating a row storing a selected chromosome within the crossbar array, and outputting data by sensing a resistance state of a memristor deviceof a corresponding row. To this end, the readout circuitreceives a row selection signal, applying a read voltage to a memristor devicecorresponding to a specific row, obtaining chromosome data by sensing a generated current according to this. A sensed current may be converted into a digital signal through an operation circuit, and a converted signal may be transmitted to an external storage device or a subsequent operation circuit. Furthermore, the readout circuitmay include a differential amplifier or a sense amplifier to minimize signal interference and guarantee accurate data output, being operable to perform a function sequentially reading out multiple chromosomes as needed.

1 Hereinafter, a method for controlling the genetic algorithm accelerator () according to the present invention will be described.

An example embodiment of the present invention may provide method for controlling a genetic algorithm accelerator including a crossbar array block in which a plurality of memristor devices are connected in a crossbar array structure, wherein resistance states of the memristor devices are set based on a chromosome such that each row of the crossbar array structure simulates the chromosome.

According to an embodiment, the crossbar array block includes a first row simulating a first parent chromosome, a second row simulating a second parent chromosome, and remaining rows simulating a child chromosome in which a part of the first parent chromosome and a part of the second parent chromosome are mixed.

According to an embodiment, the child chromosome is generated by crossing over the part of the first parent chromosome and the part of the second parent chromosome based on a plurality of preset crossover points.

According to an embodiment, the child chromosome is generated by mapping the part of the first parent chromosome to the remaining rows based on the plurality of preset crossover points, and mapping the part of the second parent chromosome to a region to which the part of the first parent chromosome is not mapped.

According to an embodiment, the resistance states of some memristor devices in the crossbar array block are changed according to a preset algorithm.

According to an embodiment, the resistance states of some memristor devices in the crossbar array block are set to a relatively high resistance state through a reset operation, and thereafter the resistance states of some other memristor devices are set to a relatively low resistance state through a set operation.

According to an embodiment, the genetic algorithm accelerator further comprises an evaluation circuit calculating fitness of the chromosome by performing a weighted sum operation based on preset weights corresponding to the respective memristor devices for each row comprised in the crossbar array block.

According to an embodiment, the evaluation circuit is based on a winner-take-all circuit.

According to an embodiment, the genetic algorithm accelerator further comprises a readout circuit externally reading out a chromosome evaluated to have the highest fitness by the evaluation circuit.

According to an embodiment, each of the plurality of memristor devices comprises a selector transistor to prevent a sneak path current by allowing a current to flow when the corresponding memristor device is activated.

Those skilled in the art related to the embodiments of the present invention will understand that the invention may be implemented in modified forms without departing from the essential characteristics described above. Accordingly, the disclosed embodiments should be considered in an illustrative rather than a limiting sense. The scope of the present invention is defined by the appended claims rather than by the detailed description, and all differences within the equivalent scope thereof should be construed as being included in the scope of the present invention.