Shift Register and Display Panel

This application claims priority to Chinese Patent Application No. 202510873629.5, filed on Jun. 26, 2025, entitled “Shift register and display panel,” which is incorporated herein by reference in its entirety.

Embodiments of the present disclosure relate to the field of display technology, and in particular, it relates to a shift register and a display panel.

With the development of display technology, users have increasingly higher requirements for the display effect of display panels.

A display panel typically includes shift registers that provide gate driving signals for pixel circuits at various stages. Existing shift registers are relatively complex, which is not conducive to achieving a narrow bezel.

Embodiments of the present disclosure provide a shift register and a display panel to reduce the bezel of the display panel.

According to an aspect of the present disclosure, a shift register is provided, including: a first signal output module and a second signal output module. A control terminal of the first signal output module and a first control terminal of the second signal output module are connected at a first node. The first node is configured to receive a start signal. A second control terminal of the second signal output module and an output terminal of the first signal output module are connected at a second node. The first signal output module is configured to output a first gate driving signal to the second node based on a voltage of the first node. The second signal output module is configured to output a second gate driving signal based on the voltage of the first node and the voltage of the second node; and a short pulse width level of the first gate driving signal is opposite to a short pulse width level of the second gate driving signal.

According to another aspect of the present disclosure, a shift register is provided, including a second signal output module and a first potential control module; a first control terminal of the second signal output module and an output terminal of the first potential control module are connected at a first node. The first node is used for receiving a start signal. A second control terminal of the second signal output module and a first control terminal of the first potential control module are connected at a second node. The first potential control module is used for controlling a voltage of the first node based on a voltage of the second node. The second signal output module is used for outputting a second gate drive signal based on the voltage of the first node and the voltage of the second node. According to another aspect of the present disclosure, a display panel is provided, the display panel including a gate drive circuit. The gate drive circuit includes a plurality of shift registers according to any embodiment of the present disclosure. The plurality of shift registers are connected in cascade; in the plurality of cascaded shift registers, the start signal received by a next-stage shift register is provided by an output terminal of the second signal output module of a current-stage shift register. The start signal of a first-stage shift register is provided by a trigger signal line. In one embodiment provided by the embodiments of the present disclosure, by controlling the voltage of the first node, the first signal output module outputs a first gate drive signal to the second node based on the voltage of the first node, and the second signal output module outputs a second gate drive signal based on the voltage of the first node and the voltage of the second node. The first node is used for receiving a start signal, the second node is used for outputting the first gate drive signal, and a short pulse width level of the first gate drive signal is opposite to a short pulse width level of the second gate drive signal. Compared with solutions in the related art, the embodiments provided by this embodiment, through mutual borrowing and coordinated cooperation between the first signal output module and the second signal output module, can output two different types of gate drive signals, and has a simple circuit structure, which is beneficial for compressing the bezel of the display panel and achieving a narrow bezel design. The content described in this section is not intended to identify key or important features of the embodiments of the present disclosure, nor is it intended to limit the scope of the present disclosure. Other features of the present disclosure will become readily apparent from the following description.

1 FIG. is a schematic structural diagram of a shift register according to an embodiment of the present disclosure.

1 FIG. 110 120 110 120 1 1 120 110 2 110 1 2 1 120 2 1 2 Referring to, the shift register provided in this embodiment includes: a first signal output moduleand a second signal output module, and a control terminal of the first signal output moduleand a first control terminal of the second signal output moduleare connected at a first node N, the first node Nis configured to receive a start signal SIN, a second control terminal of the second signal output moduleand an output terminal of the first signal output moduleare connected at a second node N, the first signal output moduleis configured to output a first gate drive signal SCANto the second node Nbased on a voltage at the first node N, and the second signal output moduleis configured to output a second gate drive signal SCANbased on the voltage at the first node Nand a voltage at the second node N.

1 2 1 1 1 1 2 2 2 A short pulse width level of the first gate drive signal SCANis opposite to a short pulse width level of the second gate drive signal SCAN. Here, the short pulse width level refers to an effective level of the gate drive signal capable of turning on a corresponding transistor. For example, if the first gate drive signal SCANis used to drive an N-type transistor, then the short pulse width level of the first gate drive signal SCANis a high level, and the long pulse width level of the first gate drive signal SCANis a low level, i.e., an on-time of the transistor connected to the first gate drive signal SCANis shorter than an off-time. For another example, if the second gate drive signal SCANis used to drive a P-type transistor, then the short pulse width level of the second gate drive signal SCANis a low level, and the long pulse width level of the second gate drive signal SCANis a high level.

1 110 1 1 120 1 2 2 In one embodiment, when the start signal SIN is a first level pulse (e.g., a low level pulse), the voltage at the first node Nis the voltage of the first level pulse of the start signal SIN, the first signal output moduleresponds to the voltage at the first node Nto output the short pulse width level of the first gate drive signal SCAN, while the second signal output moduleresponds to the voltage at the first node Nand the voltage at the second node Nto output the long pulse width level of the second gate drive signal SCAN.

1 1 2 1 Subsequently, for a period of time, the start signal SIN no longer controls the voltage at the first node N. The first node Ncontinuously maintains the voltage of the first level pulse, and the voltage at the second node Nis maintained at the short pulse width level of the first gate drive signal SCAN.

120 1 2 2 Then, under the action of a corresponding clock signal (not shown in the figure), the second signal output moduleresponds to the voltage at the first node Nand the voltage at the second node Nto output the short pulse width level of the second gate drive signal SCAN.

1 1 110 1 1 120 1 2 2 1 2 When the start signal SIN again controls the potential at the first node N, the start signal SIN has transitioned from the first level pulse to a second level pulse (e.g., a high level pulse), the voltage at the first node Nis the voltage of the second level pulse of the start signal SIN, the first signal output moduleresponds to the voltage at the first node Nto output the long pulse width level of the first gate drive signal SCAN, while the second signal output moduleresponds to the voltage at the first node Nand the voltage at the second node Nto output the long pulse width level of the second gate drive signal SCAN, thereby forming the first gate drive signal SCANand the second gate drive signal SCAN, respectively.

1 110 1 2 1 120 2 1 2 1 2 1 1 2 110 120 The embodiments provided by the embodiment of the present disclosure, by controlling the voltage at the first node N, enables the first signal output moduleto output the first gate drive signal SCANto the second node Nbased on the voltage at the first node N, and controls the second signal output moduleto output the second gate drive signal SCANbased on the voltage at the first node Nand the voltage at the second node N, and the first node Nis configured to receive the start signal, and the second node Nis configured to output the first gate drive signal SCAN, and the short pulse width level of the first gate drive signal SCANis opposite to the short pulse width level of the second gate drive signal SCAN. Compared with solutions in the related art, the embodiments provided in this embodiment, through mutual borrowing and coordinated cooperation between the first signal output moduleand the second signal output module, can output two different types of gate drive signals, and has a simple circuit structure, which is beneficial for compressing the bezel of a display panel and achieving a narrow bezel design.

2 FIG. 3 FIG. 2 FIG. 3 FIG. 1 1 2 2 110 110 110 1 2 1 is a schematic structural diagram of another shift register provided by an embodiment of the present disclosure, andis a schematic waveform diagram of a gate drive signal provided by an embodiment of the present disclosure. Referring toand, based on the above embodiment, the short pulse width level Sof the first gate drive signal SCANcovers the short pulse width level Sof the second gate drive signal SCAN. In one embodiment, a first input terminal of the first signal output modulereceives a first voltage signal VGH, a second input terminal of the first signal output modulereceives a second voltage signal VGL, and the first signal output moduleis configured to respond to the voltage at the first node Nto output the first voltage signal VGH or the second voltage signal VGL to the second node N, while outputting the first gate drive signal SCAN.

110 1 2 1 2 1 1 1 2 2 2 1 2 1 1 1 1 2 1 1 1 2 In this embodiment, the first signal output moduleincludes a first transistor Qand a second transistor Q. The control electrode of the first transistor Qand the control electrode of the second transistor Qare both connected to the first node N. The first electrode of the first transistor Qreceives a first voltage signal VGH, and the second electrode of the first transistor Qand the second electrode of the second transistor Qare both connected to the second node N. The first electrode of the second transistor Qreceives a second voltage signal VGL. The channel type of the first transistor Qis different from the channel type of the second transistor Q. When a first level pulse of a start signal SIN is transmitted to the first node N, the first transistor Qis turned on in response to the voltage at the first node N, and the first transistor Qtransmits the first voltage signal VGH to the second node N. When the start signal SIN does not control the voltage at the first node N, the first node Nmaintains the first level pulse, the first transistor Qremains turned on, and the second node Nmaintains the first voltage signal VGH.

120 2 1 2 1 1 2 2 1 1 1 2 2 During this process, the second signal output moduleoutputs a short pulse width level of a second gate driving signal SCANin response to the voltage at the first node Nand the voltage at the second node N, thereby achieving that a short pulse width level Sof a first gate driving signal SCANcovers a short pulse width level Sof the second gate driving signal SCAN. Since the short pulse width of the first gate driving signal SCANis a high level, setting the short pulse width level Sof the first gate driving signal SCANto cover the short pulse width level Sof the second gate driving signal SCANis beneficial for improving the switching speed of an N-type transistor, and the on-resistance of the N-type transistor is relatively small, thereby reducing the power consumption of the N-type transistor within one cycle, and further reducing the overall power consumption of the display panel.

1 2 1 2 2 1 When a second level pulse of the start signal SIN is transmitted to the first node N, the second transistor Qis turned on in response to the voltage at the first node N, and the second transistor Qtransmits the second voltage signal VGL to the second node N, outputting a long pulse width level of the first gate driving signal SCAN.

1 2 In one embodiment, the first transistor Qis a P-type transistor, and the second transistor Qis an N-type transistor.

1 1 1 In one embodiment, the level of the first voltage signal VGH is greater than the level of the second voltage signal VGL, the level of the first voltage signal VGH is the short pulse width level Sof the first gate driving signal SCAN, and the second voltage signal VGL is the long pulse width level of the first gate driving signal SCAN.

4 FIG. 4 FIG. 120 120 1 120 1 1 2 2 is a schematic structural diagram of another shift register provided in an embodiment of the present disclosure. Referring to, based on the above embodiments, a first input terminal of the second signal output modulereceives the first voltage signal VGH, a second input terminal of the second signal output modulereceives a first clock signal SCK, and the second signal output moduleis configured to output the first voltage signal VGH or the first clock signal SCKin response to the voltage at the first node Nand the voltage at the second node N, to output the second gate driving signal SCAN.

120 1201 1202 1201 3 1202 4 3 2 3 3 4 3 3 120 4 1 In one embodiment, the second signal output moduleincludes a first output unitand a second output unit. The first output unitincludes a third transistor Q, and the second output unitincludes a fourth transistor Q. The control electrode of the third transistor Qis connected to the second node N, the first electrode of the third transistor Qreceives the first voltage signal VGH, the second electrode of the third transistor Qand the second electrode of the fourth transistor Qare connected to a third node N, the third node Nis connected to the output terminal of the second signal output module, and the first electrode of the fourth transistor Qreceives the first clock signal SCK.

1 4 1 1 3 3 2 1 4 1 3 2 3 When the first level pulse of the start signal SIN is transmitted to the first node N, the fourth transistor Qis turned on in response to the voltage at the first node N, outputting the first clock signal SCKto the third node N, and the third transistor Qis turned off in response to the voltage at the second node N. When the second level pulse of the start signal SIN is transmitted to the first node N, the fourth transistor Qis turned off in response to the voltage at the first node N, and the third transistor Qis turned on in response to the voltage at the second node N, outputting the first voltage signal VGH to the third node N.

120 1201 1202 1 2 2 1 In one embodiment, the second signal output moduleformed by the first output unitand the second output unit, under the combined action of the voltages at the first node Nand the second node N, can output the second gate driving signal SCANof a type different from the first gate driving signal SCAN. The circuit structure is simple, which is beneficial for compressing the bezel of the display panel and achieving a narrow bezel design.

5 FIG. 5 FIG. 120 1203 1203 3 120 1203 1202 is a schematic structural diagram of another shift register provided in an embodiment of the present disclosure. Referring to, based on the above embodiment, in one embodiment, the second signal output modulefurther includes a coupling unit. The coupling unitis connected between the third node Nand a second control terminal of the second signal output module, and the coupling unitis configured to couple the potential of the second control terminal of the second signal output module.

3 1 1 1203 1202 4 4 3 2 1203 1 1 3 1 120 In one embodiment, during the process in which the third node Noutputs the first clock signal SCK, when the first clock signal SCKtransitions from a high level to a low level, under the coupling effect of the coupling unit, the potential of the second control terminal of the second signal output moduleis pulled low, improving the turn-on performance of the fourth transistor Q, ensuring that the fourth transistor Qis strongly turned on, ensuring signal output at the third node N, and facilitating improvement of the output stability of the second gate driving signal SCAN. The coupling unitincludes a first capacitor C. A first terminal of the first capacitor Cis connected to the third node N, and a second terminal of the first capacitor Cis connected to the second control terminal of the second signal output module.

6 FIG. 6 FIG. 130 130 2 130 130 130 1 130 1 2 is a structural schematic diagram of another shift register provided in an embodiment of the present disclosure. Referring to, on the basis of the above embodiments, the shift register further includes a first potential control module, a first control terminal of the first potential control moduleis connected to a second node N, a second control terminal of the first potential control modulereceives a voltage control signal VCS, an input terminal of the first potential control modulereceives a first voltage signal VGH, an output terminal of the first potential control moduleis connected to a first node N, and the first potential control moduleis configured to control a voltage of the first node Nbased on a voltage of the second node Nand the voltage control signal VCS.

5 FIG. 6 FIG. 2 3 120 2 1 130 2 1 1 2 1 2 In combination withand, when the voltage of the second node Ncauses a third transistor Qto be turned on, a second signal output moduleoutputs a long pulse width level of a second gate driving signal SCAN. During a process in which a start signal SIN releases control of the potential of the first node N, the first potential control moduleresponds to the voltage of the second node Nand the voltage control signal VCS to be turned on, transmitting the first voltage signal VGH to the first node Nto maintain the voltage of the first node N, thereby ensuring stability of the voltage of the second node N, and further improving output stability of a first gate driving signal SCANand the second gate driving signal SCAN.

7 FIG. 6 FIG. 7 FIG. 130 1301 1302 1301 2 1301 1301 1302 1302 1 1302 is a structural schematic diagram of another shift register provided in an embodiment of the present disclosure. Referring toand, on the basis of the above embodiments, the first potential control moduleincludes a first subunitand a second subunit, a control terminal of the first subunitis connected to the second node N, a first terminal of the first subunitreceives the first voltage signal VGH, a second terminal of the first subunitis connected to a first terminal of the second subunit, a second terminal of the second subunitis connected to the first node N, and a control terminal of the second subunitreceives the voltage control signal VCS.

1 110 2 1301 2 1302 1 1301 1302 1 110 2 In one embodiment, when the start signal SIN releases voltage control of the first node N, during a process in which a first signal output moduleoutputs a second voltage signal VGL to the second node N, the first subunitresponds to the voltage of the second node Nto be turned on, the second subunitresponds to the voltage control signal VCS to be turned on, and the first voltage signal VGH is transmitted to the first node Nvia the first subunitand the second subunit, maintaining the first node Nat a high level, thereby enabling the first signal output moduleto continuously output the second voltage signal VGL, ensuring stability of the voltage of the second node N.

1301 5 1302 6 5 2 5 5 6 6 1 6 5 6 5 6 In this embodiment, the first subunitincludes a fifth transistor Q, the second subunitincludes a sixth transistor Q, a control electrode of the fifth transistor Qis connected to the second node N, a first electrode of the fifth transistor Qreceives the first voltage signal VGH, a second electrode of the fifth transistor Qis connected to a first electrode of the sixth transistor Q, a second electrode of the sixth transistor Qis connected to the first node N, and a control electrode of the sixth transistor Qreceives the voltage control signal VCS. Here, a channel type of the fifth transistor Qis the same as a channel type of the sixth transistor Q, for example, both the fifth transistor Qand the sixth transistor Qare P-type transistors.

1 2 In one embodiment, the voltage control signal VCS may include a first clock signal SCKor a second clock signal SCKB.

8 FIG. 8 FIG. 2 2 1 1 2 6 6 1 1 1 is a waveform schematic diagram of a clock signal provided in an embodiment of the present disclosure. Referring to, a low-level duration Dof the second clock signal SCKB is greater than a low-level duration Dof the first clock signal SCK. When the second clock signal SCKB is used to control the control electrode of the sixth transistor Q, a turn-on duration of the sixth transistor Qcan be extended, thereby reducing a duration during which the first node Nis in a floating state during the process in which the start signal SIN releases control of the voltage of the first node N, which is beneficial for making the potential of the first node Nmore stable and improving the anti-interference capability of the shift register.

9 FIG. 9 FIG. 140 1 120 140 1 140 120 140 140 120 1 is a structural schematic diagram of another shift register provided in an embodiment of the present disclosure. Referring to, on the basis of the above embodiments, an auxiliary moduleis further included on a connection path between the first node Nand a first control terminal of the second signal output module, a first terminal of the auxiliary moduleis connected to the first node N, a second terminal of the auxiliary moduleis connected to the first control terminal of the second signal output module, a control terminal of the auxiliary modulereceives a third voltage signal VGLL, and the auxiliary moduleis configured to prevent a voltage of the first control terminal of the second signal output modulefrom being transmitted to the first node N.

4 1 3 3 1 1 4 140 4 4 1 1 1 7 1 1 In one embodiment, during a process in which a fourth transistor Qtransmits the first clock signal SCKto a third node N, when the voltage of the third node Ntransitions from a high level of the first clock signal SCKto a low level, under a coupling effect of a first capacitor C, a voltage of a fourth node Nis pulled to a lower level. By providing the auxiliary module, an extremely low level of the fourth node Ncan be isolated, preventing the extremely low level of the fourth node Nfrom being transmitted to the first node N, thereby ensuring that the voltage of the first node Nis not excessively low (when the voltage of the first node Ndrops to a value, a seventh transistor Qwill be turned off), which is beneficial for reducing bias voltages of transistors connected to the first node Nand improving stability of the transistors connected to the first node N.

140 7 7 7 1 7 120 In one embodiment, the auxiliary moduleincludes a seventh transistor Q, a control electrode of the seventh transistor Qreceives the third voltage signal VGLL, a first electrode of the seventh transistor Qis connected to the first node N, and a second electrode of the seventh transistor Qis connected to the first control terminal of the second signal output module.

1 7 4 4 1 4 2 2 4 7 1 4 1 2 In this embodiment, the level of the third voltage signal VGLL is lower than the level of the second voltage signal VGL. The advantage of this configuration is that when the first node Nis at the low level of the start signal SIN (e.g., VGL), since the third voltage signal VGLL is lower than the second voltage signal VGL, the seventh transistor Qis turned on more fully, allowing the voltage of the fourth node Nto reach the level of VGL, reducing threshold voltage loss during low-level transmission. This enables the fourth transistor Tto achieve a lower level under the coupling effect of the first capacitor C, providing a stronger driving force for the fourth transistor Twith the same size, thereby reducing the rise and fall times of the second gate drive signal SCAN, which is beneficial for improving the driving capability and stability of the second gate drive signal SCAN. Furthermore, when the fourth node Nis reduced to an extremely low level, the seventh transistor Qcan lower the voltage of the first node N(without reducing it to the voltage of the fourth node N). By maintaining the voltage of the first node Nat a lower level, it is advantageous for eliminating leakage current caused by incomplete turn-off of the second transistor T, thereby reducing unnecessary power consumption.

10 FIG. 10 FIG. 150 150 2 150 150 1 150 150 1 is a schematic structural diagram of another shift register provided by an embodiment of the present disclosure. Referring to, based on the above embodiments, the shift register further includes an input module. A first control terminal of the input moduleis connected to a third clock signal SCK, an input terminal of the input moduleis connected to the start signal SIN, an output terminal of the input moduleis connected to the first node N, and the input moduleis used to transmit the start signal SIN. By providing the input module, the timing at which the start signal SIN is transmitted to the first node Ncan be flexibly controlled.

2 2 150 2 1 150 150 2 1 The third clock signal SCKand the second clock signal SCKB are inverse signals to each other. When the input moduleis turned on in response to the third clock signal SCK, the start signal SIN can be transmitted to the first node Nvia the input module; when the input moduleis turned off in response to the third clock signal SCK, the start signal SIN ceases to control the voltage of the first node N.

10 FIG. 150 8 8 2 8 8 1 Continuing to refer to, the input moduleincludes an eighth transistor Q. A control electrode of the eighth transistor Qis connected to the third clock signal SCK, a first electrode of the eighth transistor Qis connected to the start signal SIN, and a second electrode of the eighth transistor Qis connected to the first node N.

11 FIG. 11 FIG. 150 150 2 150 9 9 2 9 8 9 1 is a schematic structural diagram of another shift register provided by an embodiment of the present disclosure. Referring to, based on the above embodiment, the input modulefurther includes a second control terminal, and the second control terminal of the input moduleis connected to the second clock signal SCKB. The input modulefurther includes a ninth transistor Q. A control electrode of the ninth transistor Qis connected to the second clock signal SCKB, a first electrode of the ninth transistor Qis connected to the first electrode of the eighth transistor Q, and a second electrode of the ninth transistor Qis connected to the first node N.

8 9 8 9 8 9 1 In this embodiment, the channel type of the eighth transistor Qis different from that of the ninth transistor Q. For example, the eighth transistor Qis a P-type transistor, and the ninth transistor Qis an N-type transistor. By providing the eighth transistor Qand the ninth transistor Qwith different channel types, the level loss when transmitting the start signal SIN is reduced, improving the transmission quality of the start signal SIN, which is beneficial for enhancing the reliability of the voltage at the first node N.

8 9 2 2 1 2 2 12 FIG. 12 FIG. In one embodiment, the eighth transistor Qand the ninth transistor Qare turned on simultaneously under the control of the second clock signal SCKB and the third clock signal SCK, which are inverse signals to each other.is a schematic diagram of a driving timing waveform of a shift register provided by an embodiment of the present disclosure, which is applicable to the shift register provided by any of the above embodiments. Referring to, the first clock signal SCK, the second clock signal SCKB, and the third clock signal SCKeach include alternating first-level pulses and second-level pulses. The voltage value of the first-level pulse is less than the voltage value of the second-level pulse. For example, the first-level pulse can be a low-level pulse, and the second-level pulse can be a high-level pulse. The setting of high and low level pulses ensures the normal operation of the shift register.

1 2 1 2 1 1 1 2 In one embodiment, the single pulse width of the first-level pulse of the first clock signal SCKis the same as the single pulse width of the first-level pulse of the third clock signal SCK, the single pulse width of the second-level pulse of the first clock signal SCKis the same as the single pulse width of the second-level pulse of the third clock signal SCK, and the single pulse width of the second-level pulse of the first clock signal SCKis greater than the single pulse width of the first-level pulse of the first clock signal SCK. That is, the waveform of the first clock signal SCKhas a different phase from the waveform of the third clock signal SCK.

1 2 1 2 2 1 1 2 1 2 2 1 2 The periods of the first clock signal SCKand the third clock signal SCKare both T, and the start time of the first first-level pulse of the first clock signal SCKdiffers from the start time of the first first-level pulse of the third clock signal SCKby T/2. The time of the second-level pulse of the third clock signal SCKcovers the time of the first-level pulse of the first clock signal line SCK, and the time of the second-level pulse of the first clock signal SCKcovers the time of the first-level pulse of the third clock signal SCK. Here, by controlling the phases of the first clock signal SCK, the second clock signal SCKB, and the third clock signal SCK, precise output of the first gate drive signal SCANand the second gate drive signal SCANcan be achieved during the operation of the shift register, ensuring that the shift register can operate normally.

2 2 2 2 2 In one embodiment, the second gate driving signal SCANincludes at least one first level pulse, and the duration of a single first level pulse of the start signal SIN is greater than or equal to the duration of a single first level pulse of the third clock signal SCK. For example, when the duration of a single first level pulse of the start signal SIN is equal to the duration of a single first level pulse of the third clock signal SCK, i.e., within the duration of the first level pulse of the start signal SIN, only one first level pulse of the third clock signal SCKis included, and at this time, the second gate driving signal SCANoutputs one first level pulse.

2 2 2 2 2 When the duration of a single first level pulse of the start signal SIN is greater than the duration of a single first level pulse of the third clock signal SCK, i.e., within the duration of the first level pulse of the start signal SIN, multiple first level pulses of the third clock signal SCKare included, and at this time, the second gate driving signal SCANoutputs multiple first level pulses. The number of first level pulses of the third clock signal SCKwithin the duration of the first level pulse of the start signal SIN is the same as the number of first level pulses of the second gate driving signal SCAN.

2 2 In this embodiment, by configuring the start signal SIN and the third clock signal SCK, multi-level pulse or single-level pulse output of the second gate driving signal SCANcan be achieved to meet different application requirements, which is beneficial for improving the compatibility of the gate driving circuit.

2 2 In one embodiment, the single pulse width of the first level pulse of the second gate driving signal SCANis the same as the single pulse width of the first level pulse of the start signal SIN, and the first level pulse of the second gate driving signal SCANis a short pulse width level.

1 1 2 2 1 In one embodiment, the first gate driving signal SCANincludes at least one second level pulse, and the pulse width of the second level pulse of the first gate driving signal SCANis equal to one period T of the third clock signal SCK. The start signal includes at least one first level pulse, and between two adjacent first level pulses of the start signal SIN, at least one first level pulse of the third clock signal SCKis interposed to form multiple second level pulses of the first gate driving signal SCAN.

1 2 1 The second level pulse of the first gate driving signal SCANis a short pulse width level. In this embodiment, by configuring the start signal SIN and the third clock signal SCK, multi-level pulse or single-level pulse output of the first gate driving signal SCANcan be achieved to meet different application requirements, which is beneficial for improving the compatibility of the gate driving circuit.

1 2 150 1 In one embodiment, this embodiment further includes a fourth clock signal SCKB, which is used to replace the second clock signal SCKB in the next-stage shift register to control the on/off of the input module. When proceeding to the next-next-stage shift register, it reverts to the fourth clock signal SCKB, thereby achieving the shift output of the gate driving signal.

11 12 FIGS.and Referring to, the operation process of the shift register provided in this embodiment is as follows:

0 1 4 1 2 1 3 2 In the Tphase, the start signal SIN is a high-level pulse (second level pulse), the voltages of the first node Nand the fourth node Nremain high under the action of the first capacitor C, the second node Noutputs a long pulse width level (low level) of the first gate driving signal SCAN, and the third node Noutputs a long pulse width level (high level) of the second gate driving signal SCAN.

1 1 2 2 8 9 1 1 1 1 2 1 In the Tphase, the start signal SIN is a low-level pulse (first level pulse), the first clock signal SCKis a high-level pulse (second level pulse), the second clock signal SCKB is a high-level pulse (second level pulse), and the third clock signal SCKis a low-level pulse (first level pulse). Therefore, the eighth transistor Qand the ninth transistor Qare turned on, transmitting the start signal SIN to the first node N, and the potential of the first node Nis low. The first transistor Qis turned on in response to the voltage of the first node Nand outputs a first voltage signal VGH to the second node N, i.e., outputting a short pulse width level of the first gate driving signal SCAN.

1 7 4 1 4 4 1 3 2 Under the action of the voltage of the first node Nand the third voltage signal VGLL, the seventh transistor Qis turned on, and the voltage of the fourth node Ncan reach the same low level as the first node N, causing the fourth transistor Qto be turned on. The fourth transistor Qtransmits the high level of the first clock signal SCKto the third node N, i.e., outputting a long pulse width level of the second gate driving signal SCAN.

2 1 2 2 8 9 1 1 3 1 2 1 4 4 7 1 7 1 2 In the Tphase, the start signal SIN is a high-level pulse (second level pulse), the first clock signal SCKis a low-level pulse (first level pulse), the second clock signal SCKB is a low-level pulse (first level pulse), and the third clock signal SCKis a high-level pulse (second level pulse). The eighth transistor Qand the ninth transistor Qare turned off, and the start signal SIN releases control over the voltage of the first node N. Since the first clock signal SCKtransitions from high to low, and the third node Noutputs the first clock signal SCK, i.e., outputting a short pulse width level of the second gate driving signal SCAN, under the coupling effect of the first capacitor C, the voltage of the fourth node Nis pulled to a lower voltage level to ensure strong conduction of the fourth transistor Q. At this time, under the action of the seventh transistor Q, the voltage of the first node Ndoes not decrease significantly; otherwise, the seventh transistor Qwould be turned off. Since the voltage of the first node Nremains low, the voltage of the second node Nremains unchanged.

3 1 3 2 8 9 1 2 In the Tphase, the first clock signal SCKtransitions from low to high, and the third node Noutputs a long pulse width level of the second gate driving signal SCAN. The eighth transistor Qand the ninth transistor Qremain off, and the voltages of the first node Nand the second node Nremain unchanged.

4 1 2 2 8 9 1 1 2 1 2 2 1 3 2 3 3 3 2 In the Tphase, the start signal SIN is a high-level pulse (second-level pulse), the first clock signal SCKis a high-level pulse (second-level pulse), the second clock signal SCKB is a high-level pulse (second-level pulse), and the third clock signal SCKis a low-level pulse (first-level pulse). The eighth transistor Qand the ninth transistor Qare turned on, transmitting the start signal SIN to the first node N, where the voltage of the first node Nis at a high level. The second transistor Qis turned on in response to the voltage of the first node N, and transmits the second voltage signal VGL to the second node N, i.e., the second node Noutputs a long pulse width level of the first gate drive signal SCAN. The third transistor Qis turned on in response to the voltage of the second node N, and the first voltage signal VGH is transmitted through the third transistor Qto the third node N, i.e., the third node Noutputs a long pulse width level of the second gate drive signal SCAN.

2 1 2 5 6 1 1 2 Under the action of the voltage of the second node Nand the first clock signal SCK(or the second clock signal SCKB), the fifth transistor Qand the sixth transistor Qare turned on, transmitting the first voltage signal VGH to the first node Nto maintain the high level of the first node N, thereby stabilizing the voltage of the second node N.

13 FIG. 11 FIG. 12 FIG. 13 FIG. 2 2 2 2 2 is a schematic diagram of a drive timing waveform of another shift register provided in an embodiment of the present disclosure, which is also applicable to the shift register shown in. Different from the timing shown in, in the timing shown in, when the duration of a single first-level pulse of the start signal SIN is greater than the duration of a single first-level pulse of the third clock signal SCK, within the duration of the first-level pulse of the start signal SIN, multiple first-level pulses of the third clock signal SCKare included, and the second gate drive signal SCANoutputs multiple first-level pulses. In this embodiment, the number of first-level pulses of the third clock signal SCKwithin the duration of the first-level pulse of the start signal SIN is the same as the number of first-level pulses of the second gate drive signal SCAN.

14 FIG. 11 FIG. 12 FIG. 14 FIG. 14 FIG. 13 14 FIGS.and 1 1 2 2 1 is a schematic diagram of a drive timing waveform of another shift register provided in an embodiment of the present disclosure, which is also applicable to the shift register shown in. Different from the timing shown in, in the timing shown in, the first gate drive signal SCANincludes multiple second-level pulses, and the pulse width of the second-level pulses of the first gate drive signal SCANis equal to one period T of the third clock signal SCK. In one embodiment, the start signal includes multiple first-level pulses (such as two first-level pulses in), and between two adjacent first-level pulses of the start signal SIN, at least one first-level pulse of the third clock signal SCKis arranged at an interval, to form multiple second-level pulses of the first gate drive signal SCAN. The working process of the shift register corresponding to the drive timings shown inwill not be described in detail here.

15 FIG. is a schematic structural diagram of another shift register provided in an embodiment of the present disclosure.

15 FIG. 2 2 2 1 1 Referring to, based on the above embodiments, the second transistor Qis a vertical dual-gate transistor, and the second transistor Qincludes a first gate and a second gate. The first gate of the second transistor Qand the control electrode of the first transistor Qare both connected to the first node N.

160 1 2 160 2 160 2 1 2 2 The shift register further includes a second potential control module, which is connected between the first node Nand the second gate of the second transistor Q. The control terminal of the second potential control moduleis connected to the second node N. The second potential control moduleis used to control the voltage of the second gate of the second transistor Qaccording to the voltage of the first node Nand the voltage of the second node N, which is beneficial to reducing the leakage current of the second transistor Q.

16 FIG. In one embodiment,is a schematic structural diagram of another shift register provided in an embodiment of the present disclosure.

16 FIG. 160 2 10 10 2 10 10 2 2 2 2 1 Referring to, the second potential control moduleincludes a second capacitor Cand a tenth transistor Q. The first gate of the tenth transistor Qis connected to the second node N, the first electrode of the tenth transistor Qis connected to a third voltage signal VGLL, the second electrode of the tenth transistor Qis connected to the second gate of the second transistor Q, the first terminal of the second capacitor Cis connected to the second gate of the second transistor Q, and the second terminal of the second capacitor Cis connected to the first node N.

1 2 10 2 2 2 2 2 In one embodiment, when the voltage of the first node Njumps from a high level to a low level, the voltage of the second node Nis at a high level, causing the tenth transistor Qto be turned on, transmitting the third voltage signal VGLL to the second gate of the second transistor Q, and the voltage of the second gate of the second transistor Qis VGLL, thereby making the threshold state of the second transistor Qcontrollable. By adjusting the threshold voltage of the second transistor Q, the leakage current of the second transistor Qcan be reduced.

1 10 2 2 When the voltage of the first node Njumps from a low level to a high level, the tenth transistor Qis turned off. Under the coupling effect of the second capacitor C, the voltage of the second gate of the second transistor Qincreases, adjusting the threshold voltage of the second transistor to be negatively biased, enhancing the conduction capability of the second transistor. In another optional implementation manner provided by the present disclosure,

17 FIG. is a schematic structural diagram of another shift register provided in an embodiment of the present disclosure.

17 FIG. 120 130 120 130 1 1 120 130 2 130 1 2 120 2 1 2 Referring to, the shift register includes a second signal output moduleand a first potential control module. The first control terminal of the second signal output moduleand the output terminal of the first potential control moduleare connected to the first node N. The first node Nis used to receive the start signal SIN. The second control terminal of the second signal output moduleand the first control terminal of the first potential control moduleare connected to the second node N. The first potential control moduleis used to control the voltage of the first node Naccording to the voltage of the second node N. The second signal output moduleis used to output the second gate drive signal SCANaccording to the voltage of the first node Nand the voltage of the second node N.

2 120 120 2 1 130 2 1 1 2 2 In one embodiment, when the voltage at the second node Ncauses the second signal output moduleto be turned on, the second signal output moduleoutputs a long pulse width level of the second gate driving signal SCAN. During the process where the start signal SIN releases the voltage control of the first node N, the first potential control moduleresponds to the voltage at the second node Nand the voltage control signal VCS to be turned on, transmitting the first voltage signal VGH to the first node Nto maintain the voltage at the first node N, thereby ensuring the stability of the voltage at the second node Nand consequently the stability of the second gate driving signal SCAN.

9 9 In other embodiments, the ninth transistor Qmay also be configured as a vertical dual-gate transistor to reduce the off-state leakage current of the ninth transistor Q.

In one embodiment, the first gate of the N-type transistor is a top gate, and the second gate of the N-type transistor is a bottom gate; or, the first gate of the N-type transistor is a bottom gate, and the second gate of the N-type transistor is a top gate, which can be set according to actual requirements.

18 FIG. is a schematic structural diagram of another shift register provided by an embodiment of the present disclosure.

18 FIG. 130 130 120 120 1 120 1 1 2 2 Referring to, based on the above embodiments, the first potential control modulefurther includes a second control terminal, and the second control terminal of the first potential control moduleis connected to the voltage control signal VCS; a first input terminal of the second signal output moduleis connected to the first voltage signal VGH, a second input terminal of the second signal output moduleis connected to the first clock signal SCK, and the second signal output moduleis configured to output the first voltage signal VGH or the first clock signal SCKin response to the voltage at the first node Nand the voltage at the second node N, to output the second gate driving signal SCAN.

19 FIG. is a schematic structural diagram of another shift register provided by an embodiment of the present disclosure.

19 FIG. 1 2 1 2 2 1 1 2 Referring to, in one embodiment, the voltage control signal VCS includes the first clock signal SCKor the second clock signal SCKB; both the first clock signal SCKand the second clock signal SCKB include alternately arranged first level pulses and second level pulses, the time of the first level pulse of the second clock signal SCKB covers the time of the first level pulse of the first clock signal SCK, and the time of the second level pulse of the first clock signal SCKcovers the time of the second level pulse of the second clock signal SCKB. In one embodiment, the voltage value of the first level pulse is less than the voltage value of the second level pulse.

130 1301 1302 1301 2 1301 1301 1302 1302 1 1302 In one embodiment, the first potential control moduleincludes a first sub-unitand a second sub-unit, a control terminal of the first sub-unitis connected to the second node N, a first terminal of the first sub-unitis connected to the first voltage signal VGH, a second terminal of the first sub-unitis connected to a first terminal of the second sub-unit, a second terminal of the second sub-unitis connected to the first node N, and a control terminal of the second sub-unitis connected to the voltage control signal VCS.

1 1301 2 1302 1 1301 1302 1 110 2 In one embodiment, when the start signal SIN releases the voltage control of the first node N, the first sub-unitis turned on in response to the voltage at the second node N, the second sub-unitis turned on in response to the voltage control signal VCS, and the first voltage signal VGH is transmitted to the first node Nthrough the first sub-unitand the second sub-unit, maintaining the first node Nat a high level, thereby causing the first signal output moduleto continuously output the second voltage signal VGL, ensuring the stability of the voltage at the second node N.

1301 5 1302 6 5 2 5 5 6 6 1 6 5 6 5 6 In this embodiment, the first sub-unitincludes a fifth transistor Q, the second sub-unitincludes a sixth transistor Q, a control electrode of the fifth transistor Qis connected to the second node N, a first electrode of the fifth transistor Qis connected to the first voltage signal VGH, a second electrode of the fifth transistor Qis connected to a first electrode of the sixth transistor Q, a second electrode of the sixth transistor Qis connected to the first node N, and a control electrode of the sixth transistor Qis connected to the voltage control signal VCS. Here, the channel type of the fifth transistor Qis the same as the channel type of the sixth transistor Q. For example, both the fifth transistor Qand the sixth transistor Qare P-type transistors.

2 1 2 6 6 1 1 1 In this embodiment, the low-level duration of the second clock signal SCKB is greater than the low-level duration of the first clock signal SCK. When the second clock signal SCKB is used to control the control electrode of the sixth transistor Q, the turn-on duration of the sixth transistor Qcan be extended, thereby reducing the duration during which the first node Nis in a floating state during the process where the start signal SIN releases the voltage control of the first node N, which is beneficial for making the potential of the first node Nmore stable and improving the anti-interference capability of the shift register.

15 FIG. 110 150 140 160 In one embodiment, referring to, the shift register further includes a first signal output module, an input module, an auxiliary module, and a second potential control module, and the specific working principles and structures thereof can be referred to the relevant descriptions in the above embodiments, which will not be repeated here.

20 FIG. In one embodiment, an embodiment of the present disclosure further provides a display panel, which includes a gate driving circuit, and the gate driving circuit includes the shift register provided by any embodiment of the present disclosure, having the beneficial effects described in any of the above embodiments.is a schematic structural diagram of a gate driving circuit provided by an embodiment of the present disclosure.

15 FIG. 20 FIG. 11 11 11 120 11 11 Referring toand, a plurality of shift registersare connected in cascade. In the plurality of cascaded shift registers, the start signal SIN input to a next-stage shift registeris provided by the output terminal of the second signal output moduleof the current-stage shift register, and the start signal SIN of the first-stage shift registeris provided by the trigger signal line RL.

21 FIG. 11 11 11 11 11 11 is a schematic diagram of driving timing waveforms of another shift register provided in an embodiment of the present disclosure. The first gate driving signal SCAN1<1> output by the first-stage shift register, the first gate driving signal SCAN1<2> output by the second-stage shift register, and the first gate driving signal SCAN1<3> output by the third-stage shift registerare shifted stage by stage. The second gate driving signal SCAN2<1> output by the first-stage shift register, the second gate driving signal SCAN2<2> output by the second-stage shift register, and the second gate driving signal SCAN2<3> output by the third-stage shift registerare shifted stage by stage.

20 FIG. 21 FIG. 11 1 2 3 1 2 11 2 11 11 130 150 150 11 110 1 11 120 2 11 120 1 11 150 2 11 150 3 11 With reference toand, the shift registerincludes an input terminal IN, a first clock signal terminal CK, a second clock signal terminal CK, a third clock signal terminal CK, a first output terminal OUT, and a second output terminal OUT. The input terminal IN of the next-stage shift registeris connected to the second output terminal OUTof the current-stage shift register. The shift registerfurther includes a first potential control moduleand an input module. The input terminal of the input moduleserves as the input terminal IN of the shift register. The output terminal of the first signal output moduleserves as the first output terminal OUTof the shift register. The output terminal of the second signal output moduleserves as the second output terminal OUTof the shift register. The second input terminal of the second signal output moduleserves as the first clock signal terminal CKof the shift register. The second control terminal of the input moduleserves as the second clock signal terminal CKof the shift register. The first control terminal of the input moduleserves as the third clock signal terminal CKof the shift register.

1 2 3 4 3 11 3 3 11 1 2 11 4 2 11 2 1 11 1 1 11 3 The display panel further includes a first signal line CLK, a second signal line CLK, a third signal line CLK, and a fourth signal line CLK. The third clock signal terminal CKof the odd-stage shift registeris connected to the third signal line CLK, and the third clock signal terminal CKof the even-stage shift registeris connected to the first signal line CLK. The second clock signal terminal CKof the odd-stage shift registeris connected to the fourth signal line CLK, and the second clock signal terminal CKof the even-stage shift registeris connected to the second signal line CLK. The first clock signal terminal CKof the odd-stage shift registeris connected to the first signal line CLK, and the first clock signal terminal CKof the even-stage shift registeris connected to the third signal line CLK.

1 1 1 2 2 4 2 3 1 2 The first clock signal SCKtransmitted on the first signal line CLKand the fourth clock signal SCKB transmitted on the second signal line CLKare inverse signals of each other. The second clock signal SCKB transmitted on the fourth signal line CLKand the third clock signal SCKtransmitted on the third signal line CLKare inverse signals of each other. By configuring the timing of each clock signal, stable output of the first gate driving signal SCANand the second gate driving signal SCANcan be achieved.

1 2 3 4 In one embodiment, the first signal line CLK, the second signal line CLK, the third signal line CLK, and the fourth signal line CLKmay be respectively connected to different pins of a driving chip to output different clock signals.

22 FIG. 1 2 1 3 2 1 1 4 3 2 is a schematic structural diagram of a gate driving circuit provided in an embodiment of the present disclosure. The display panel further includes a first inverter Iand a second inverter I. The first signal line CLKand the third signal line CLKare respectively connected to different pins of the driving chip. The second signal line CLKis connected to the first signal line CLKvia the first inverter I, and the fourth signal line CLKis connected to the third signal line CLKvia the second inverter I, which helps reduce the number of pins of the driving chip and optimize the connection resources of the driving chip, thereby further reducing the power consumption of the driving chip.

1 1 3 2 1 4 3 1 150 11 2 11 1 11 1 2 3 4 2 4 The display panel further includes a first inverter I. The first signal line CLKand the third signal line CLKare respectively connected to different pins of the driving chip. The second signal line CLKis connected to the first signal line CLK, and the fourth signal line CLKis connected to the third signal line CLK. The first inverter Iis connected between the second control terminal of the input modulein the shift registerand the second clock signal terminal CKof the shift register. The first inverter Iis integrated inside the shift register. In one embodiment, the first signal line CLKcan be used to multiplex the second signal line CLK, and the third signal line CLKcan be used to multiplex the fourth signal line CLK, thereby saving the number of the second signal line CLKand the fourth signal line CLK, which is beneficial for improving PPI.

In this embodiment, the display panel can be applied to a mobile phone, and can also be applied to any electronic product with a display function, including but not limited to the following categories: televisions, notebook computers, desktop monitors, tablet computers, digital cameras, smart bracelets, smart glasses, vehicle-mounted displays, medical devices, industrial control devices, touch interaction terminals, etc., which are not specifically limited in the embodiments of the present disclosure.