Semiconductive memory device capable of carrying out a write-in operation at a high speed

1. A semiconductive memory device comprising a plurality of memory cells and writing data in a specific one of said memory cells in accordance with a write-in address, comprising: control signal producing means for producing a plurality of control signals in accordance with a synchronous signal, said control signals having phases different from one another; column selection signal producing means that receives the control signals, the column selection signal producing means being responsive to said write-in address and said control signals for producing a plurality of column selection signals, the column selection signals being dependent on the control signals input to the column selection signal producing means; latch means for latching said data as latched data in synchronism with said control signals; write bus means for supplying said latched data to said memory cells; and write-in means for writing said latched data on said write bus means in said specific memory cell in accordance with said column selection signals.

2. A semiconductive memory device as claimed in claim 1, wherein said semiconductive memory device further comprises switching means positioned between said write bus means and said memory cells, said switching means being switched in accordance with said column selection signals.

3. A semiconductive memory device as claimed in claim 1, wherein said column selection signal producing means latches an input address signal based on said write-in address in accordance with said control signals to produce said column selection signals.

4. A semiconductive memory device as claimed in claim 1, wherein said write bus means has at least two write bus pairs.

5. A semiconductive memory device as claimed in claim 4, wherein said write bus means has first and second write bus pairs.

6. A semiconductive memory device as claimed in claim 5, wherein said control signal producing means produces first and second control signals in accordance with said synchronous signal.

7. A semiconductive memory device as claimed in claim 6, wherein: said write-in means comprises first and second switching circuits which are switched on the basis of said column selection signals; said first bus pair being connected to said memory cells through said first switching circuit; and said second bus pair being connected to said memory cells through said second switching circuit.

8. A semiconductive memory device as claimed in claim 7, wherein: said column selection signal producing means latches said input address signal in accordance with said first control signal to produce a first column selection signal, said column selection signal producing means latches said input address signal in accordance with said second control signal to produce a second column selection signal; said first switching circuit being switched on the basis of said first column selection signal; and said second switching circuit being switched on the basis of said second column selection signal.

9. A semiconductive memory device as claimed in claim 8, wherein said latched data are held on said either one of said first and said second write bus pairs during two cycles to be written in said specific memory cell.

10. A semiconductor memory device as claimed in claim 1, wherein said control signal producing means comprises a delay circuit that receives the synchronous signal and at least two circuit elements that receive an output signal from the delay circuit, the circuit elements outputting the plurality of control signals.

11. A semiconductive memory device comprising: a plurality of memory cells capable of having data written into a specific one of said memory cells in accordance with a write-in address; a control signal producing circuit that receives a synchronous signal and produces a plurality of control signals based on the synchronous signal, said control signals having phases different from one another; a column selection signal producing device that receives the control signals and produces column selection signals based at least on the received control signals; a latch device that latches said data as latched data in synchronism with said control signals; and a write-in device that receives the latched data from the latch device and writes said latched data in said specific memory cell in accordance with said column selection signals.

12. A semiconductive memory device as claimed in claim 11, wherein said semiconductive memory device further comprises a switching circuit positioned between said latch device and said memory cells, said switching circuit switching in accordance with said column selection signals.

13. A semiconductive memory device as claimed in claim 11, wherein said column selection signal producing device latches an input address signal based on said write-in address in accordance with said control signals to produce said column selection signals.

14. A semiconductive memory device as claimed in claim 11, further comprising a first write bus and a second write bus, said first and second write buses supplying said latched data to the write-in device.

15. A semiconductive memory device as claimed in claim 14, wherein said control signal producing circuit produces first and second control signals in accordance with said synchronous signal.

16. A semiconductive memory device as claimed in claim 15, wherein: said write-in device comprises first and second switching circuits which are switched on the basis of said column selection signals; said first write bus being connected to said memory cells through said first switching circuit; and said second write bus being connected to said memory cells through said second switching circuit.

17. A semiconductive memory device as claimed in claim 16, wherein: said column selection signal producing device latches said input address signal in accordance with said first control signal to produce a first column selection signal, said column selection signal producing device latches said input address signal in accordance with said second control signal to produce a second column selection signal; said first switching circuit being switched on the basis of said first column selection signal; and said second switching circuit being switched on the basis of said second column selection signal.

18. A semiconductive memory device as claimed in claim 17, wherein said latched data are held on said either one of said first write bus and said second write bus during two cycles to be written in said specific memory cell.

19. A semiconductor device as claimed in claim 17, wherein said latched data is held on the column selection line for two cycles and during said two cycles the data is transferred to the bus selected by said column selection signal.

20. A semiconductor memory device as claimed in claim 11, wherein said control signal producing circuit comprises a delay circuit that receives the synchronous signal and at least two circuit elements that receive an output signal from the delay circuit, the circuit elements outputting the plurality of control signals.