Apparatus for performing real time caching utilizing an execution quantization timer and an interrupt controller

1. A data processing system comprising: a central processing unit; a multi-port cache array coupled to said central processing unit; a cache loader, coupled to said multi-port cache array; a main memory unit, comparatively slow to said cache array, coupled to said cache loader; a plurality of asynchronous clock interrupts, coupled to said central processing unit; an interrupt controller, coupled to said central processing unit, for managing real time data streams into said cache array; an execution quantizer coupled to said interrupt controller, wherein said execution quantizer limits any interrupts on said central processing unit from said plurality of asynchronous clock interrupts from executing after a fixed execution quantization (EQ) time; and gating logic, coupled to said execution quantizer, for gating off any interrupts received during a cache load or cache unload operation of a quantized block so as to allow said interrupts to be processed after completion of said cache load or unload operation.

2. The invention according to claim 1 wherein said multi-port cache array further comprises a first partition, coupled to said main memory and a second partition, coupled to said central processing unit, and a third partition, coupled to said first and second partitions and said central processing unit wherein a portion of an operating system is stored in said third partition.

3. The invention according to claim 1 wherein said quantization timer also perform latching and time stamping all interrupts received by said gating logic for later execution according to their time of receipt.

4. The invention according to claim 1 wherein said interrupt controller further performs loading of a quantization block while another quantization block is being executed.

5. The invention according to claim 1 wherein an operating system executes between quantization blocks in a time frame denoted as a quantization boundary.

6. The invention according to claim 2 wherein one of said partitions is accessed by said cache loader and the other partition is accessed by said central processing unit, but both partitions are not be accessed by both said cache loader and said CPU simultaneously.

7. A data processing system comprising: a central processing unit; a multi-port cache array coupled to said central processing unit; a cache loader, coupled to said multi-port cache array; a plurality of asynchronous memory units, comparatively slow to said cache array, coupled to said cache loader; a plurality of asynchronous clock interrupts, coupled to said central processing unit; an interrupt controller, coupled to said central processing unit, that manages real time data streams from said plurality of asynchronous memory units to said cache array as directed by any of said of asynchronous clock interrupts; an execution quantizer, coupled to said interrupt controller, wherein said execution quantizer limits any interrupts on said central processing unit from said plurality of asynchronous clock interrupts from executing after a fixed execution quantization (EQ) time; and a gating logic, coupled to said execution quantizer for gating off any interrupts received during a cache load or unload operation of a quantized block so as to allow said interrupts to be processed after completion of said cache load or unload operation.

8. The data processing system according to claim 7, wherein said multi-port cache array further comprises a first partition, coupled to said main memory, and a second partition, coupled to said central processing unit, wherein one of said partitions is accessed by said cache loader and the other partition is accessed by said central processing unit in an asynchronous manner, but not simultaneously.

9. The data processing system according to claim 7, further comprising a master clock, coupled to said central processing unit, wherein said master clock clocks all tasks executed by said central processing unit and provides coordination among said plurality of asynchronous clock interrupts.