Single-poly EEPROM cell structure operations and array architecture

1. A single-poly EEPROM cell comprising: an inverter comprising: a p-well formed in a substrate; a gate structure formed atop said p-well and being formed from a thin gate oxide layer underneath a conductive layer; an n-base formed adjacent to a first edge of said gate structure and within said p-well; a p+ region formed within said n-base; and a n+ region adjacent a second edge of said gate structure and within said p-well; and a capacitive coupling area, said capacitive coupling area being formed from a second p-well formed in said substrate and a floating gate, said floating gate formed from said conductive layer and capacitively coupled to said second p-well.

2. The EEPROM cell of claim 1 further wherein said second p-well has formed within itself a second p+ region.

3. The EEPROM cell of claim 1 wherein said cell is programmed by biasing said second p-well, said p-well, and said n+ region to a voltage V.sub.cc and said p+ region to -V.sub.cc.

4. The EEPROM cell of claim 1 wherein said cell is erased by biasing said second p-well and said p+ region to a voltage -V.sub.cc and said p-well and said n+ region to V.sub.cc.

5. The EEPROM cell of claim 1 wherein said cell is read by biasing said second p-well and said n+ region to a voltage V.sub.cc and grounding said p+ region.

6. A single-poly EEPROM cell comprising: an inverter comprising: an n-well formed in a substrate; a gate structure formed atop said n-well and being formed from a thin gate oxide layer underneath a conductive layer; a p-base formed adjacent to a first edge of said gate structure and within said p-well; an n+ region formed within said p-base; and a p+ region adjacent a second edge of said gate structure and within said n-well; and a capacitive coupling area, said capacitive coupling area being formed from a second n-well formed in said substrate and a floating gate, said floating gate formed from said conductive layer and capacitively coupled to said second n-well.

7. The EEPROM cell of claim 6 further wherein said second n-well has formed within itself a second n+ structure.

8. The EEPROM cell of claim 6 wherein said cell is programmed by biasing said second n-well, said n-well, and said p+ region to a voltage V.sub.cc and said n+ region to -V.sub.cc.

9. The EEPROM cell of claim 6 wherein said cell is erased by biasing said second n-well and said n+ region to a voltage -V.sub.cc and said n-well and said p+ region to V.sub.cc.

10. The EEPROM cell of claim 6 wherein said cell is read by biasing said second n-well and said p+ region to a voltage V.sub.cc and grounding said n+ region.