Transistor stack read only memory

1. A read only memory, comprising: a first bitline; a second bitline; multiple transistor stacks coupled to each of the first and second bitlines, each transistor stack comprising at least four switching devices connected in series and having a single connection to an operating potential, some of the at least four switching devices being programmed by forming a metal short circuit across said some of the at least four switching devices wherein a conductive path is established across said some of the at least four switching devices; and amultiplexer coupled to the first and second bitlines and to a sense amplifier for selectively coupling one of the first and second bitlines to the sense amplifier.

2. The read only memory of claim 1 wherein said switching devices are FETs.

3. The read only memory of claim 2 wherein one logic level is stored by forming a conductive path from source to drain bypassing a channel of an FET.

4. The read only memory of claim 3 wherein each transistor stack comprises precharge circuitry, said precharge circuitry, during a precharge phase, applying a known logic signal to at least one of a top-most transistor and a bottom-most transistor in the stack.

5. The read only memory of claim 4 further comprising select circuitry coupled in series with the stack, and coupled to a first circuit node.

6. The read only memory of claim 5 wherein the precharge circuitry applies a known logic signal to the first circuit node.