Legal claims defining the scope of protection, as filed with the USPTO.
1. An input/output (I/O) buffer circuit, comprising: a first output driver stage operably coupled to an input/output node and configured to drive the input/output node, wherein the first output driver is enabled when resistive termination of a transmission line connected to the input/output node is not required; a second output driver stage operably coupled to the input/output node and configured to drive the input/output node with an electrical resistance substantially equal to a characteristic impedance of the transmission line, wherein the second output driver stage is enabled when resistive termination of the transmission line is required; an input termination stage operably coupled to the input/output node and configured to: (i) provide resistive termination of the transmission line for a period of time following a transition of an input signal, and (ii) reinforce said input signal following said period of time such that electrical power dissipation within the I/O buffer circuit is reduced; and wherein said period of time is substantially equal to the amount of time it takes the input signal to propagate the length of the transmission line.
2. The input/output (I/O) buffer circuit as recited in claim 1, wherein the first output driver comprises a first switching element having a resistive value selectively coupled solely between the input/output node and an electrical potential.
3. The input/output (I/O) buffer circuit as recited in claim 2, wherein the electrical potential comprises ground or a voltage exceeding ground.
4. The input/output (I/O) buffer circuit as recited in claim 1, wherein the second output driver comprises a second switching element coupled in series with a resistor between the input/output node and an electrical potential.
5. The input/output (I/O) buffer circuit as recited in claim 4, wherein the electrical potential comprises ground or a voltage exceeding ground.
6. The input/output (I/O) buffer circuit as recited in claim 4, wherein the sum of a resistive value attributed to the second switching element and the resistor is substantially equal to the characteristic impedance of the transmission line coupled to the input/output node.
7. The input/output (I/O) buffer circuit as recited in claim 6, wherein the sum is substantially equal to the impedance during times when the second switching element is in a high conductance state.
8. The input/output (I/O) buffer circuit as recited in claim 1, wherein said input termination stage comprises: a resistive element having a first and second terminals, wherein the first terminal connected to the input/output node; and a mechanism for maintaining a high conductance connection of the second terminal to an electrical potential for said period of time following the transition of said input signal.
9. The input/output (I/O) buffer circuit as recited in claim 8, wherein the mechanism further changes the high conductance connection to a low conductance connection subsequent to expiration of said period of time.
10. The input/output (I/O) buffer circuit as recited in claim 8, wherein the high conductance connection comprises a switching element responsive to a delayed signal forwarded from a time delay unit, wherein the switching element is coupled between the second terminal and the electrical potential.
11. The input/output (I/O) buffer circuit as recited in claim 8, wherein the electrical potential comprises ground or a voltage exceeding ground.
12. An input/output (I/O) buffer circuit, comprising: an input/output node; a first output driver stage comprising a first pair of switching elements, wherein one of said first pair of switching elements is coupled between the input/output node and a power supply potential, and wherein the other of said first pair of switching elements is coupled between the input/output node and a ground potential, and wherein the first output driver stage is enabled when resistive termination of a transmission line connected to the input/output node is not required; a second output driver stage comprising a second pair of switching elements and a pair of electrically resistive elements, wherein one of said second pair of switching elements is coupled in series with one of said pair of electrically resistive elements between the input/output node and the power supply potential, and wherein the other of said second pair of switching elements is coupled in series with the other of said pair of electrically resistive elements between the input/output node and the ground potential, and wherein the second output buffer stage is enabled when resistive termination of the transmission line is required; an input termination stage comprising a termination node and a resistive element coupled between the input/output node and the termination node, and wherein the termination node is selectively coupled to either the power supply potential or the ground potential, and wherein the resistive element provides resistive termination of the transmission line for a predetermined time period following transitions of an input signal, and wherein the resistive element reinforces said input signal following said time period such that electrical power dissipation within the I/O buffer circuit is reduced; and wherein said time period is substantially equal to the amount of time it takes the input signal to propagate the length of the transmission line.
13. The I/O buffer as recited in claim 12, wherein the first driver section comprises: a p-channel metal oxide semiconductor (MOS) transistor coupled between the input/output node and the power supply potential; and an n-channel MOS transistor coupled between the input/output node and the ground potential.
14. The I/O buffer as recited in claim 12, wherein the second driver section comprises: a p-channel metal oxide semiconductor (MOS) transistor coupled in series with the one of the pair of resistive elements between the input/output node and the power supply potential; and an n-channel MOS transistor coupled in series with the other of the pair of resistive elements between the input/output node and the ground potential.
15. The I/O buffer as recited in claim 12, wherein the sum of an intrinsic resistance of the one of said second pair of switching elements and the resistance of the one of said pair of electrically resistive elements is substantially equal to a characteristic impedance of the transmission line.
16. The I/O buffer as recited in claim 12, wherein the sum of an intrinsic resistance of the other of said second pair of switching elements and the resistance of the other of said pair of electrically resistive elements is substantially equal to a characteristic impedance of the transmission line.
17. The I/O buffer as recited in claim 12, wherein the electrical resistance of the resistive element of the input termination stage is substantially equal to the characteristic impedance of the transmission line.
18. The I/O buffer as recited in claim 12, further comprising a differential amplifier having two input terminals and an output terminal, wherein a first input terminal of the differential amplifier is connected to the input/output node, and wherein a second terminal of the differential amplifier is connected to a reference potential, and wherein the differential amplifier is configured to produce the input signal at the output terminal.
19. The I/O buffer as recited in claim 18, wherein the input termination unit further comprises a time delay unit coupled to receive the input signal produced by the differential amplifier and configured to produce a time-delayed input signal at an output terminal following a predetermined delay time, and wherein the time-delayed input signal determines whether the termination node is coupled to the power supply potential or the ground potential.
20. The I/O buffer as recited in claim 19, wherein when the input signal transitions from a logic low level to a logic high level, the termination node is first coupled to the ground potential, and wherein after the predetermined delay time of the time delay unit has elapsed, the termination node is coupled to the power supply potential.
21. The I/O buffer as recited in claim 19, wherein when the input signal transitions from a logic high level to a logic low level, the termination node is first coupled to the power supply potential, and wherein after the predetermined delay time of the time delay unit has elapsed, the termination node is coupled to the ground potential.
22. An input/output (I/O) buffer circuit, comprising: an input/output node; a first output driver stage, comprising: a first p-channel metal oxide semiconductor (MOS) transistor coupled between the input/output node and a power supply potential; a first n-channel MOS transistor coupled between the input/output node and a ground potential; and wherein the first output driver stage is enabled when resistive termination of a transmission line connected to the input/output node is not required; a second output driver stage, comprising: a second p-channel MOS transistor coupled in series with a first resistive element between the input/output node and the power supply potential; a second n-channel MOS transistor coupled in series with a second resistive element between the input/output node and the ground potential; and wherein the second output buffer stage is enabled when resistive termination of the transmission line is required; and a differential amplifier having a positive input terminal, a negative input terminal, and an output terminal, wherein the positive input terminal is connected to the input/output node, and wherein the negative input terminal is connected to a reference potential, and wherein the differential amplifier is configured to produce an input signal at the output terminal; an input termination stage, comprising: a termination node; a third resistive element coupled between the input/output node and the termination node; a time delay unit coupled to receive the input signal produced by the differential amplifier and configured to produce a time-delayed input signal after a predetermined time delay has elapsed; wherein said time delay is substantially equal to the amount of time it takes the input signal to propagate the length of the transmission line; and wherein the termination node is selectively coupled to either the power supply potential or the ground potential dependent upon the time-delayed input signal produced by the time delay unit such that the input signal is reinforced following said time delay.
23. The I/O buffer as recited in claim 22, wherein the input termination unit further comprises: a third p-channel metal oxide semiconductor (MOS) transistor coupled between the termination node and the power supply potential; and a third n-channel MOS transistor coupled between the termination node and the ground potential.
24. The I/O buffer as recited in claim 22, wherein the sum of an intrinsic resistance of the second p-channel MOS transistor and the resistance of the first resistive element is substantially equal to a characteristic impedance of the transmission line.
25. The I/O buffer as recited in claim 22, wherein the sum of an intrinsic resistance of the second n-channel MOS transistor and the resistance of the second resistive element is substantially equal to a characteristic impedance of the transmission line.
26. The I/O buffer as recited in claim 22, wherein the electrical resistance of the third resistive element is substantially equal to a characteristic impedance of the transmission line.
27. The I/O buffer as recited in claim 22, wherein when the input signal transitions from a logic low level to a logic high level, the termination node is first coupled to the ground potential, and wherein after the predetermined delay time of the time delay unit has elapsed, the termination node is coupled to the power supply potential.
28. The I/O buffer as recited in claim 22, wherein when the input signal transitions from a logic high level to a logic low level, the termination node is first coupled to the power supply potential, and wherein after the predetermined delay time of the time delay unit has elapsed, the termination node is coupled to the ground potential.
29. An input/output (I/O) buffer circuit, comprising: an input/output node; a first output driver stage, comprising: a first p-channel metal oxide semiconductor (MOS) transistor coupled between the input/output node and a power supply potential; a first n-channel MOS transistor coupled between the input/output node and a ground potential; and wherein the first output driver stage is enabled when resistive termination of a transmission line connected to the input/output node is not required; a second output driver stage, comprising: a second p-channel MOS transistor coupled in series with a first resistive element between the input/output node and the power supply potential; a second n-channel MOS transistor coupled in series with a second resistive element between the input/output node and the ground potential; and wherein the second output buffer stage is enabled when resistive termination of the transmission line is required; and a differential amplifier having a positive input terminal, a negative input terminal, and an output terminal, wherein the positive input terminal is connected to the input/output node, and wherein the negative input terminal is connected to a reference potential, and wherein the differential amplifier is configured to produce an input signal at the output terminal; an input termination stage, comprising: a third p-channel metal oxide semiconductor (MOS) transistor coupled in series with a third resistive element between the input/output node and the power supply potential; a third n-channel MOS transistor coupled in series with a fourth resistive element between the input/output node and the ground potential; a time delay unit coupled to receive the input signal produced by the differential amplifier and configured to produce a time-delayed input signal after a predetermined time delay has elapsed; wherein said time delay is substantially equal to the amount of time it takes the input signal to propagate the length of the transmission line; and wherein the input/output node is selectively coupled to either the power supply potential or the ground potential dependent upon the time-delayed input signal produced by the time delay unit such that the input signal is reinforced following said time delay.
30. An input buffer circuit, comprising: an input node; a differential amplifier having a positive input terminal, a negative input terminal, and an output terminal, wherein the positive input terminal is connected to the input node, and wherein the negative input terminal is connected to a reference potential, and wherein the differential amplifier is configured to produce an input signal at the output terminal; and an input termination stage, comprising: a termination node; a resistive element coupled between the input node and the termination node; a time delay unit coupled to receive the input signal produced by the differential amplifier and configured to produce a time-delayed input signal after a predetermined time delay has elapsed; wherein said time delay is substantially equal to the amount of time it takes the input signal to propagate the length of the transmission line; and wherein the termination node is selectively coupled to either a power supply potential or a ground potential dependent upon the time-delayed input signal produced by the time delay unit such that the input signal is reinforced following said time delay.
31. An input buffer circuit, comprising: an input node; a differential amplifier having a positive input terminal, a negative input terminal, and an output terminal, wherein the positive input terminal is connected to the input node, and wherein the negative input terminal is connected to a reference potential, and wherein the differential amplifier is configured to produce an input signal at the output terminal; and an input termination stage, comprising: a p-channel metal oxide semiconductor (MOS) transistor coupled in series with a first resistive element between the input node and a power supply potential; an n-channel MOS transistor coupled in series with a second resistive element between the input node and a ground potential; a time delay unit coupled to receive the input signal produced by the differential amplifier and configured to produce a time-delayed input signal after a predetermined time delay has elapsed; wherein said time delay is substantially equal to the amount of time it takes the input signal to propagate the length of the transmission line; and wherein the input node is selectively coupled to either the power supply potential or the ground potential through the first or second resistive element dependent upon the time-delayed input signal produced by the time delay unit such that the input signal is reinforced following said time delay.
32. An input/output (I/O) buffer circuit, comprising: a first output driver stage and a second output driver stage operably coupled to an input/output node, wherein said first and second output drivers are coupled to receive a high frequency enable (HFE) signal, an output enable (OE) signal, and an output data (OD) signal; an input termination stage coupled to receive an input data (ID) signal and a termination enable (TE) signal; wherein the second output driver is configured to drive the input/output node with an electrical resistance substantially equal to a characteristic impedance of a transmission line connected to the input/output node; wherein when the HFE signal is deasserted and the OE signal is asserted, the second output driver is disabled and the first output driver stage drives the OD signal upon the input/output node; wherein when the HFE and OE signals are asserted, the first output driver is disabled and the second output driver stage drives the OD signal upon the input/output node; and wherein when the TE signal is asserted, the input termination stage: (i) terminates the transmission line in a resistance substantially equal to the characteristic impedance of the transmission for a predetermined period of time following a transition of the ID signal, and (ii) reinforces the ID signal following said predetermined period of time such that electrical power dissipation within the I/O buffer is reduced.
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While the invention is susceptible to various modifications and alternative
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Unknown
April 25, 2000
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