Magnetic random access memory with a reference memory array

1. A magnetic random access memory comprising: a first electrically conductive line; a magnetic memory cell coupled in series to the first electrically conductive line, the magnetic memory cell having a magnetic resistance that is switched between a minimum magnetic resistance and a maximum magnetic resistance according to directions of magnetization vectors stored in the magnetic memory cell; a second electrically conductive line; a reference magnetic memory cell coupled in series to the second electrically conductive line, the reference magnetic memory cell having a predetermined magnetic resistance; and a resistive element coupled in series to the reference magnetic memory cell, a total resistance across the reference magnetic memory cell and the resistive element being set between the minimum magnetic resistance and the maximum magnetic resistance.

2. The magnetic random access memory as claimed in claim 1 further including a comparator having a first input and a second input, the first input being coupled to the first electrically conductive line and the second input being coupled to the second electrically conductive line, for comparing the magnetic resistance to the total resistance to provide an output.

3. The magnetic random access memory as claimed in claim 2 wherein the comparator includes: a converter for converting a first current on the first electrically conductive line and a second current on the second electrically conductive line to a first voltage and a second voltage, respectively; and a voltage comparator for comparing the first voltage to the second voltage to provide the output.

4. The magnetic random access memory as claimed in claim 1 wherein the resistive element is a transistor, which allows the total resistance to be set between the minimum magnetic resistance and the maximum magnetic resistance.

5. The magnetic random access memory as claimed in claim 1 wherein the resistive element is set so as for the total resistance to be a mid-point resistance between the minimum magnetic resistance and the maximum magnetic resistance.

6. The magnetic random access memory as claimed in claim 1 further including a first switch coupled in series to the first electrically conductive line for enabling the magnetic memory cell to be active, and a second switch coupled in series to the second electrically conductive line for enabling the reference magnetic memory cell to be active.

7. The magnetic random access memory as claimed in claim 1 wherein the magnetic memory cell and the reference magnetic memory cell have magnetic layers separated by a non-magnetic layer.

8. A magnetic random access memory device comprising: a plurality of magnetic memory cells placed in rows and columns; a plurality of reference magnetic memory cells; a plurality of resistive elements, each resistive element being electrically coupled in series to a reference magnetic memory cell; a selector for selecting a target memory cell being one of the plurality of magnetic memory cells, and a reference memory cell being one of the plurality of reference magnetic memory cells; and a comparator for comparing a resistive value across the target memory cell to a total resistive value across the reference memory cell and a resistive element coupled to the reference memory cell to provide an output signal.

9. The magnetic random access memory device as claimed in claim 8 wherein the plurality of magnetic memory cells are placed on intersections of a plurality of bit lines and a plurality of digit lines.

10. The magnetic random access memory device as claimed in claim 8 wherein the comparator has a first input and a second input, the first and second inputs being electrically coupled to the target memory cell and the reference memory cell, respectively.

11. The magnetic random access memory device as claimed in claim 8 wherein each of the plurality of magnetic memory cells has a minimum resistive value and a maximum resistive value, and the total resistive value is set between the minimum resistive value and the maximum resistive value.

12. The magnetic random access memory device as claimed in claim 11 wherein the total resistive value is a mid-point resistive value between the minimum resistive value and the maximum resistive value.

13. The magnetic random access memory device as claimed in claim 12 wherein the resistive element is a transistor having a gate electrode, the total resistive value being set by a reference signal applied to the gate electrode.

14. The magnetic random access memory device as claimed in claim 8 wherein the magnetic memory cell and the reference magnetic memory cell have magnetic layers separated by a non-magnetic layer.

15. A magnetic random access memory device comprising: a memory array including: a plurality of bit lines, each bit line being electrically conductive; a plurality of digit lines, each digit line being electrically conductive and perpendicularly placed to the bit lines; and a plurality of magnetic memory cells, each magnetic memory cell being placed on each intersection of the plurality of bit lines and the plurality of digit lines, and being electrically coupled in series to the bit line; and a reference memory array including: a reference line being electrically conductive; a plurality of reference bit lines, each reference bit line being electrically conductive; a plurality of reference magnetic memory cells, each reference magnetic memory cell being electrically coupled in series to the each reference bit line; and a plurality of resistive elements, each resistive element being electrically coupled in series to a reference magnetic memory cell and being electrically coupled to the reference line.

16. The magnetic random access memory device as claimed in claim 15 wherein each of the plurality of magnetic memory cells has a minimum resistive value and a maximum resistive value, and a total resistive value across the reference magnetic memory cell and a resistive element is set between the minimum resistive value and the maximum resistive value.

17. The magnetic random access memory device as claimed in claim 16 wherein the total resistive value is a mid-point resistive value between the minimum resistive value and the maximum resistive value.

18. The magnetic random access memory device as claimed in claim 17 wherein the resistive element is a transistor having a gate electrode, the total resistive value being set by a reference signal applied to the gate electrode.

19. The magnetic random access memory device as claimed in claim 15 wherein the magnetic memory cell and the reference magnetic memory cell have magnetic layers separated by a non-magnetic layer.

20. A magnetic random access memory device comprising: a plurality of memory banks including: a couple of bit lines being coupled to a shared bit line and electrically conductive; a plurality of digit lines, each digit line being perpendicularly placed to the bit lines and electrically conductive; and a plurality of magnetic memory cells, one each magnetic memory cell being placed on each intersection of the couple of bit lines and the plurality of digit lines, and being electrically coupled to said shared bit line; and a reference memory array including: a reference line being electrically conductive; a plurality of reference bit lines, each reference bit line being electrically conductive; a plurality of reference magnetic memory cells, each reference magnetic memory cell being electrically coupled in series to the each reference bit line; and a plurality of resistive elements, each resistive element being electrically coupled in series to a reference magnetic memory cell and being electrically coupled to the reference line; and a comparator having a first input, and a second input, the first input being coupled to shared bit lines in the plurality of memory banks and the second input being coupled to the plurality of reference bit lines.

21. The magnetic random access memory device as claimed in claim 20 wherein each of the plurality of magnetic memory cells has a minimum resistive value and a maximum resistive value, and a total resistive value is set between the minimum resistive value and the maximum resistive value.

22. The magnetic random access memory device as claimed in claim 21 wherein the total resistive value is a mid-point resistive value between the minimum resistive value and the maximum resistive value.

23. The magnetic random access memory device as claimed in claim 22 wherein the resistive element is a transistor having a gate electrode, the total resistive value being set by a reference signal applied to the gate electrode.

24. The magnetic random access memory device as claimed in claim 20 wherein the magnetic memory cell and the reference magnetic memory cell have magnetic layers separated by a non-magnetic layer.