Ultra high density inverter using a stacked transistor arrangement

1. An integrated circuit comprising: a first transistor having a first source implant, a first drain implant and a first gate conductor arranged upon a first topography; a first interlevel dielectric extending over said first topography, said first interlevel dielectric having an opening which exposes the first gate conductor; a second transistor having a second source implant, a second drain implant and a second gate conductor which extends over said first interlevel dielectric, wherein said second gate conductor extends below said second source and drain implants and into said opening in electrical abutment with said first gate conductor; an output conductor abutting an outermost lateral edge of said second drain implant and extending from said outermost lateral edge to an upper surface of said first drain implant; a power conductor spaced substantially parallel to said output conductor and abutting an upper surface of said second source implant; and a ground conductor spaced substantially parallel to said output conductor and said power conductor and abutting an upper surface of said first source implant .

2. The integrated circuit as recited in claim 1, wherein said integrated circuit comprises an inverter.

3. The integrated circuit as recited in claim 2, wherein said output conductor, said power conductor and said ground conductor are connected between said first and second transistors to form an inverter.

4. The integrated circuit as recited in claim 2, wherein said output conductor, said power conductor and said ground conductor each extend along an axis perpendicular to said first topography.

5. The integrated circuit as recited in claim 1, wherein said second transistor is inverted relative to said first transistor.

6. The integrated circuit as recited in claim 1, further comprising a silicide interposed between said first gate conductor and said second gate conductor.

7. The integrated circuit as recited in claim 1, wherein said second drain and source implants are doped with an impurity opposite said first drain and source implants.

8. The integrated circuit as recited in claim 1, wherein said second gate conductor completely fills said opening, such that an entire upper surface of the second gate conductor is substantially even with an upper surface of said first interlevel dielectric.

9. An inverter circuit, comprising: a first transistor having a first gate conductor, a first source implant and a first drain implant, wherein said first gate conductor extends along a plane above said first source and drain implants; a second transistor having a second gate conductor, a second source implant and a second drain implant, wherein said second gate conductor extends along a plane below said second source and drain implants, and wherein said second gate conductor abuts with said first gate conductor; an output conductor abutting an outermost lateral edge of said second drain implant and extending from said outermost lateral edge to an upper surface of said first drain implant; a power conductor spaced substantially parallel to said output conductor and abutting an upper surface of said second source implant; and a ground conductor spaced substantially parallel to said output conductor and said power conductor and abutting an upper surface of said first source implant.

10. The inverter as recited in claim 9, further comprising a silicide interposed between said first gate conductor and said second gate conductor.

11. The inverter as recited in claim 9, wherein said second drain and source implants are doped with an impurity opposite said first drain and source implants.