Delay control circuit using dynamic latches

1. A delay control circuit comprising: a clock terminal for receiving a clock signal; a write enable terminal for receiving a write enable signal; at least one dynamic latch providing a latched signal in response to a latch enable signal; and a control circuit coupled to the at least one dynamic latch and the write enable terminal, the control circuit being formed to assert the latch enable signal in response to a transition of the clock signal, and de-assert the latch enable signal at a defined time after the transition of the clock signal.

2. The delay control circuit of claim 1 wherein the control circuit asserts the latch enable signal when the write enable signal is in a first state and not when the write enable signal is in a second state.

3. The delay control circuit of claim 1 wherein the control circuit comprises: a logic gate for providing the latch enable signal in response to assertion of both the clock signal and a force signal; a storage circuit for asserting a latched write signal in response to assertion of the write enable signal and de-assertion of the clock signal; and a delay circuit for asserting the force signal in response to assertion of the latched write signal and de-asserting the force signal after the defined time.

4. A delay control circuit comprising: a clock terminal for receiving a clock signal; a write enable terminal for receiving a write enable signal; at least one dynamic latch providing a latched signal in response to a latch enable signal; and a control circuit coupled to the at least one dynamic latch, the control circuit being formed to assert a latched write signal and the latch enable signal in response to the clock signal and the write enable signal, the control circuit asserting the latch enable signal in response to a transition of the clock signal and de-asserting the latch enable signal at a defined time after the latched write signal is asserted.

5. The delay control circuit of claim 4 wherein the at least one dynamic latch comprises an address latch and the latched signal is an address signal.

6. The delay control circuit of claim 4 wherein the at least one dynamic latch comprises a data latch and the latched signal is a data signal.

7. The delay control circuit of claim 4 wherein the control circuit comprises: a storage circuit coupled to receive the clock signal and the write enable signal, the storage circuit asserting the latched write signal in response to the clock signal and the write enable signal; a first delay circuit coupled to receive the latched write signal, the first delay circuit being configured to generate a reset signal which is a delayed version of the latched write signal, the latched write signal being de-asserted in response to the reset signal; a second delay circuit coupled to receive the clock signal, the second delay circuit being configured to generate a delayed clock signal which is a delayed version of the clock signal; a first logic gate coupled to receive the delayed clock signal, the reset signal and the latched write signal, wherein the first logic gate generates a forcing signal in response to the delayed clock signal, the reset signal and the latched write signal; and a second logic gate coupled to receive the forcing signal and the clock signal, wherein the second logic gate generates the latch enable signal in response to the clock signal and the forcing signal.

8. The delay control circuit of claim 7, wherein the latch enable signal causes the dynamic latch to enter a transparent state in response to a transition in the forcing signal.

9. The delay control circuit of claim 4, wherein the control circuit is formed to assert the latched write signal when the write enable signal is asserted and the clock signal undergoes a transition.

10. The delay control circuit of claim 4, wherein the control circuit comprises: a storage circuit coupled to receive the clock signal and the write enable signal, the storage circuit asserting an intermediate write enable signal and the latched write signal in response to the clock signal and the write enable signal; a first delay circuit coupled to receive the write strobe pulse, the first delay circuit being formed to generate a reset signal which is a delayed version of the latched write signal, the intermediate write enable signal and the latched write signal being de-asserted in response to the reset signal; a second delay circuit coupled to receive the intermediate write enable signal, the second delay circuit being formed to generate a forcing signal which is a delayed version of the intermediate write enable signal; and a logic gate coupled to receive the clock signal and the forcing signal, wherein the logic gate generates the latch enable signal in response to the clock signal and the forcing signal.

11. The delay control circuit of claim 4, wherein the control circuit comprises: a storage circuit coupled to receive the clock signal and the write enable signal, the storage circuit asserting the latched write signal in response to the clock signal and the write enable signal; and a first delay circuit coupled to receive the latched write signal, the first delay circuit being configured to generate a reset signal which is a delayed version of the latched write signal, the latched write signal being de-asserted in response to the reset signal.

12. The delay control circuit of claim 11, wherein the storage circuit comprises a flip-flop with a RESET input terminal.

13. The delay control circuit of claim 12, wherein the first delay circuit is coupled to the flip flop such that the reset signal is applied to the RESET input terminal.

14. The delay control circuit of claim 13, wherein the first delay circuit comprises a logic gate receiving as input signals a delayed latched write signal and a disabling signal, the logic gate applying the delayed latched write signal to the RESET input terminal when the disabling signal is not active.

15. The delay control circuit of claim 11, wherein the storage circuit is configured to generate an intermediate signal in response to the reset signal, the control circuit further comprising a second delay circuit configured to generate a forcing signal in response to the intermediate signal, wherein the second delay circuit provides a defined delay to the intermediate signal to create the forcing signal, and wherein the latch enable signal is de-asserted in response to the forcing signal.