Pipelined, high-precision fast fourier transform processor

1. Fast fourier transform processor comprising a plurality of pipelined, functionally identical stages, each stage including only a single memory component and including means for providing coefficient and programmable memory address generation support functions necessary to perform a portion of a fast fourier transform operation on a block of data, the output of the processor being the fast fourier transform of the data block.

2. The processor of claim 1 wherein each stage includes a computational butterfly.

3. The processor of claim 2 wherein the computational butterfly is fully programmable.

4. The processor of claim 2 wherein the computational butterfly employs iterative multiplication.

5. The processor of claim 1 wherein the support function includes coefficient generation by recursive multiplication of the consecutive powers of a complex seed value.

6. The processor of claim 1 including log.sub.6 N stages where r is the radix order and N is the number of samples.

7. The processor of claim 1 wherein each stage includes a buffer memory interface.

8. The processor of claim 7 wherein the buffer memory interface is an interface to static random access memory.