Legal claims defining the scope of protection, as filed with the USPTO.
1. An apparatus including a circuit for adaptively equalizing an input data signal by removing duty cycle distortion jitter therefrom, comprising: an equalization circuit configured to receive an equalization control signal and in accordance therewith receive and equalize an input data signal and in accordance therewith provide an equalized data signal which includes pluralities of rising and falling edges with associated rise and fall times, respectively, wherein said rise and fall times are substantially equal; a signal analysis circuit, coupled to said equalization circuit, configured to receive and analyze said equalized data signal and in accordance therewith provide a plurality of analysis result signals, wherein each one of said analysis result signals represents one of a plurality of characteristics of said equalized data signal; and a control circuit, coupled to said signal analysis circuit and said equalization circuit, configured to receive and process said plurality of analysis result signals and in accordance therewith provide said equalization control signal.
2. The apparatus of claim 1, wherein: said equalization circuit comprises a current controlled inverter circuit; and said equalization control signal comprises a current signal.
3. The apparatus of claim 2, wherein said current controlled inverter circuit comprises: a first current mirror circuit configured to receive an input current and in accordance therewith provide a first mirror current; a second current mirror circuit configured to receive said current signal and in accordance therewith provide a second mirror current; and an inverter circuit, coupled between said first and second current mirror circuits, configured to receive said first and second mirror currents and said input data signal and in accordance therewith provide said equalized data signal.
4. The apparatus of claim 1, wherein said equalization control signal comprises a first current signal, and a second current signal inversely proportional to said first current signal, and wherein said equalization circuit comprises: a first current mirror circuit configured to receive said first current signal and in accordance therewith generate a first output; a second current mirror circuit configured to receive said second current mirror signal and in accordance therewith generate a second output; a first voltage generator circuit configured to receive said first output and in accordance therewith generate a first voltage; a second voltage generator circuit configured to receive said second output and in accordance therewith generate a second voltage; a delay circuit configured to receive said first voltage and said second voltage, and in accordance therewith provide said equalized data signal.
5. The apparatus of claim 1, wherein said signal analysis circuit comprises a signal timing extraction circuit configured to extract timing information from said equalized data signal and in accordance therewith provide a plurality of timing signals as said plurality of analysis result signals, wherein each one of said plurality of timing signals represents one of a plurality of timing characteristics of said equalized data signal.
6. The apparatus of claim 5, wherein said signal timing extraction circuit comprises: a first phase-lock loop circuit configured to phase-lock to said equalized data signal rising edges and in accordance therewith provide a first recovered clock signal as a first one of said plurality of timing signals; and a second phase-lock loop circuit configured to phase-lock to said equalized data signal falling edges and in accordance therewith provide a second recovered clock signal as a second one of said plurality of timing signals.
7. The apparatus of claim 5, wherein said signal timing extraction circuit comprises: a phase-lock loop circuit configured to phase-lock to said equalized data signal and in accordance therewith to generate a recovered clock signal; a first phase detector circuit configured to receive said recovered clock signal and in accordance therewith selectively generate a first signal indicative of a leading error in rising edges of said recovered clock signal and a second signal indicative of a lagging error in said rising edges; and a second phase detector circuit configured to receive said recovered clock signal and in accordance therewith selectively generate a third signal indicative of a leading error in falling edges of said recovered clock signal and a fourth signal indicative of a lagging error in said falling edges.
8. The apparatus of claim 6, wherein: said first phase-lock loop circuit is further configured to provide a first phase-lock indication signal which indicates when said first recovered clock signal is phase-locked to said equalized data signal rising edges; said second phase-lock loop circuit is further configured to provide a second phase-lock indication signal which indicates when said second recovered clock signal is phase-locked to said equalized data signal falling edges; and said control circuit is further configured to receive said first and second phase-lock indication signals and in accordance therewith provide said equalization control signal.
9. The apparatus of claim 5, wherein said signal timing extraction circuit comprises: a differential signal converter configured to receive and convert said equalized data signal to a differential data signal; a single-ended signal converter, coupled to said differential signal converter, configured to receive and convert said differential data signal to a single-ended data signal which includes pluralities of rising and falling edges corresponding to said equalized data signal rising and falling edges; a first phase-lock loop circuit configured to phase-lock to said single-ended data signal rising edges and in accordance therewith provide a first recovered clock signal as a first one of said plurality of timing signals; and a second phase-lock loop circuit configured to phase-lock to said single-ended data signal falling edges and in accordance therewith provide a second recovered clock signal as a second one of said plurality of timing signals.
10. The apparatus of claim 9, wherein: said first phase-lock loop circuit is further configured to provide a first phase-lock indication signal which indicates when said first recovered clock signal is phase-locked to said equalized data signal rising edges; said second phase-lock loop circuit is further configured to provide a second phase-lock indication signal which indicates when said second recovered clock signal is phase-locked to said equalized data signal falling edges; and said control circuit is further configured to receive said first and second phase-lock indication signals and in accordance therewith provide said is equalization control signal.
11. The apparatus of claim 1, wherein said control circuit comprises: a signal comparison circuit configured to receive and compare said plurality of analysis result signals and in accordance therewith provide a comparison result signal; and a processing circuit, coupled to said signal comparison circuit, configured to receive and process said comparison result signal and in accordance therewith provide said equalization control signal.
12. The apparatus of claim 11, wherein said signal comparison circuit comprises a phase comparator circuit.
13. The apparatus of claim 11, wherein said processing circuit comprises: a digital filter circuit configured to filter said comparison result signal and in accordance therewith provide a filtered signal; and a digital-to-analog converter circuit, coupled to said digital filter circuit, configured to receive and convert said filtered signal to an analog signal.
14. The apparatus of claim 11, wherein said signal comparison circuit comprises: a plurality of counter circuits each configured to receive one of said plurality of analysis result signals and in accordance therewith store a cumulative quantity of the one signal and in accordance therewith output a cumulative quantity signal; and a comparator circuit configured to receive a said cumulative signal from each of said plurality of counter circuits and in accordance therewith provide said comparison result signal.
15. The apparatus of claim 11, wherein said processing circuit comprises: a counter configured to receive said comparison result signal and in accordance therewith generate a control signal; a first digital-to-analog converter circuit configured to receive said control signal and in accordance therewith generate a first output signal proportional to said control signal; and a second digital-to-analog converter circuit configured to receive said control signal and in accordance therewith generate a second output signal inversely proportional to said control signal.
16. An apparatus including a circuit for adaptively equalizing an input data signal by removing duty cycle distortion jitter therefrom, comprising: a plurality of equalization circuits, each configured to receive a select signal and an equalization control signal and in accordance therewith receive and equalize an input data signal and in accordance therewith provide an equalized data signal which includes pluralities of rising an falling edges with associated rise and fall times, respectively, wherein said rise and fall times are substantially equal; a multiplexor circuit configured to receive a plurality of equalized data signals and in accordance therewith output one of said plurality of equalized data signals based on said select signal; a signal analysis circuit, coupled to said multiplexor circuit, configured to receive and analyze said one of said plurality and in accordance therewith provide a plurality of analysis result signals, wherein each one of said analysis result signals represents one of a plurality of characteristics of said equalized data signal; and a control circuit, coupled to said signal analysis circuit, said multiplexor circuit, and said plurality of equalization circuits, configured to receive and process said plurality of analysis result signals and in accordance therewith provide said equalization control signal, and configured to output said select signal.
17. The apparatus of claim 16, wherein said signal analysis circuit comprises a signal timing extraction circuit configured to extract timing information from said equalized data signal and in accordance therewith provide a plurality of timing signals as said plurality of analysis result signals, wherein each one of said plurality of timing signals represents one of a plurality of timing characteristics of said equalized data signal.
18. The apparatus of claim 17, wherein said signal timing extraction circuit comprises: a first phase-lock loop circuit configured to phase-lock to said equalized data signal rising edges and in accordance therewith provide a first recovered clock signal as a first one of said plurality of timing signals; and a second phase-lock loop circuit configured to phase-lock to said equalized data signal falling edges and in accordance therewith provide a second recovered clock signal as a second one of said plurality of timing signals.
19. The apparatus of claim 18, wherein: said first phase-lock loop circuit is further configured to provide a first phase-lock indication signal which indicates when said first recovered clock signal is phase-locked to said equalized data signal rising edges; said second phase-lock loop circuit is further configured to provide a second phase-lock indication signal which indicates when said second recovered clock signal is phase-locked to said equalized data signal falling edges; and said control circuit is further configured to receive said first and second phase-lock indication signals and in accordance therewith provide said equalization control signal.
20. The apparatus of claim 16, wherein each one of said plurality of equalization circuits comprises: a current controlled inverter circuit; a current digital-to-analog converter circuit, coupled to said current controlled inverter circuit, configured to receive a stored equalization control signal and in accordance therewith output a current equalization control signal to said converter controlled inverter circuit; and a memory circuit, coupled to said current digital-to-analog converter circuit, configured to receive said select signal and configured to receive and store said equalization control signal and in accordance therewith output said stored equalization control signal.
21. The apparatus of claim 20, wherein said current controlled inverter circuit comprises: a first current mirror circuit configured to receive an input current and in accordance therewith provide a first mirror current; a second current mirror circuit configured to receive said current equalization control signal and in accordance therewith provide a second mirror current; and an inverter circuit, coupled between said first and second current mirror circuits, configured to receive said first and second mirror currents and said input data signal and in accordance therewith provide said equalized data signal.
22. The apparatus of claim 17, wherein each one of said plurality of equalization circuits further comprises: a differential signal converter configured to receive and convert said equalized data signal to a differential data signal; and a single-ended signal converter, coupled to said differential signal converter, configured to receive and convert said differential data signal to a single-ended data signal which includes pluralities of rising and falling edges corresponding to said equalized data signal rising and falling edges.
23. The apparatus of claim 22, wherein: said first phase-lock loop circuit is further configured to provide a first phase-lock indication signal which indicates when said first recovered clock signal is phase-locked to said equalized data signal rising edges; said second phase-lock loop circuit is further configured to provide a second phase-lock indication signal which indicates when said second recovered clock signal is phase-locked to said equalized data signal falling edges; and said control circuit is further configured to receive said first and second phase-lock indication signals and in accordance therewith provide said equalization control signal.
24. The apparatus of claim 16, wherein said control circuit comprises: a selector circuit, coupled to said multiplexor circuit and said plurality of equalization circuits, configured to generate said select signal; a signal comparison circuit configured to receive and compare said analysis result signals and in accordance therewith provide a comparison result signal; and a processing circuit, coupled to said signal comparison circuit, configured to receive and process said comparison result signal and in accordance therewith provide said equalization control signal.
25. The apparatus of claim 24, wherein said signal comparison circuit comprises a phase comparator circuit.
26. The apparatus of claim 24, wherein said processing circuit comprises a digital filter circuit.
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Unknown
July 11, 2000
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