Execute unit configured to selectably interpret an operand as multiple operands or as a single operand

1. A method of operating a first integer operation circuit and a second integer operation circuit, comprising: performing an integer operation upon a first operand and a second operand in said first integer operation circuit, thereby producing a first result; performing said integer operation upon a third operand and a fourth operand in said second integer operation circuit, thereby producing a second result; and modifying said second result using a circuit if a control signal from a control unit is deasserted, such that said first result and said second result comprise a third result indicative of performing said integer operation upon a fifth operand comprising said first and third operands and a sixth operand comprising said second and fourth operands, and wherein said first result and said second result are independent if said control signal is asserted; said control unit receiving an instruction corresponding to said first operand, said second operand, said third operand, and said fourth operand, and selectively asserting or deasserting said control signal in response to said instruction.

2. The method as recited in claim 1 wherein said integer operation is addition.

3. The method as recited in claim 1 wherein said integer operation is multiplication.

4. The method as recited in claim 3 further comprising performing a multiplication of said first operand and said fourth operand, thereby producing a fourth result; performing a multiplication of said second operand and said third operand, thereby producing a fifth result; and combining said first, second, fourth and fifth results to produce a sixth result indicative of performing said integer operation on said fifth and sixth operands.

5. The method as recited in claim 1 further comprising performing at least one additional integer operation in at least one additional integer operation circuit, each additional integer operation being performed upon two additional operands, thereby producing an additional result; modifying said additional result using said circuit if an additional control signal from said control unit is deasserted, such that said additional result and said third result comprise a fourth result indicative of performing said integer operation upon a seventh operand comprising said first and third operands and one of said additional operands and an eighth operand comprising said second and fourth operands and another of said additional operands, and wherein said additional result is independent of said first result and said second result if said additional control signal is asserted.

6. An execute unit comprising: a first circuit configured to perform an integer operation upon a first operand and a second operand, thereby producing a result; and a control unit coupled to said first circuit, wherein said control unit is coupled to receive an instruction corresponding to said first operand and said second operand, and wherein said control unit is configured to assert a control signal if said instruction indicates that a first portion of said result is computed independent of a second portion of said result, and wherein said first portion of said result comprises said integer operation applied to a first portion of said first operand and a first portion of said second operand, and wherein said second portion of said result comprises said integer operation applied to a second portion of said first operand and a second portion of said second operand, and wherein said control unit is configured to deassert said control signal if said instruction indicates that said result comprises said integer operation applied to said first operand and said second operand; wherein said first circuit comprises: a first integer operation circuit configured to perform said integer operation upon said first portion of said first operand and said first portion of said second operand, thereby producing said first portion of said result; a second integer operation circuit configured to perform said integer operation upon said second portion of said first operand and said second portion of said second operand, thereby producing said second portion of said result; and a second circuit configured to modify said second portion of said result upon deassertion of said control signal to produce said result comprising said integer operation applied to said first operand and said second operand.

7. The execute unit as recited in claim 1 wherein said first circuit further comprises a third integer operation circuit and a fourth integer operation circuit; wherein said third integer operation circuit is configured to perform said integer operation upon a third portion of said first operand and a third portion of said second operand, thereby producing a third portion of said result; and wherein said fourth integer operation circuit is configured to perform said integer operation upon a fourth portion of said first operand and a fourth portion of said second operand, thereby producing a fourth portion of said result.

8. The execute unit as recited in claim 6 wherein said first circuit further comprises at least one additional integer operation circuit; and wherein said at least one additional integer operation circuit is configured to perform said integer operation upon at least one additional portion of said first operand and at least one additional portion of said second operand, thereby producing at least one additional portion of said result; and wherein one of said first, second and additional portions of said results has a size dissimilar to a size of another of said first, second and additional portions of said results.

9. The execute unit as recited in claim 7 wherein said control unit is configured to assert an additional control signal to said first circuit, wherein said additional control signal is indicative, when asserted, that said first portion of said result and said second portion of said result are combined to produce a second result and said third portion of said result and said fourth portion of said result are combined to produce a third result.

10. The execute unit as recited in claim 7; wherein said control unit is configured to assert a second control signal to said first circuit, wherein said second control signal is indicative, when asserted, that said first portion of said result and said second portion of said result are combined to produce a second result; and wherein said control unit is configured to assert a third control signal to said first circuit, wherein said third control signal is indicative, when asserted, that said third portion of said result and said fourth portion of said result are combined to produce a third result; and wherein said second control signal and said third control signal can be asserted independent of each other and independent of said control signal.

11. The execute unit as recited in claim 9 further comprising a third circuit coupled to receive said additional control signal, wherein said third integer operation circuit is configured to receive a third carry operand representing a carry into said addition, and wherein said third circuit is configured to supply said third carry operand.

12. The execute unit as recited in claim 11 wherein said third circuit is configured to supply a zero if said additional control signal is asserted.

13. The execute unit as recited in claim 11 wherein said second integer operation circuit is configured to supply a fourth carry operand indicative of a carry out of said addition.

14. The execute unit as recited in claim 13 wherein said third circuit is configured to supply said fourth carry operand as said third carry operand if said additional control signal is deasserted.

15. An execute unit comprising: a first circuit configured to perform an integer operation upon a first operand and a second operand, thereby producing a result; and a control unit coupled to said first circuit, wherein said control unit is coupled to receive an instruction corresponding to said first operand and said second operand, and wherein said control unit is configured to assert a control signal if said instruction indicates that a first portion of said result is computed independent of a second portion of said result, and wherein said first portion of said result comprises said integer operation applied to a first portion of said first operand and a first portion of said second operand, and wherein said second portion of said result comprises said integer operation applied to a second portion of said first operand and a second portion of said second operand, and wherein said control unit is configured to deassert said control signal if said instruction indicates that said result comprises said integer operation applied to said first operand and said second operand; wherein said first circuit comprises: a first integer operation circuit configured to perform said integer operation upon said first portion of said first operand and said first portion of said second operand, thereby producing said first portion of said result; a second integer operation circuit configured to perform said integer operation upon said second portion of said first operand and said second portion of said second operand, thereby producing said second portion of said result; and a second circuit configured to modify said second portion of said result upon deassertion of said control signal to produce said result comprising said integer operation applied to said first operand and said second operand wherein said integer operation is multiplication.

16. The execute unit as recited in claim 15 wherein said second circuit is an adder circuit configured to receive said second portion of said result from said second integer operation circuit.

17. The execute unit as recited in claim 16 further comprising a third integer operation circuit configured to produce a second result comprising a multiplication of said first portion of said first operand and said second portion of said second operation.

18. The execute unit as recited in claim 17 further comprising a third circuit coupled to said third integer operation circuit and said second circuit, said third circuit configured to select between said second result and a zero result, thereby producing a selected result, wherein said third circuit provides said selected result to said second circuit.

19. The execute unit as recited in claim 17 wherein said second circuit is configured to add said selected result to said second portion of said result, whereby said second portion of said result is provided if said zero result comprises said selected result.

20. A method for performing reconfigurable additions, the method comprising: performing a first integer operation upon a first portion of a first operand and a first portion of a second operand in a first integer operation circuit, thereby producing a first result; performing a second integer operation upon a second portion of said first operand and a second portion of said second operand in a second integer operation circuit, thereby producing a second result; selectively propagating a portion of said first result from said first integer operation circuit to said second integer operation circuit in response to a deassertion of a first control signal by a control unit, wherein said selectively propagating includes propagating a zero value to said second integer operation circuit in response to an assertion of said control signal; said control unit receiving an instruction, said instruction corresponding to said first and second operands, and responsively controlling the assertion or deassertion of said control signal, wherein said assertion of said control signal induces independent integer operations of corresponding portions of said first operand and said second operand, wherein deassertion of said control signal induces a composite integer operand on said first operand and said second operand.

21. The method of claim 20, wherein said first integer operation circuit and said second integer operation unit comprise adders, wherein said portion of said first result is a carry out signal from said first integer operation circuit.

22. The method of claim 21 comprising: performing a plurality of integer operations in a corresponding plurality of integer operation circuits, wherein each of the integer operation circuits operates on corresponding portions of said first operand and said second operand; selectively propagating to each integer operation circuit a zero value of a carry out value from the previous integer operation circuit in response to a corresponding control signal; said control unit controlling the assertion and deassertion of said control signals in response to said instruction; said integer operation circuits generating a plurality of results.

23. A method for performing reconfigurable multiplications, the method comprising: performing a first multiplication of a first portion of a first operand and a first portion of a second operand in a first multiply circuit, thereby generating a first low order result; performing a second multiplication of a second portion of said first operand and a second portion of said second operand in a second multiply circuit, thereby generating a first high order result; computing a second low order result and a second high order result using said first operand and said second operand; generating an intermediate low order value by selectively adding said first low order result to (a) said second low order result or (b) a zero value, in response to the value of a first control signal; generating an intermediate high order value by selectively adding said first high order result to (a) said second high order result or (b) a zero value, in response to the value of a second control signal; said control unit receiving an instruction corresponding to said first and second operands and responsively controlling the values of said control signals, wherein assertion of said first control signal and said second control signal induces an independent multiplication of corresponding portions of said first operand and said second operand.

24. The method of claim 23, wherein said computing a second low order result includes performing a third multiplication of said first portion of said first operand and said second portion of said second operand in a third multiply circuit, and said computing of said second high order result comprises performing a fourth multiplication of said second portion of said first operand and said first portion of said second operand.

25. The method of claim 24 further comprising adding said intermediate low order value and said intermediate high order value to generate an output value, wherein said output value comprises independent results of multiplying separate portions of said first operand and said second operand when said first control signal and said second control signal are asserted by said control unit.