Signal-transfer system and semiconductor device for high-speed data transfer

1. A signal-transfer system for transferring a signal via a line having no anti-signal-reflection resistor, said signal-transfer system comprising: a line having an equalized characteristic impedance Z.sub.0 ; and an output circuit having an output turn-on resistance Z.sub.0 /2 and outputting to said line a signal which has a voltage difference between a high level and a low level smaller than about 1 V, said output circuit including two driver transistors which are connected in series and receive inputs at gates thereof, a joint point between said two driver transistors connected to said line, said two driver transistors having the same turn-on resistance, one of said two driver transistors being turned on to output said signal to said line, and said inputs to the gates of said driver transistors being constant while said driver transistors are being either turned on or turned off.

2. The signal-transfer system as claimed in claim 1, wherein said output circuit receives as power voltages a first voltage and a second voltage lower than said first voltage, said first voltage and said second voltage having a voltage difference smaller than about 1 V.

3. The signal-transfer system as claimed in claim 2, wherein said high level is said first voltage and said low level is said second voltage.

4. The signal-transfer system as claimed in claim 1, wherein said line comprises a tri-state bus, and said output circuit has an infinite output impedance when outputting no signal.

5. The signal-transfer system as claimed in claim 1, wherein said line comprises a loop.

6. The signal-transfer system as claimed in claim 1, wherein each of said two driver transistors has the turn-on resistance thereof substantially equal to Z.sub.0 /2.

7. The signal-transfer system as claimed in claim 1, wherein said output circuit further comprises an inserted resistance inserted between said joint point and said line, a sum of said turn-on resistance of any one of said two driver transistors and said inserted resistance being substantially equal to Z.sub.0 /2.

8. The signal-transfer system as claimed in claim 1, wherein said output circuit is positioned around a midpoint of said line.

9. The signal-transfer system as claimed in claim 1, further comprising a driver circuit for supplying at least one control voltage to gates of said driver transistors, wherein said driver circuit controls said turn-on resistance by adjusting said at least one control voltage.

10. The signal-transfer system as claimed in claim 1, wherein said output circuit further comprises a plurality of additional driver transistors connected in parallel to said two driver transistors, said turn-on resistance being formed by connecting said two driver transistors and said additional driver transistors together in parallel.

11. The signal-transfer system as claimed in claim 10, further comprising a driver circuit supplying inputs to gates of said driver transistors, wherein said driver circuit adjusts a number of transistors to be driven among said driver transistors so as to control said turn-on resistance.

12. The signal-transfer system as claimed in claim 2, further comprising an internal circuit outputting said signal to said line via said output circuit, wherein said internal circuit receives as power voltages a third voltage higher than said first voltage and a fourth voltage lower than said second voltage.

13. The signal-transfer system as claimed in claim 12, wherein a voltage difference between said first voltage and said second voltage is smaller than about one third of a voltage difference between said third voltage and said fourth voltage.

14. The signal-transfer system as claimed in claim 8, further comprising a plurality of receiver circuits connected to said line and receiving said signal, wherein said receiver circuits are arranged at substantially symmetric positions along said line with respect to a center of symmetry at which said output circuit is connected to said line.

15. The signal-transfer system-as claimed in claim 14, wherein said line is folded in two, and said output circuit is connected to said line at a fold point of said line.

16. The signal-transfer system as claimed in claim 14, wherein said output circuit and said receiver circuits are arranged at substantially equal intervals along said line.

17. The signal-transfer system as claimed in claim 5, further comprising a plurality of receiver circuits connected to said line and receiving said signal, wherein said output circuit and said receiver circuits are arranged at substantially equal intervals along said line.

18. A signal-transfer system for transferring a signal via a line having no anti-signal-reflection resistor, said signal-transfer system comprising: a line having an equalized characteristic impedance Z.sub.0 ; an output circuit having an output turn-on resistance Z.sub.0 /2 and outputting to said line a signal which has one of a first voltage and a second voltage lower than said first voltage, said output circuit including two driver transistors which are connected in series and receive inputs at gates thereof, a joint point between said two driver transistors connected to said line, said two driver transistors having the same turn-on resistance, and one of said two driver transistors being turned on to output said signal to said line; and an internal circuit outputting said signal to said line via said output circuit, said internal circuit being provided with a third voltage higher than said first voltage and a fourth voltage lower than said second voltage as power voltages, wherein said inputs to the gates of said driver transistors are constant while said driver transistors are being either turned on or turned off.

19. A semiconductor device for outputting a signal to a line which has an equalized characteristic impedance Z.sub.0 and no anti-signal-reflection resistor, said semiconductor device comprising: an output circuit having an output turn-on resistance Z.sub.0 /2 and outputting to said line a signal which has one of a first voltage and a second voltage lower than said first voltage, said output circuit including two driver transistors which are connected in series and receive inputs at gates thereof, a joint point between said two driver transistors connected to said line, said two driver transistors having the same turn-on resistance, and one of said two driver transistors being turned on to output said signal to said line; and an internal circuit outputting said signal to said line via said output circuit, said internal circuit being provided with a third voltage higher than said first voltage and a fourth voltage lower than said second voltage as power voltages, wherein said inputs to the gates of said driver transistors are constant while said driver transistors are being either turned on or turned off.

20. A semiconductor device for outputting a signal to a line which has an equalized characteristic impedance Z.sub.0 and no anti-signal-reflection resistor, said semiconductor device comprising: an output circuit having an output impedance Z.sub.0 /2 and outputting to said line a signal which has a voltage difference between a high level and a low level smaller than about 1 V, said output circuit including two driver transistors which are connected in series and receive inputs at gates thereof, a joint point between said two driver transistors connected to said line, said two driver transistors having the same turn-on resistance, and one of said two driver transistors being turned on to output said signal to said line; and an internal circuit using said output circuit to output said signal wherein said inputs to the gates of said driver transistors are constant while said driver transistors are being either turned on or turned off.

21. The semiconductor device as claimed in claim 20, wherein said output circuit receives as power voltages a first voltage and a second voltage lower than said first voltage, said first voltage and said second voltage having a voltage difference smaller than about 1 V.

22. The semiconductor device as claimed in claim 21, wherein said high level is said first voltage and said low level is said second voltage.

23. The semiconductor device as claimed in claim 20, wherein said output circuit has an infinite output impedance when outputting no signal.

24. The semiconductor device as claimed in claim 20, further comprising a driver circuit for supplying at least one control voltage to gates of said driver transistors, wherein said driver circuit controls said turn-on resistance by adjusting said at least one control voltage.

25. The semiconductor device as claimed in claim 20, wherein each of said two driver transistors has the turn-on resistance thereof substantially equal to Z.sub.0 /2.

26. The semiconductor device as claimed in claim 20, wherein said output circuit further comprises an inserted resistance inserted between said joint point and said line, a sum of said turn-on resistance of any one of said two driver transistors and said inserted resistance being substantially equal to Z.sub.0 /2.

27. The semiconductor device as claimed in claim 20, wherein said output circuit further comprises a plurality of additional driver transistors connected in parallel to said two driver transistors, said turn-on resistance being formed by connecting said two driver transistors and said additional driver transistors together in parallel.

28. The semiconductor device as claimed in claim 27, further comprising a driver circuit supplying inputs to gates of said driver transistors, wherein said driver circuit adjusts a number of transistors to be driven among said driver transistors so as to control said turn-on resistance.

29. The semiconductor device as claimed in claim 21, wherein said internal circuit receives as power voltages a third voltage higher than said first voltage and a fourth voltage lower than said second voltage.

30. The semiconductor device as claimed in claim 29, wherein a voltage difference between said first voltage and said second voltage is smaller than about one third of a voltage difference between said third voltage and said fourth voltage.