Memory including logic for operating upon graphics primitives

1. A memory comprising: a plurality of memory banks, wherein each of said plurality of memory banks comprises: a memory array for storing data; a graphics primitive logic coupled to said memory array, said graphics primitive logic configured to perform a predetermined operation upon a plurality of graphics primitives stored in said memory array, said graphics primitive logic configured to iteratively perform said predetermined operation upon said plurality of graphics primitives responsive to a command receivable by said memory bank; and wherein each of said plurality of memory banks is coupled to a plurality of conductors, wherein one of the plurality of conductors conveys a logic command signal indicative of said predetermined graphics operation in addition to a standard dynamic random access memory control signal set.

2. The memory as recited in claim 1 wherein said memory array and said graphics primitive logic are integrated onto a single integrated circuit.

3. The memory as recited in claim 2 wherein said single integrated circuit comprises a dynamic random access memory.

4. The memory as recited in claim 1 wherein said graphics primitive logic comprises a plurality of control registers, wherein said plurality of control registers are programmable using said logic command signal and a plurality of predetermined addresses; wherein said control registers store an indication of a selected one of several predetermined graphics operations which will be performed by said graphics primitive logic.

5. The memory is recited in claim 1 wherein said memory array and said graphics primitive logic are configured onto a single inline memory module.

6. The memory is recited in claim 5 wherein said memory array comprises a plurality of dynamic random access memory modules.

7. The memory as recited in claim 6 wherein said command is received by said single inline memory module via said logic command signal provided in addition to a standard single inline memory module control signal set.

8. The memory as recited in claim 7 wherein said graphics primitive logic comprises a plurality of control registers programmable using said logic command signal and a plurality of predetermined addresses; wherein said control registers store an indication of a selected one of several predetermined graphics operations which will be performed by said graphics primitive logic.

9. The memory as recited in claim 1 wherein said predetermined operation comprises anti-aliasing.

10. The memory as recited in claim 1 wherein said predetermined operation comprises shading.

11. The memory as recited in claim 1, wherein said logic command signal is indicative that a particular read or write operation is a graphics command.

12. A method for performing a predetermined operation upon a plurality of graphics primitives in a computer system, the method comprising: storing said plurality of graphics primitives into a memory array within a memory bank; wherein a plurality of memory banks are comprised within a memory; wherein each of said plurality of memory banks includes a graphics primitive logic; transmitting a command signal in addition to a standard memory control signal set to said memory bank subsequent to said storing via one of a plurality of conductors coupled to each of said plurality of memory banks, wherein said logic command signal is indicative of said predetermined graphics operation; and responsive to said logic command signal, iteratively performing said predetermined operation upon said plurality of graphics primitives by said graphics primitive logic.

13. The method as recited in claim 12 wherein said predetermined operation comprises anti-aliasing.

14. The method as recited in claim 12 wherein said predetermined operation comprises shading.

15. The method as recited in claim 12 wherein said memory and said graphics primitive logic are integrated into a dynamic random access memory, and wherein said logic command signal is in addition to a set of dynamic random access memory control signals.

16. The method as recited in claim 12 wherein said memory and said graphics primitive logic are integrated onto a single inline memory module, and wherein said logic command signal is conveyed from said conductor upon said single inline memory module to said graphics primitive logic.

17. The method as recited in claim 12 wherein said graphics primitive logic comprises a plurality of control registers, the method further comprising programming said plurality of control registers using said logic command signal; wherein said control registers store an indication of a selected one of several predetermined graphics operations which will be performed by said graphics primitive logic.

18. The method as recited in claim 12 further comprising transferring said plurality of graphics primitives to a graphics controller within said computer system subsequent to said iteratively performing.

19. A computer system comprising: a microprocessor; a bus bridge coupled to said microprocessor; and a memory including a plurality of memory banks, wherein each of said plurality of memory banks comprises: a memory array for storing data; a graphics primitive logic coupled to said memory array, said graphics primitive logic configured to perform a predetermined operation upon a plurality of graphics primitives stored in said memory array, said graphics primitive logic configured to iteratively perform said predetermined operation upon said plurality of graphics primitives responsive to a command conveyed by said microprocessor subsequent to said microprocessor storing said plurality of graphics primitives into said memory array; wherein each of said plurality of memory banks is coupled to a plurality of conductors, wherein one of the plurality of conductors conveys a logic command signal indicative of said predetermined graphics operation in addition to a standard memory control signal set.