Pointer circuit with low surface requirement high speed and low power loss

1. A pointer circuit with a predetermined number of outputs and for selecting one output such that the one output alone is in a determined one logical state of two logically distinguishable states, while all other outputs are in the other logical state and are not selected, and for changing the one logical state from the one output to an output immediately adjacent to this output in response to inputting a clock signal, so that after this change the immediately adjacent output is in the one logical state and is the selected output, while all other outputs, are in the other logical state and are not selected, comprising: a plurality of static memories, each of said static memories having first and second memory terminals, the plurality of static memories being respectively associated with the number of outputs, each of said memories respectively having the first and second memory terminals complementary to one another, such that the terminals are always in first and second stored logical states that are different from one another; a respective static memory of said plurality of static memories having a predetermined memory terminal connected with a respective output that is associated with the respective static memory; a shift circuit connected with the predetermined memory terminal of each memory for producing a logical state at the predetermined memory terminal of a memory and for changing the logical state from the predetermined memory terminal of a first memory to a predetermined memory terminal of a second memory immediately adjacent to the first memory by inputting at least one clock signal, which simultaneously effect the change such that the predetermined memory terminal of one respective memory is in one of the first and second logical states, and such that the predetermined memory terminals of all other memories are in the other of the first and second logical states.

2. The circuit according to claim 1, wherein the shift circuit comprises for each respective memory: a controllable switch, which is connected between a first memory terminal of the respective memory and a reference terminal for applying a reference potential; the first controllable switch having a control input for applying a switching signal for closing and/or opening the first controllable switch; a second controllable switch, which is connected between the second memory terminal of the respective memory and a terminal for applying a control potential; the second controllable switch having a control input for applying a switching signal for closing and/or opening the second controllable switch.

3. The circuit according to claim 2, wherein: each first controllable switch is individually allocated to a respective memory, which first controllable switch is connected with the first memory terminal of the respective memory, and is connected with a terminal for applying a potential; each second controllable switch is individually allocated to a respective memory, which second controllable switch is connected with the second memory terminal of the respective memory, and is connected with a terminal for applying a clock signal, such that these switches are connected successively in alternating fashion with a terminal for the application of a clock signal and with a terminal for the application of another clock signal; and the predetermined memory terminal of a respective memory is connected to the control input of a switch that is allocated to a memory immediately adjacent to the respective memory and is connected with the predetermined memory terminal of the immediately adjacent memory, and to the control input of a switch that is allocated to a another memory immediately adjacent to the one memory and is connected with the other memory terminal of this immediately adjacent other memory.

4. The circuit according to claim 3, wherein each controllable switch individually allocated to a respective memory, which switch is connected with the predetermined memory terminal of the respective memory, is connected with a terminal for the applying of a reference potential.

5. The circuit according to claim 3, wherein each controllable switch individually allocated to a respective memory, which switch is connected with the predetermined memory terminal of the respective memory, is connected with a terminal for applying an additional clock signal, such that these switches are connected successively in alternating fashion with a terminal for applying a further clock signal and with a terminal for applying a different additional clock signal.

6. The circuit according to claim 2, wherein: each first controllable switch is associated with a respective memory, which first controllable switch is connected with the first memory terminal of the respective memory, and is connected with a terminal for applying a potential; each second controllable switch is respectively associated with a respective memory, which second controllable switch is connected with the second memory terminal of the respective memory, and is connected with a terminal for applying a clock signal, such that these switches are connected successively in alternating fashion with a terminal for the application of a clock signal and with a terminal for the application of another clock signal; the predetermined memory terminal of a respective memory is connected to the control input of a switch that is associated with a memory immediately adjacent to the respective memory and is connected with the predetermined memory terminal of the immediately adjacent memory, and to the control input of a switch that is associated with a another memory immediately adjacent to the one memory and is connected with the other memory terminal of this immediately adjacent other memory; the predetermined memory terminal of a respective memory is connected to the control input of a switch that is associated with a memory immediately adjacent to the respective memory and is connected with the other memory terminal of this immediately adjacent memory; the control input of each switch is connected with a terminal for applying an additional clock signal such that the control inputs of the switches are connected successively in alternating fashion with a terminal for applying an additional clock signal and with a terminal for applying another additional clock signal.

7. The circuit according to claim 2, wherein: each first controllable switch is respectively associated with a respective memory, which first controllable switch is connected with the first memory terminal of the respective memory, and is connected with a terminal for applying a potential; each second controllable switch is respectively associated with a respective memory, which second controllable switch is connected with the second memory terminal of the respective memory, and is connected with a terminal for applying a clock signal, such that these switches are connected successively in alternating fashion with a terminal for the application of a clock signal and with a terminal for the application of another clock signal; the predetermined memory terminal of a respective memory is connected to the control input of a switch that is associated with a memory immediately adjacent to the respective memory and is connected with the predetermined memory terminal of the immediately adjacent memory, and to the control input of a switch that is allocated to a another memory immediately adjacent to the one memory and is connected with the other memory terminal of this immediately adjacent other memory; each second controllable switch is associated with a respective memory, which second controllable switch is connected with the second memory terminal of the respective memory, and is connected with a terminal for applying a determined reference potential; a terminal for applying a clock signal, with which is connected a predetermined controllable switch connected with the predetermined memory terminal of the respective memory, is connected via a controllable intermediate switch with the control terminal of the other memory terminal of a memory immediately adjacent to the respective memory; and the predetermined memory terminal of a respective memory is connected with the control terminal of the terminal for applying a clock signal, with which is connected the controllable switch connected with the predetermined memory terminal of the respective memory, and the intermediate switches connected with the other memory terminal of the memory immediately adjacent to the respective memory, and is connected with the control terminal of the switch connected with the predetermined memory terminal of another memory immediately adjacent to the respective memory.

8. The circuit according to claim 7, wherein each of the intermediate switches has a control characteristic complementary to the predetermined switch.

9. The circuit according to claim 7, wherein the other memory terminal of a respective memory is connected with a control input of a further intermediate switch that is connected between the control terminal and the other memory terminal of a memory immediately adjacent to the respective memory.

10. The circuit according to claim 2, wherein: each second controllable switch respectively associated with a respective memory, which switch is connected with the predetermined memory terminal of the respective memory, is connected with a terminal for applying a reference potential; a respective controllable switch is respectively associated with every second memory in a series of memories, which switch is connected with the other memory terminal of a next-but-one memory, and is connected with a terminal for applying of a clock signal; the predetermined memory terminal of each memory located between two adjacent next-but-one memories is connected with the control input of the switch connected with the predetermined memory output of an adjacent next-but-one memory and with the control input of the switch connected with the other memory output of the other adjacent next-but-one memory; and a respective additional switch with a respective control input for applying a switching impulse for closing and/or opening of the additional switch and with a control characteristic complementary to a respective switch is connected between the control input of the switch connected with the predetermined memory output of each next-but-one memory and a terminal for applying the clock signal, whereby the other memory terminal of the next-but-one memory is connected with the control input of the additional switch.

11. The circuit according to claim 2, wherein: each first controllable switch respectively associated with a respective memory, which switch is connected with the predetermined memory terminal of the respective memory, is connected with a terminal for applying a predetermined reference potential; each second controllable switch is respectively associated with a memory, which switch is connected with the other memory terminal of the respective memory, is connected with a terminal for applying the predetermined reference potential; an additional switch is connected between the control input of the switch connected with the other memory output of each memory and a terminal for applying a clock signal, with a respective control input for applying a switching impulse for closing and/or opening of the additional switch and with a control characteristic complementary to the respective switch, such that these additional switches are successively connected in alternating fashion with a terminal for applying a clock signal and with a terminal for applying another clock signal; and the control input of an additional memory allocated to a memory is connected with the other memory terminal of a memory immediately adjacent to the respective memory.