Devices and methods for testing cell margin of memory devices

1. A method for testing a semiconductor memory device, the memory device having a plurality of memory cells accessible by a plurality of word lines and bit lines, the memory device having preparatory and control circuitry for preparing and selecting ones of the memory cells, word lines, and bit lines for a write or read operation, one set of the memory cells being coupled to a sense amplifier via at least one bit line, individual memory cells being configured to store an electrical charge indicative of a binary 1 or 0, the binary I or O being written to and read from an individual memory cell by applying a voltage level to a word line and applying or measuring a data voltage level indicative of a binary 1 or 0 on a bit line, the writing and reading occurring during a cycle of sequential timing signals that activates at least in part the sense amplifier, a word line, a bit line, and the preparatory and control circuitry, the timing signals within a cycle occurring in a sequential order at selected start times after commencement of the cycle, the timing signals having selected durations after their respective start times, the timing signals having selected voltage levels, the method for testing comprising the following steps: writing and reading test information to and from the memory cells during a testing period; during the testing period, controllably adjusting at least one of (1) start times of the timing signals in relation to commencement of a cycle, (2) the durations of the timing signals, and (3) the voltage levels of the timing signals, the controlled adjustment of timings and voltage levels resulting in an alteration of the data voltage level on the bit line to be sensed by the sense amplifier such that, in a case that the memory device has a defect, the data voltage level will be altered to a degree that causes the sense amplifier to incorrectly sense test information written to or read from a memory cell and to output an erroneous value; comparing the test information input to and output from the memory cells; and generating an error signal if the test information read from the memory cells is not the same as the information written to the memory cells.

2. A method for testing a semiconductor memory device having a plurality of memory cells arranged in rows and columns, a plurality of word lines each coupled to the memory cells in one of the rows of memory cells for accessing the memory cells in the row, and a plurality of complementary pairs of bit lines, each pair being coupled to the memory cells in one of the columns of memory cells for writing to and reading from the memory cells in the column, the memory device also having an operational write cycle that includes activating one of the word lines to access the memory cells in one of the rows of memory cells, applying a data bit to one of the bit lines for storage in one of the accessed memory cells, and deactivating the activated word line to interrupt access to the accessed memory cells, the operational write cycle having an operation duration from activating one of the word lines to deactivating the activated word line, the method comprising: activating one of the word lines; applying a test bit to one of the bit lines; deactivating the activated word line when a period of time has elapsed since the activated word line was activated that is less than the operational duration of the operational write cycle; reading the test bit from the memory device; and comparing the test bit as read from the memory device to the test bit as applied to the one of the bit lines.

3. A method for testing a semiconductor memory device having a plurality of memory cells that may be accessed via a plurality of word lines and via a plurality of bit lines, the method comprising: activating one of the word lines; applying a test bit to one of the bit lines; prematurely deactivating the activated word line; reading the test bit from the memory device; and comparing the test bit as read from the memory device to the test bit as applied to the one of the bit lines.

4. The method of claim 3 wherein the step of prematurely deactivating the activated word line comprises deactivating the activated word line when a period of time has elapsed since the activated word line was activated that is substantially less than a duration of an operational write cycle of the memory device.

5. A method for testing a memory cell, the method comprising: accessing the memory cell; applying a test bit to the memory cell for storage therein; prematurely interrupting access to the memory cell before full storage of the test bit may take place; reading the test bit from the memory cell; and comparing the test bit as read from the memory cell to the test bit as applied to the memory cell.

6. The method of claim 5 wherein the step of accessing the memory cell comprises activating a word line coupled to the memory cell.

7. The method of claim 5 wherein the step of applying a test bit to the memory cell comprises applying the test bit to a bit line coupled to the memory cell.

8. The method of claim 5 wherein the step of prematurely interrupting access to the memory cell comprises interrupting access to the memory cell when a period of time has elapsed since the memory cell was accessed that is substantially less than a duration of an operational write cycle of the memory cell.

9. A method in a test system for stressing a memory cell, the method comprising: accessing the memory cell; applying a test bit to the accessed memory cell; and prematurely interrupting access to the accessed memory cell.

10. The method of claim 9 wherein the step of accessing the memory cell comprises activating a word line coupled to the memory cell.

11. The method of claim 9 wherein the step of applying a test bit to the accessed memory cell comprises applying the test bit to a bit line coupled to the accessed memory cell.

12. The method of claim 9 wherein the step of prematurely interrupting access to the accessed memory cell comprises interrupting access to the accessed memory cell when a period of time has elapsed since the accessed memory cell was accessed that is substantially less than a duration of an operational write cycle of the memory cell.

13. A method for testing a semiconductor memory device having a plurality of memory cells that may be accessed via a plurality of word lines and via a plurality of bit lines, the memory device also having operational activation voltage for the word lines, the method comprising: activating one of the word lines with a test activation voltage that is less than the operational activation voltage of the word lines; applying a test bit on one of the bit lines; deactivating the activated word line; reading the test bit from the memory device; and comparing the test bit as read from the memory device to the test bit as applied to the one of the bit lines.

14. A method for testing a memory cell, the method comprising: accessing the memory cell with a test activation voltage that is less than an operational activation voltage of the memory cell; applying a test bit to the memory cell for storage therein; interrupting access to the memory cell; reading the test bit from the memory cell; and comparing the test bit as read from the memory cell to the test bit as applied to the memory cell.

15. The method of claim 14 wherein the step of accessing the memory cell comprises activating a word line coupled to the memory cell.

16. The method of claim 14 wherein the step of applying a test bit to the memory cell comprises applying the test bit on a bit line coupled to the memory cell.

17. A method in a test system for stressing a memory cell, the method comprising: accessing the memory cell with a test activation voltage that is less than an operational activation voltage of the memory cell; applying a test bit to the accessed memory cell; and interrupting access to the accessed memory cell.

18. The method of claim 17 wherein the step of accessing the memory cell comprises activating a word line coupled to the memory cell.

19. The method of claim 17 wherein the step of applying a test bit to the accessed memory cell comprises applying the test bit to a bit line coupled to the memory cell.

20. A semiconductor memory device comprising: a plurality of memory cells; a plurality of word lines coupled to the memory cells: a plurality of bit lines coupled to the memory cells; circuitry coupled to the bit lines for applying data bits to the bit lines for storage in the memory cells; and circuitry coupled to the word lines for activating and then deactivating the word lines during operational write cycles of the memory device having an operational write cycle duration and for activating and then deactivating the word lines during test write cycles of the memory device having a test write cycle duration that is less than the operational write cycle duration.

21. The semiconductor memory device of claim 10 wherein the circuitry coupled to the bit lines and the circuitry coupled to the word lines comprise preparatory and control circuitry.

22. Circuitry in a semiconductor memory device adapted to stress memory cells in the memory device during a test write cycle of the memory device, the memory device having an operational write cycle that includes accessing a memory cell in the memory device and then interrupting access to the memory cell when an operational write cycle duration has elapsed, the stressing circuitry comprising circuitry adapted to access a memory cell in the memory device and to interrupt access to the accessed memory cell when a test write cycle duration has elapsed that than the operational write cycle duration.

23. A semiconductor memory device comprising: a plurality of memory cells; a plurality of word lines coupled to the memory cells; a plurality of bit lines coupled to the memory cells; circuitry coupled to the bit lines for applying data bits to the bit lines for storage in the memory cells; and circuitry coupled to the word lines for activating the word lines with operational activation voltage during operational write cycles of the memory device and for activating the word lines with a test activation voltage that is less than the operational activation voltage during test write cycles of the memory device.

24. The semiconductor memory device of claim 23 wherein the circuitry coupled to the bit lines and the circuitry coupled to the word lines comprise preparatory and control circuitry.

25. Circuitry in a semiconductor memory device for stressing memory cells in the memory device during a test write cycle of the memory device, the memory device having an operational write cycle in which memory cells are accessed with an operational activation voltage, the stressing circuitry comprising circuitry for accessing a memory cell in the memory device during the test write cycle of the memory device with a test activation voltage that is less than the operational activation voltage.

26. A system for testing a semiconductor memory device, the system comprising: word lines and bit lines; memory cells accessible through the word and bit lines; preparatory and control circuitry involved in preparing and selecting the memory cells, word lines, and bit lines for reading and writing operations; sense circuitry to selectively sense voltage levels in the memory cells; and signal generation circuitry to write said voltage levels into the memory cells and generate timing signals for the preparatory and control circuitry and the word lines, the timing signals having start time, duration, and voltage parameters, and the signal generation circuitry being adapted to adjust at least one of the parameters of at least some of the timing signals outside parameters associated with operating conditions for stressing the memory device such that the voltage levels to be sensed from particular ones of the memory cells that are associated with defects will significantly differ from the voltage levels written into such memory cells.