Dependency table for reducing dependency checking hardware

1. An apparatus for performing dependency checking in a superscalar microprocessor, comprising: a dependency table having a storage location for storing dependency information regarding a register, wherein said dependency information includes a first tag identifying an instruction which updates at least a portion of said register and a width identifying said portion of said register updated by said instruction, and wherein said instruction identified by said first tag is the most recent instruction in program order to update said register; and a control unit configured to detect dependencies between a set of concurrently decoded instructions and to assign a second tag for each source operand within said set of concurrently decoded instructions, wherein said second tag identifies one of said set of concurrently decoded instructions if said control unit detects an update of said source operand by said one of said set of concurrently decoded instructions, wherein said control unit is configured to supply said first tag from said storage location within said dependency table as said second tag if said source operand is stored in said register and said control unit does not detect an update of said source operand by said one of said set of concurrently decoded instructions.

2. The apparatus as recited in claim 1 wherein said dependency table includes multiple ones of said storage locations, wherein each of said multiple ones of said storage locations corresponds to a different register.

3. The apparatus as recited in claim 1 wherein said dependency information further includes a validity indication.

4. The apparatus as recited in claim 3 wherein said validity indication indicates invalid if said register is storing a value generated by said instruction.

5. The apparatus as recited in claim 3 wherein a value stored in said register is conveyed by said control unit instead of said second tag if said validity indication indicates invalid.

6. The apparatus as recited in claim 1 wherein said first tag identifies a second storage location within a reorder buffer, wherein said second storage location is storing said instruction.

7. The apparatus as recited in claim 6 wherein said second storage location stores a value to be stored into said register upon retirement of said instruction.

8. The apparatus as recited in claim 7 wherein said value is conveyed instead of said second tag if said value is stored in said second storage location upon decode of said set of concurrently decoded instructions.

9. The apparatus as recited in claim 6 wherein, upon detection of a mispredicted branch instruction within said reorder buffer, said dependency table is cleared of said dependency information.

10. The apparatus as recited in claim 9 wherein said dependency table is updated with dependency information corresponding to instructions prior to said mispredicted branch instruction in program order.

11. The apparatus as recited in claim 10 wherein said control unit is configured to stall a second set of concurrently decoded instructions if said second set of concurrently decoded instructions are decoded prior to completing update of said dependency table subsequent to a mispredicted branch instruction.

12. The apparatus as recited in claim 1 wherein said control unit is configured to compare said width to a second width indicative of said source operand.

13. The apparatus as recited in claim 12 wherein said second tag is set equal to said first tag if said second width is included within said first width.

14. The apparatus as recited in claim 12 wherein said control unit is configured to stall one of said set of concurrently decoded instructions for which said source operand is said register if said second width includes a second portion of said register excluded from said portion identified by said width.

15. The apparatus as recited in claim 14 wherein said control unit is further configured to stall additional ones of said set of concurrently decoded instructions, wherein said additional ones of said set of concurrently decoded instructions are subsequent to said one of said set of concurrently decoded instructions in program order.

16. The apparatus as recited in claim 1 wherein said dependency table is written prior to being read during a particular clock cycle.

17. The apparatus as recited in claim 16 wherein said control unit is configured to generate updated dependency information including said set of concurrently decoded instructions, and wherein said updated dependency information is stored into said dependency table.

18. The apparatus as recited in claim 17 wherein said updated dependency information is stored into a storage circuit upon generation during a first clock cycle, and is stored into said dependency table during a second clock cycle subsequent to said first clock cycle if said set of concurrently decoded instructions are not stalled by said control unit.

19. A method for performing dependency checking in a superscalar microprocessor, comprising: storing a first tag indicative of an instruction which updates at least a portion of a register into a dependency table, and further storing a width indicative of said portion, wherein said dependency table includes an entry corresponding to said register into which said first tag and said width are stored, and wherein said instruction identified by said first tag is the most recent instruction in program order to update said register; conveying source operands corresponding to a set of concurrently decoded instructions to said dependency table; and assigning a set of second tags to said source operands, wherein one of said set of second tags is equal to said first tag if a corresponding one of said source operands is stored in said register, and said one of said source operands is not updated by one of said set of concurrently decoded instruction said assigning comprising reading said first tag from said entry responsive to said one of said source operands.

20. The method as recited in claim 19 wherein said assigning further comprises comparing a second width identifying a second portion of said register which comprises said corresponding one of said source operands to said width.

21. The method as recited in claim 20 wherein said assigning further comprises stalling one of said set of concurrently decoded instructions having said corresponding one of said source operands if said second portion of said register includes a third portion excluded from said portion of said register corresponding to said width.