Signal processor for amplifying picture signals, and sampling and holding the amplified picture signals

1. A signal processor comprising: a dual correlation sampling circuit; and a sample-and-hold circuit connected to the output part of the dual correlation sampling circuit; said dual correlation sampling circuit comprising: an amplifying stage to which an input signal is given; a low-pass filter connected to the output part of the amplifying stage; a time constant changing switch to be closed to set the low-pass filter for a smaller time constant; and a switch driving means for closing the time constant changing switch after the completion of giving an input signal to the amplifying stage.

2. The signal processor according to claim 1, wherein the switch driving means closes the time constant changing switch upon the completion of application of a picture signal to the amplifying stage, and opens the time constant changing switch after the passage of a time in which the output of the low-pass filter stabilizes substantially, and the sample-and-hold circuit samples the output of the dual correlation sampling circuit after the time constant changing switch has been closed.

3. The signal processor according to claim 1, wherein the sample-and-hold circuit samples the output of the dual correlation sampling circuit a time equal to or longer than a time constant available while the low-pass filter is in an on-state after the time constant changing switch has been closed.

4. The signal processor according to claim 1, wherein the low-pass filter comprises a resistor and a capacitor; the time constant changing switch is connected in parallel to the resistor, and the resistor is short-circuited when the time constant changing switch is closed.

5. The signal processor according to claim 1 further comprising an input control means to be driven by the switch driving means to control the application of an input signal to the amplifying stage.

6. A signal processor comprising: a dual correlation sampling circuit; and a sample-and-hold circuit connected to the output part of the dual correlation sampling circuit; said dual correlation sampling circuit comprising: an amplifying stage to which an input signal is given; an input bias voltage application switch that connects a bias voltage source to and disconnect the same from the input part of the amplifying stage to which an input signal is given; a low-pass filter connected to the output part of the amplifying stage and comprising a resistor and a capacitor; a cutoff switch interposed between the resistor and the capacitor of the low-pass filter to connect the resistor to and disconnect the same from the capacitor; a dc regenerating capacitor having one electrode connected to the junction of the resistor and the cutoff switch; a reference power supply connecting switch connected to the other terminal of the dc regenerating capacitor and an output reference power supply; and a switch driving means for driving the switches so that the output reference power supply connecting switch is closed to connect the output reference power supply to the dc regenerating capacitor and the cutoff switch is opened to disconnect the resistor from the capacitor when the input bias voltage is applied to the amplifying stage for a first sampling cycle, and the output reference power supply connecting switch is opened and the cutoff switch is closed when a composite signal produced by superposing the input bias voltage and a picture signal is applied to the amplifying stage for a second sampling operation.

7. The signal processor according to claim 6, wherein the switch driving means closes the cutoff switch after opening the output reference power supply connecting switch.

8. The signal processor according to claim 6, wherein the dual correlation sampling circuit has an input reset switch connected to the input part of the amplifying stage and the input bias power source, and switch driving means controls the input reset switch so that the input part of the amplifying stage is connected to the input bias power supply before the first sampling cycle.

9. The signal processor according to claim 6, wherein the switch driving means opens the cutoff switch and the output reference power supply connecting switch when an excessive input that saturates the amplifying stage is given.

10. The signal processor according to claim 6 further comprising an operational amplifier having an input terminal connected to the other electrode of the dc regenerating capacitor connected to the reference power supply connecting switch.

11. A signal processor comprising: a first operational amplifier having a first input terminal to which an input is applied and a second input terminal; a first switch for connecting the first input terminal of the first operational amplifier to and disconnecting the same from a reference power supply; a second switch for connecting the second input terminal of the first operational amplifier to and disconnecting the same from the output terminal of the first operational amplifier; a first capacitor having an electrode connected to the second input terminal of the operational amplifier and the other electrode connected to the output reference power supply; a third switch interposed between the first capacitor and the output reference power supply; and a plurality of sample-and-hold main circuits each comprising a sample-and-hold capacitor and a buffer having an input terminal connected to the sample-and-hold capacitor; wherein the improvement comprises: sample-and-hold main circuit selector switches for connecting, when selected, the output terminal of the first operational amplifier to the sample-and-hold capacitors of the plurality of sample-and-hold main circuits, respectively; and negative feedback switches each for connecting the output terminal of the associated sample-and-hold main circuit to the junction of the first capacitor and the third switch when the associated sample-and-hold main circuit is selected by the sample-and-hold main circuit selector switch.

12. The signal processor according to claim 11 further comprising a second capacitor connected to the output terminal of the first operational amplifier, and the junction of the first capacitor and the third switch.

13. The signal processor according to claim 11, wherein the buffer is an operational amplifier.

14. The signal processor according to claim 11 further comprising a switch driving means for opening the second switch first when opening all the first, the second and the third switch in a closed state.