Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of fabricating an integrated circuit device comprising: providing a layer of gate silicon oxide over the surface of a semiconductor substrate; depositing a first layer of polysilicon overlying said gate silicon oxide layer; etching away said first polysilicon and said gate oxide layer where they are not covered by a mask to provide an opening to said semiconductor substrate where a planned buried contact junction will be formed; depositing a second polysilicon layer overlying said first polysilicon layer and said planned buried contact junction and doping said second polysilicon layer whereby said planned buried contact junction is formed in said semiconductor substrate underlying said doped second polysilicon layer; planarizing said second polysilicon layer; etching away said first and second polysilicon layers where they are not covered by a mask to provide an opening overlying a portion of said buried contact junction wherein a trench is etched into said semiconductor substrate where said semiconductor substrate is not covered by said gate oxide layer; depositing an oxide layer overlying said second polysilicon layer, said gate oxide layer exposed within said opening and within said trench; etching away said oxide layer where it is not covered by a mask wherein said trench and a portion of said second polysilicon layer overlying said buried contact junction and adjacent to said trench are exposed and whereby said oxide is removed from said trench; depositing a third polysilicon layer overlying said oxide layer and said second polysilicon layer and said trench exposed within said opening; and patterning said third polysilicon layer whereby said third polysilicon layer forms a butted contact with said second polysilicon layer exposed within said opening completing said fabrication of said integrated circuit device.
2. The method according to claim 1 wherein said first polysilicon layer has a thickness of between about 500 and 1000 Angstroms.
3. The method according to claim 1 wherein said second polysilicon layer has a thickness of between about 800 and 1500 Angstroms.
4. The method according to claim 1 wherein said first and second polysilicon layers are doped by in-situ doping.
5. The method according to claim 1 wherein said first and second polysilicon layers are doped by ion implantation.
6. The method according to claim 1 wherein said step of planarizing said second polysilicon layer is performed by chemical mechanical polishing.
7. The method according to claim 1 wherein said after said step of planarizing said second polysilicon layer the combined thickness of said first and second polysilicon layers is between about 1000 and 2500 Angstroms.
8. The method according to claim 1 wherein said trench has a depth of less than 1000 Angstroms.
9. The method according to claim 1 wherein said oxide layer has a thickness of between about 1000 and 2000 Angstroms.
10. The method according to claim 1 wherein said third polysilicon layer has a thickness of between about 500 and 1500 Angstroms.
11. The method according to claim 1 wherein said integrated circuit device is a four transistor SRAM device.
12. A method of fabricating an integrated circuit device having a conduction channel between a third polysilicon layer through a butted contact to an adjoining buried contact junction comprising: providing a layer of gate silicon oxide over the surface of a semiconductor substrate; depositing a first layer of polysilicon overlying said gate silicon oxide layer; etching away said first polysilicon and said gate oxide layer where they are not covered by a mask to provide an opening to said semiconductor substrate where a planned said buried contact junction will be formed; depositing a second polysilicon layer overlying said first polysilicon layer and said planned buried contact junction and doping said second polysilicon layer whereby said planned buried contact junction is formed in said semiconductor substrate underlying said doped second polysilicon layer; planarizing said second polysilicon layer by chemical mechanical polishing; etching away said first and second polysilicon layers where they are not covered by a mask to provide an opening overlying a portion of said buried contact junction wherein a trench is etched into said semiconductor substrate where said semiconductor substrate is not covered by said gate oxide layer; depositing an oxide layer overlying said second polysilicon layer, said gate oxide layer exposed within said opening and within said trench; etching away said oxide layer where it is not covered by a mask wherein said trench and a portion of said second polysilicon layer overlying said buried contact junction and adjacent to said trench are exposed and whereby said oxide is removed from said trench; depositing said third polysilicon layer overlying said oxide layer and said second polysilicon layer and said trench exposed within said opening; and patterning said third polysilicon layer whereby said third polysilicon layer forms said butted contact with said second polysilicon layer exposed within said opening completing said fabrication of said integrated circuit device having a conduction channel between said third polysilicon layer through said butted contact to adjoining said buried contact junction.
13. The method according to claim 12 wherein said first polysilicon layer has a thickness of between about 500 and 1000 Angstroms.
14. The method according to claim 12 wherein said second polysilicon layer has a thickness of between about 800and 1500 Angstroms.
15. The method according to claim 12 wherein said polysilicon layers are doped by in-situ doping.
16. The method according to claim 12 wherein said polysilicon layers are doped by ion implantation.
17. The method according to claim 12 wherein said after said step of planarizing said second polysilicon layer the combined thickness of said first and second polysilicon layers is between about 1000 and 2500 Angstroms.
18. The method according to claim 12 wherein said trench has a depth of less than 1000 Angstroms.
19. The method according to claim 12 wherein said oxide layer has a thickness of between about 1000 and 2000Angstroms.
20. The method according to claim 12 wherein said third polysilicon layer has a thickness of between about 500and 1500 Angstroms.
21. The method according to claim 12 wherein said integrated circuit device is a four transistor SRAM device.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
Unknown
September 19, 2000
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