Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor device comprising: a rectangular-shaped mounting board comprised of a pair of long sides and a pair of short sides extending perpendicular to said long sides, said mounting board having a plurality of wirings on its major surface, said wirings extending along said long sides, respectively; and a plurality of semiconductor memory devices mounted on said major surface of said mounting board, each of said semiconductor memory devices including: a rectangular-shaped semiconductor chip having a plurality of external terminals on its major surface, said semiconductor chip having a pair of long sides extending in a first direction and a pair of short sides extending in a second direction generally perpendicular to said first direction; said external terminals being arranged along one of said of long sides of the semiconductor chip; a plurality of first leads arranged along said one of said pair of long sides of the semiconductor chip, said first leads each including inner lead portions and outer lead portions, and the end portions of said inner lead portions being directly connected to corresponding external terminals; a plurality of second leads arranged along the other of said pair of long sides of the semiconductor chip, each said second leads are arranged opposite to one of said first leads, respectively, and including inner lead portions and outer lead portions, and said second lead portions being not directly connected to said semiconductor chip; a sealing body in which said semiconductor chip, the inner lead portions of said first leads, and the inner lead portions of said second leads are packaged, said sealing body being formed into a rectangular shape having a pair of long sides extending in said first direction and a pair of short sides extending in said second direction, the outer leads of said first leads protruding from one of the pair of long sides of said sealing body, and the outer leads of said second leads protruding from the other of said pair of long sides, wherein one of said first leads and one of said second leads are connected by one of said wirings, respectively.
2. A semiconductor device according to claim 1, wherein said one of said second leads is arranged opposite to said one of said first leads.
3. A semiconductor device according to claim 1, wherein all said second leads are arranged opposite to said first leads, respectively.
4. A semiconductor device according to claim 1, wherein said plurality of semiconductor memory devices are arranged along one of said long sides of said mounting board.
5. A semiconductor device according to claim 4, wherein said plurality of wirings are extended under said plurality of semiconductor memory devices.
6. A semiconductor device according to claim 5, wherein said plurality of wirings are arranged to parallel each other.
7. A semiconductor device according to claim 1, wherein one of said semiconductor memory devices and another one of said semiconductor devices are adjoined each other, said second leads of said one of said semiconductor memory devices and said first leads of said another one of said semiconductor memory devices being arranged closely adjacent to one another.
8. A semiconductor device according to claim 7, wherein said first leads and said second leads of said semiconductor memory devices are directly connected by said one of said wirings.
9. A semiconductor device according to claim 1, wherein said plurality of first leads and said second leads are bonded to said mounting board by solder.
10. A semiconductor device according to claim 1, further comprising: a plurality of connector terminals arranged along one of said shorter sides of said mounting board.
11. A semiconductor device according to claim 1, wherein eight of said semiconductor memory devices are mounted on said mounting board.
12. A semiconductor device according to claim 1, wherein said one of said wirings commonly inputs a signal to said plurality of devices.
13. A semiconductor device comprising: a mounting board having a plurality of wirings on its major surface; and a plurality of semiconductor memory devices mounted on said major surface of said mounting board, each of said semiconductor memory devices including: a rectangular-shaped semiconductor chip having a plurality of external terminals on its major surface, said semiconductor chip having a pair of long sides extending in a first direction and a pair of short sides extending in a second direction perpendicular to said first direction, and said external terminals being arranged along one of said pair of long sides of said semiconductor chip; a plurality of first leads arranged along said one of said pair of long sides of said semiconductor chip, said first leads each including inner lead portions and outer lead portions, and the end portions of said inner lead portions being directly connected to corresponding external terminals; a plurality of second leads arranged along the other of said pair of long sides of said semiconductor chip, each said second leads being arranged opposite to one of said first leads, respectively, and including inner lead portions and outer lead portions, and said second lead portions being not directly connected to said semiconductor chip; a sealing body in which said semiconductor chip, the inner lead portions of said first leads and the inner portions of said second leads are packaged, said sealing body being formed into a rectangular shape having a pair of long sides extending in said first direction and a pair of short sides extending in said second direction; the outer lead portions of said first leads protruding from one of the pair of long sides of said sealing body, and the outer lead portions of said second leads protruding from the other of said pair of long sides of said sealing body; wherein one of said first leads and one of said second leads which is opposite to said one of said first leads are connected to one another by a same wiring among said plurality of wirings.
14. A semiconductor device according to claim 13, wherein all said second leads are arranged in opposing relationship to said first leads, respectively.
15. A semiconductor device according to claim 13, wherein said plurality of wirings are extended under said plurality of semiconductor memory device and arranged along said second direction.
16. A semiconductor device according to claim 15, wherein said plurality of wirings are arranged to parallel each other.
17. A semiconductor device according to claim 15, wherein one of said semiconductor memory devices and another one of said semiconductor memory devices are adjoined to each other and mounted on said mounting board, said second leads of said one of said semiconductor memory devices and said first leads of said another one of said semiconductor memory devices being arranged closely adjacent to one another.
18. A semiconductor device according to claim 17, wherein said first leads and second leads of said semiconductor memory devices are connected by said same wiring.
19. A semiconductor device according to claim 13, wherein said plurality of first leads and said second leads are bonded to said mounting board by solder.
20. A semiconductor device according to claim 13, wherein eight semiconductor memory devices are mounted on said mounting board.
21. A semiconductor device according to claim 13, wherein said same wiring commonly inputs a signal to said plurality of semiconductor memory devices.
22. A semiconductor device comprising: a mounting board having a pair of long sides and a plurality of wirings on its major surface; and a first semiconductor memory device and a second semiconductor memory device mounted on said major surface of said mounting board, each of said first and said second semiconductor memory devices including: a rectangular-shaped semiconductor chip having a pair of long sides extending in a first direction and a pair of short sides extending in a second direction perpendicular to said first direction; a plurality of external terminals arranged on a major surface of said semiconductor chip and along one of said pair of long sides of said semiconductor chip; a plurality of first leads arranged along one of said pair of long sides of said semiconductor chip, said first leads each including inner lead portions and outer lead portions, and the end portions of said inner lead portions being directly connected to corresponding ones of said external terminals; a plurality of second leads arranged along the other of said pair of long sides of said semiconductor chip, each said second leads being arranged opposite to one of said first leads, respectively, and including inner lead portions and outer lead portions, and said second leads being not directly connected to said semiconductor chip; a sealing body in which said semiconductor chip, the inner lead portions of said first leads and the inner lead portions of said second leads are packaged, said sealing body being formed into a rectangular shape having a pair of long sides extending in said first direction and a pair of short sides extending in said second direction; the outer lead portions of said first leads protruding from one of the pair of long sides of said sealing body, and the outer lead portions of said second leads protruding from the other of said pair of long sides of said sealing body, wherein one of said first leads of said first memory device, one of said first leads of said second memory device and one of said second leads of said first memory device are all connected to a common wiring among said plurality of wirings.
23. A semiconductor device according to claim 22, wherein said common wiring is extended along in a direction where said first semiconductor device and said second semiconductor device are arranged.
24. A semiconductor device according to claim 23, wherein said common wiring is extended along said long sides of said semiconductor chip, linearly.
25. A semiconductor device according to claim 22, wherein said second leads of said first and said second semiconductor device are arranged opposite to said first leads of said first and said second semiconductor device, respectively.
26. A semiconductor device according to claim 22, wherein said wirings are extended under said first and said second semiconductor devices.
27. A semiconductor device according to claim 26, wherein said plurality of wirings are arranged to parallel each other.
28. A semiconductor device according to claim 22, wherein said first and said second semiconductor memory devices are adjoined to each other, said second leads of said first semiconductor memory device and said first leads of said second semiconductor memory device are arranged closely adjacent to one another.
29. A semiconductor device according to claim 22, wherein said plurality of outer lead portions of said first and said second leads are bonded to said mounting board by solder.
30. A semiconductor device according to claim 22, further comprising: a plurality of connector terminals arranged along one of said shorter sides of said mounting board.
31. A semiconductor device according to claim 22, wherein said wirings commonly input signals to said first and said second semiconductor memory devices.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
Unknown
September 19, 2000
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