Patentable/Patents/US-6125334
US-6125334

Module-configurable full-chip power profiler

PublishedSeptember 26, 2000
Assigneenot available in USPTO data we have
Inventorsnot available in USPTO data we have
Technical Abstract

Patent Claims
40 claims

Legal claims defining the scope of protection, as filed with the USPTO.

1

1. A method for determining the power consumption, resulting from execution of a block of code, of an integrated circuit that includes a processor module and one or more other circuit modules, comprising the steps of: storing a set of average current values for each of said modules, for a predetermined plurality of conditions having an effect on power consumption of said module, for each instruction in the instruction set of said processor module; for each module, for each instruction in a block of code to be executed on said processor module, testing said instruction to determine which of said conditions exist for said instruction, for each processor cycle; retrieving one of said average current values for each condition so tested that is met; and adding said average current values so retrieved.

2

2. A method for determining power consumption as in claim 1, wherein said step of adding is performed by accumulating said average current values so retrieved.

3

3. A method for determining power consumption as in claim 1, further including, in said step of providing a set of average current values, the step of providing a set of baseline average current values that are stored for a module for retrieval for all cycles when said module is powered to operate.

4

4. A method for determining power consumption as in claim 1, wherein said conditions include conditions for a memory module.

5

5. A method for determining power consumption as in claim 4, wherein two types of said conditions for said memory module are provided, a first type relating to the memory instruction mode, and a second type relating to data pattern dependencies.

6

6. A method for determining power consumption as in claim 1, wherein said conditions include conditions for an input/output (I/O) module.

7

7. A method for determining power consumption as in claim 6, wherein three types of said conditions for said input/output module are provided, a first type relating to output capacitance of said I/O module, a second type relating to the number of inputs of said I/O module that change during a cycle for an I/O instruction, and a third type relating to the number of outputs of said I/O module that change during a cycle for an I/O instruction.

8

8. A method for determining power consumption as in claim 1, wherein said conditions include conditions for a control logic module for said processor module.

9

9. A method for determining power consumption as in claim 8, wherein said integrated circuit includes a pipeline having a plurality of phases, and wherein three types of said conditions for said control logic module are provided, a first type relating to the number of bits changing on signal lines of said module, a second type relating to differentiating between modes of operation of said control module, and a third type relating to pipeline phase differences during a cycle.

10

10. A method for determining power consumption as in claim 1, wherein said conditions include conditions for a data buffer module.

11

11. A method for determining power consumption as in claim 10, wherein a baseline average current value is provided when a clock signal is provided to said data buffer module, and wherein said conditions for said data buffer module relate to the number of bits changing in said data buffer module during a cycle.

12

12. A method for determining power consumption as in claim 1, wherein said conditions include conditions for functional unit modules for said processor module.

13

13. A method for determining power consumption as in claim 12, wherein four types of said conditions for said functional unit modules are provided, a first type relating to what instruction executed in the cycle previous to a cycle under test, a second type relating to operational and data pattern factors for said functional unit and an instruction, a third type relating to pipeline phase differences during a cycle, and a fourth type relating to factors involved in the transfer of a result to a register during a cycle.

14

14. A method for determining power consumption as in claim 13, wherein said conditions include conditions for peripheral and interface modules for said processor module.

15

15. A method for determining power consumption as in claim 14, wherein two types of said conditions for said peripheral and interface modules are provided, a first type relating to the number of bits changing on signal lines of said peripheral and interface modules during a cycle, and a second type relating to the size of data transferred by said peripheral and interface modules during a cycle.

16

16. A method for determining power consumption as in claim 1, wherein said conditions include conditions for register modules for said processor module.

17

17. A method for determining power consumption as in claim 16, wherein three types of said conditions for said register modules are provided, a first type relating to the number of read operations done during a cycle, a second type relating to the number of write operations done during a cycle, and a third type relating to the number of bits changing during a cycle.

18

18. A method for determining power consumption as in claim 1, wherein said average current values are stored as a list.

19

19. A method for determining power consumption as in claim 1, wherein said average current values are stored as a values embedded in code.

20

20. A method for determining the power consumption, from execution of a block of code, of an integrated circuit that includes a processor module and one or more other circuit modules, comprising the steps of: providing a simulation tool that executes a model of each module, for each instruction executed in the instruction set of said processor module, and generates and stores a set of average current values for each module, for a predetermined plurality of sets of conditions selected for power consumption effect on the module and associated with said module, for each cycle, in sequence, of a block of code executing on said processor module; providing a current modeling program that tests a sequence of instructions for said set of conditions, and retrieves one of said average current values for each condition so tested that is met; providing a block of code, comprising a sequence of instructions; and determining the power consumed by the execution of said block of code by executing said current modeling program on said block of code, to retrieve appropriate ones of said average current values, for each module, resulting from the execution of said block of code, for each cycle of operation of said processor module, and adding said average current values so retrieved.

21

21. A method for determining power consumption as in claim 20, wherein said step of adding is performed by accumulating said average current values so retrieved.

22

22. A method for determining power consumption as in claim 20, wherein wherein said simulation tool performs simulation and characterization using module level transistor netlists with extracted parasitics.

23

23. A method for determining power consumption as in claim 20, wherein.

24

24. A method for determining power consumption as in claim 20, wherein said average current values are stored as a list.

25

25. A method for determining power consumption as in claim 20, wherein said average current values are stored as a values embedded in code.

26

26. A method for determining power consumption as in claim 20, further including, in said step of providing a set of average current values, the step of providing a set of baseline average current values that are stored for a module for retrieval for all cycles when said module is powered to operate.

27

27. A method for determining power consumption as in claim 20, wherein said conditions include conditions for a memory module.

28

28. A method for determining power consumption as in claim 27, wherein two types of said conditions for said memory module are provided, a first type relating to the memory instruction mode, and a second type relating to data pattern dependencies.

29

29. A method for determining power consumption as in claim 20, wherein said conditions include conditions for an input/output (I/O) module.

30

30. A method for determining power consumption as in claim 29, wherein three types of said conditions for said input/output module are provided, a first type relating to output capacitance of said I/O module, a second type relating to the number of inputs of said I/O module that change during a cycle for an I/O instruction, and a third type relating to the number of outputs of said I/O module that change during a cycle for an I/O instruction.

31

31. A method for determining power consumption as in claim 20, wherein said conditions include conditions for a control logic module for said processor module.

32

32. A method for determining power consumption as in claim 31, wherein said integrated circuit includes a pipeline having a plurality of phases, and wherein three types of said conditions for said control logic module are provided, a first type relating to the number of bits changing on signal lines of said module, a second type relating to differentiating between modes of operation of said control module, and a third type relating to pipeline phase differences during a cycle.

33

33. A method for determining power consumption as in claim 20, wherein said conditions include conditions for a data buffer module.

34

34. A method for determining power consumption as in claim 33, wherein a baseline average current value is provided when a clock signal is provided to said data buffer module, and wherein said conditions for said data buffer module relate to the number of bits changing in said data buffer module during a cycle.

35

35. A method for determining power consumption as in claim 20, wherein said conditions include conditions for functional unit modules for said processor module.

36

36. A method for determining power consumption as in claim 35, wherein four types of said conditions for said functional unit modules are provided, a first type relating to what instruction executed in the cycle previous to a cycle under test, a second type relating to operational and data pattern factors for said functional unit and an instruction, a third type relating to pipeline phase differences during a cycle, and a fourth type relating to factors involved in the transfer of a result to a register during a cycle.

37

37. A method for determining power consumption as in claim 36, wherein said conditions include conditions for peripheral and interface modules for said processor module.

38

38. A method for determining power consumption as in claim 37, wherein two types of said conditions for said peripheral and interface modules are provided, a first type relating to the number of bits changing on signal lines of said peripheral and interface modules during a cycle, and a second type relating to the size of data transferred by said peripheral and interface modules during a cycle.

39

39. A method for determining power consumption as in claim 20, wherein said conditions include conditions for register modules for said processor module.

40

40. A method for determining power consumption as in claim 39, wherein three types of said conditions for said register modules are provided, a first type relating to the number of read operations done during a cycle, a second type relating to the number of write operations done during a cycle, and a third type relating to the number of bits changing during a cycle.

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Patent Metadata

Filing Date

Unknown

Publication Date

September 26, 2000

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