Gate-coupled structure for enhanced ESD input/output pad protection in CMOS ICs

1. An electrostatic discharge protection circuit comprising a static discharge input node, a first NMOS FET having its drain connected to said input node and its source and substrate connected to Vss, a first switch apparatus comprised of a first PMOS FET and a second NMOS FET having the source and substrate of the first PMOS FET connected to said input node, the drain and substrate of the second NMOS FET connected to Vss, the drain of the first PMOS FET connected at a junction to the drain of the second NMOS FET, and the gates of the first PMOS FET and of the second NMOS FET connected to Vdd and said junction connected to the gate of the first NMOS FET.

2. A circuit as defined in claim 1, further comprising a second PMOS FET having its drain connected to said input node and its source, substrate and gate connected to Vdd.

3. An electrostatic discharge protection circuit comprising a static discharge input node, a first PMOS FET having its drain connected to said input node and its source and substrate connected to Vdd, a first switch apparatus comprised of a first NMOS FET, a second NMOS FET and a second PMOS FET having the source and substrate of the first NMOS FET connected at a junction to the drain of the second PMOS FET, the source and substrate of the second PMOS FET connected to said input node, and the drain of the first NMOS FET connected to Vdd and said junction connected to the gate of the first PMOS FET, and the source and substrate of the second NMOS FET connected to the gate of the first NMOS FET, and the drain and gate of the second NMOS FET connected to Vdd.

4. A circuit as defined in claim 3, further comprising a third NMOS FET having its drain connected to said input node and its source, substrate and gate connected to Vss.

5. A circuit as defined in claim 2, further including a second switch apparatus comprised of a third NMOS FET, a fourth NMOS FET and a third PMOS FET having the source and substrate of the third NMOS FET connected at a junction to the drain of the third PMOS FET, the source and substrate of the third PMOS FET connected to said input node, and the drain of the third NMOS FET connected to Vdd and said junction connected to the gate of the second PMOS FET, and the source and substrate of the fourth NMOS FET connected to the gate of the third NMOS FET, and the drain and gate of the fourth NMOS FET connected to Vdd.

6. A circuit as defined in claim 2, further including a voltage divider circuit connected to the gate of the first NMOS FET.

7. A circuit as defined in claim 6 in which one leg of the voltage divider consists of a PMOS FET having its source and substrate connected to said input node, its gate connected to Vdd and its drain connected to the gate of the first NMOS FET, and an NMOS FET having its drain connected to the gate of the first NMOS FET, its source and substrate connected to Vss and its gate connected to Vdd, and a second leg of the voltage divider is formed of a PMOS FET having its source and substrate connected to the gate of the first NMOS FET, its drain connected to Vss and its gate connected to Vdd.

8. A circuit as defined in claim 4, further including a voltage divider circuit connected to the gate of the first PMOS FET.

9. A circuit as defined in claim 8 in which one leg of the voltage divider consists of a PMOS FET having its source and substrate connected to said input node, its gate connected to Vdd and its drain connected to the gate of the first PMOS FET, and an NMOS FET having its source and substrate connected to the gate of the first PMOS FET, its drain connected to Vdd and its gate connected to Vdd through the drain-source circuit of another NMOS FET having its gate connected to Vdd, and a second leg of the voltage divider is formed of an PMOS FET having its drain connected to the gate of the first PMOS FET, its source, substrate, and gate connected to Vdd.

10. A circuit as defined in claim 5, in which the first and second switch apparatuses form first legs of respective first and second voltage dividers, a second leg of the first voltage divider is formed of a PMOS FET having its source and substrate to the gate of the first NMOS FET, its drain connected to Vss and its gate connected to Vdd, and in which a second leg of a second voltage divider is formed of an PMOS FET having its drain connected to the gate of the first PMOS FET and its source, substrate and gate connected to Vdd.

11. An electrostatic discharge protection circuit comprising an NMOS FET having its drain connected to a static discharge input node and its source and substrate connected to Vss, and switch means for conducting positive polarity electrostatic current directly to the gate and drain of the NMOS FET thereby turning the NMOS FET into a conducting state, and conducting said current through its source-drain circuit to Vss.

12. A circuit as defined in claim 11 in which said switch means is a normally off PMOS FET.

13. A circuit as defined in claim 11 in which the switch means is a PMOS FET, the PMOS FET having its gate connected to Vdd, the source and substrate of the PMOS FET being connected to said input node, and the source and substrate of the NMOS FET of the inverter being connected to Vss.

14. An electrostatic discharge protection circuit comprising a PMOS FET having its drain connected to a static discharge input node and its source and substrate connected to Vdd, and switch means for conducting negative polarity electrostatic current directly to the gate and drain of the PMOS FET thereby turning the PMOS FET into a conducting state, and conducting said current through its source-drain circuit to Vdd.

15. A circuit as defined in claim 14 in which the switch means is a normally off NMOS FET.

16. A circuit as defined in claim 14 in which the switch means is an NMOS FET, the NMOS FET having its gate connected to Vdd, the source and substrate of the NMOS FET being connected to said input node, and the source and substrate of a second PMOS FET being connected to Vdd.